[PATCH] fdt: Fix fdt_pack_reg() on 64-bit platforms
When "memory" node is being processed in fdt_pack_reg() on ARM64
platforms, an unaligned bus access might happen, which leads to
"synchronous abort" CPU exception. Consider next dts example:
/ {
#address-cells = <2>;
#size-cells = <1>;
memory@8000 {
device_type = "memory";
reg = <0x0 0x8000 0x3ab0>,
<0x0 0xc000 0x4000>,
<0x8 0x8000 0x8000>;
};
};
After fdt_pack_reg() reads the first addr/size entry from such memory
node, the "p" pointer becomes 12 bytes shifted from its original value
(8 bytes for two address cells + 4 bytes for one size cell). So now it's
not 64-bit aligned, and an attempt to do 64-bit bus access to that
address will cause an abort like this:
"Synchronous Abort" handler, esr 0x9621, far 0xba235efc
This issue was originally reported by David Virag [1] who observed it
happening on Samsung Exynos7885 SoC (ARM64), and later the same issue
was observed on Samsung Exynos850 (ARM64).
Fix the issue by using put_unaligned_be64() helper, which takes care of
possible unaligned 64-bit accesses. That solution was proposed by Simon
Glass in the original thread [1].
[1] https://lists.denx.de/pipermail/u-boot/2023-July/522074.html
Fixes: 739a01ed8e02 ("fdt_support: fix an endian bug of fdt_fixup_memory_banks")
Suggested-by: Simon Glass
Reported-by: David Virag
Closes: https://lists.denx.de/pipermail/u-boot/2023-July/522074.html
Signed-off-by: Sam Protsenko
---
boot/fdt_support.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 090d82ee80a5..9844c70be806 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -421,13 +422,13 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64
*address, u64 *size,
for (i = 0; i < n; i++) {
if (address_cells == 2)
- *(fdt64_t *)p = cpu_to_fdt64(address[i]);
+ put_unaligned_be64(address[i], p);
else
*(fdt32_t *)p = cpu_to_fdt32(address[i]);
p += 4 * address_cells;
if (size_cells == 2)
- *(fdt64_t *)p = cpu_to_fdt64(size[i]);
+ put_unaligned_be64(size[i], p);
else
*(fdt32_t *)p = cpu_to_fdt32(size[i]);
p += 4 * size_cells;
--
2.39.2
Re: [PATCH 2/2] part: efi: Treat unused partition type GUID as a valid case
On Thu, Mar 28, 2024 at 8:07 PM Heinrich Schuchardt wrote:
>
> On 3/28/24 23:29, Sam Protsenko wrote:
> > Some platforms use the "unused" (all-zero) GUID as a partition type GUID
> > to make some partitions hidden from the OS. For example, Samsung phones
> > and other devices often have GPT partition tables like that, created by
> > their "gpt_builder" tool [1]. All partitions with FILESYS=0 value
> > (second column in [2] file) will be created in a way that:
> >1. Partition type GUID will be all-zero ("unused")
> >2. Attributes[48:49] bits will be set to 0 (whereas non-zero values
> > mean the partition is visible to the OS: 1=raw, 2=ext4, 3=f2fs)
>
> The UEFI specification is defining what a GPT partition table has to
> look like.
>
> According the specification partition type GUID
> ---- marks an "unused entry" in the
> partition table.
>
> An unused partition table entry cannot define a partition. It is one of
> the entries, that you skip over when enumerating via your patch 1/2.
>
> With this patch 128 partition table entries are printed for an image
> having a single partition.
>
> => part list host 0
>
> Partition Map for HOST device 0 -- Partition Type: EFI
>
> PartStart LBA End LBA Name
> Attributes
> Type GUID
> Partition GUID
>1 0x0800 0x0001f7ff "EFI system partition"
> attrs: 0x0005
> type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
> (system)
> guid: ee474198-4601-4d5c-81f0-54acf904dd40
>2 0x 0x ""
> attrs: 0x
> type: ----
> (----)
> guid: ----
> ...
>
> 128 0x 0x ""
> attrs: 0x
> type: ----
> (----)
> guid: ----
>
> This is definitively wrong.
>
> >
> > Although it's true that Linux kernel verifies the partition type GUID to
> > be non-zero (in block/partitions/efi.c, is_pte_valid() function), where
> > its U-Boot counterpart code was borrowed from originally, in case of
> > U-Boot we want to handle partitions with "unused" GUIDs the same way as
> > any other valid partitions, to allow the user to interact with those
> > (e.g. list partitions using "part list", be able to flash those via
> > fastboot, etc).
>
> You cannot interact with a non-existing partition.
>
> You may create a new partition in any empty slot that Samsung's tool has
> left in the partition table and then write to it. No patch is needed for
> this.
>
Thanks for reviewing! In case of Samsung's way of creating GPT tables,
those are actually real partitions (they just "hide" those by means of
setting their type GUIDs to 0), and it's possible to flash those and
interact with them in other ways. But I can see how it's not a
standard way of doing things. And because (as you pointed out) this
patch leads to undesirable effects on other platforms, I also think it
should be NAKed. That of course means it won't be possible to access
all partitions on downstream Samsung devices, but with upstream U-Boot
people will probably want to create an appropriate GPT table anyways.
> Best regards
>
> Heinrich
>
[snip]
[PATCH 2/2] part: efi: Treat unused partition type GUID as a valid case
Some platforms use the "unused" (all-zero) GUID as a partition type GUID
to make some partitions hidden from the OS. For example, Samsung phones
and other devices often have GPT partition tables like that, created by
their "gpt_builder" tool [1]. All partitions with FILESYS=0 value
(second column in [2] file) will be created in a way that:
1. Partition type GUID will be all-zero ("unused")
2. Attributes[48:49] bits will be set to 0 (whereas non-zero values
mean the partition is visible to the OS: 1=raw, 2=ext4, 3=f2fs)
Although it's true that Linux kernel verifies the partition type GUID to
be non-zero (in block/partitions/efi.c, is_pte_valid() function), where
its U-Boot counterpart code was borrowed from originally, in case of
U-Boot we want to handle partitions with "unused" GUIDs the same way as
any other valid partitions, to allow the user to interact with those
(e.g. list partitions using "part list", be able to flash those via
fastboot, etc).
[1] https://gitlab.com/Linaro/96boards/e850-96/tools/gpt/
[2]
https://gitlab.com/Linaro/96boards/e850-96/tools/gpt/-/blob/master/gpt_layout
Fixes: 07f3d789b9be ("Add support for CONFIG_EFI_PARTITION (GUID Partition
Table)")
Signed-off-by: Sam Protsenko
---
disk/part_efi.c | 21 +
1 file changed, 5 insertions(+), 16 deletions(-)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 4ce9243ef25c..6b138abae0a6 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -1166,28 +1166,17 @@ static gpt_entry *alloc_read_gpt_entries(struct
blk_desc *desc,
*/
static int is_pte_valid(gpt_entry * pte)
{
- efi_guid_t unused_guid;
+ /*
+* NOTE: Do not check unused (zero) GUIDs here, it's considered a valid
+* case in U-Boot.
+*/
if (!pte) {
log_debug("Invalid Argument(s)\n");
return 0;
}
- /* Only one validation for now:
-* The GUID Partition Type != Unused Entry (ALL-ZERO)
-*/
- memset(unused_guid.b, 0, sizeof(unused_guid.b));
-
- if (memcmp(pte->partition_type_guid.b, unused_guid.b,
- sizeof(unused_guid.b)) == 0) {
-
- log_debug("Found an unused PTE GUID at 0x%08X\n",
- (unsigned int)(uintptr_t)pte);
-
- return 0;
- } else {
- return 1;
- }
+ return 1;
}
/*
--
2.39.2
[PATCH 1/2] part: Check all partitions in part_get_info_by_name()
In part_get_info_by_name() the inability to get some partition info
shouldn't be a reason for dropping out of the loop. That might happen
e.g. if the partition is hidden or unused. An example of such case are
Samsung devices, where they use the "unused" GUID type
(----) to indicate that the partition
should be hidden from the OS. Such partitions might not be seen in
"part list" output, which creates "gaps" in numbering in between of the
visible partitions:
PartStart LBA End LBA Name
1 0x0400 0xa3ff "efs"
5 0x00026420 0x00026c1f "dtbo"
12 0x0003f390 0x0074738f "super"
In that case, the loop in part_get_info_by_name() would break after
partition #1, so any attempt to obtain "dtbo" or "super" partition will
fail. Fix that by continuing to iterate over the remaining partitions to
make sure none of the visible ones is missed. That makes "part" command
(e.g. "part start", "part size") able to work with such tables.
Fixes: 87b8530fe244 ("disk: part: implement generic function
part_get_info_by_name()")
Signed-off-by: Sam Protsenko
---
disk/part.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/disk/part.c b/disk/part.c
index 36b88205eca7..08c9331e059c 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -717,8 +717,11 @@ int part_get_info_by_name(struct blk_desc *desc, const
char *name,
for (i = 1; i < part_drv->max_entries; i++) {
ret = part_drv->get_info(desc, i, info);
if (ret != 0) {
- /* no more entries in table */
- break;
+ /*
+* Partition with this index can't be obtained, but
+* further partitions might be, so keep checking.
+*/
+ continue;
}
if (strcmp(name, (const char *)info->name) == 0) {
/* matched */
--
2.39.2
Re: [BUG] fdt_pack_reg in common/fdt_support.c can cause crash from unaligned access
[snip] > > So I suspect the answer might be that we have a problem here, on ARM. > > One solution might be to add a helper like put_unaligned_be64() which > uses a CONFIG to indicate whether 32-bit-aligned 64-bit read/write is > supported, and either just does the write, or calls > put_unaligned_be64(). > > Another option might be to adjust fdt_pack_reg() to write the cells > one at a time. > Hi Simon, David, Just stumbled upon the same issue on E850-96 board when trying to boot the kernel using `bootm' command. It's an ARM64 board (Exynos850 SoC). Did you by chance find any solution to this? Looks to me it actually needs some sort of fix. I wonder why more people don't see this error on other ARM64 board. Anyways, would be happy to help out fixing it, so please let me know if you have any advice on this. Thanks! > Regards, > Simon
Re: [PATCH] clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present
On Thu, Mar 7, 2024 at 6:04 PM Sam Protsenko wrote:
>
> Sometimes clocks provided to a consumer might not have .set_rate
> operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag
> set. In that case it's usually possible to find a parent up the tree
> which is capable of setting the rate (div, pll, etc). Implement a simple
> lookup procedure for such cases, to traverse the clock tree until
> .set_rate capable parent is found, and use that parent to actually
> change the rate. The search will stop once the first .set_rate capable
> clock is found, which is usually enough to handle most cases.
>
> Signed-off-by: Sam Protsenko
> ---
Hi Lukasz, Sean, Tom,
If this patch looks good to you and there are no outstanding comments,
can you please apply it? It's needed as a part of eMMC enablement for
E850-96 board, as eMMC gate (leaf) clock is specified as ciu clock in
dts, which requires further clock rate change propagation up to
divider clock.
Thanks!
> drivers/clk/clk-uclass.c | 16 ++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index ed6e60bc4841..755f05f34669 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -571,8 +571,20 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
> return 0;
> ops = clk_dev_ops(clk->dev);
>
> - if (!ops->set_rate)
> - return -ENOSYS;
> + /* Try to find parents which can set rate */
> + while (!ops->set_rate) {
> + struct clk *parent;
> +
> + if (!(clk->flags & CLK_SET_RATE_PARENT))
> + return -ENOSYS;
> +
> + parent = clk_get_parent(clk);
> + if (IS_ERR_OR_NULL(parent) || !clk_valid(parent))
> + return -ENODEV;
> +
> + clk = parent;
> + ops = clk_dev_ops(clk->dev);
> + }
>
> /* get private clock struct used for cache */
> clk_get_priv(clk, );
> --
> 2.39.2
>
Re: [PATCH 0/4] clk: exynos: Prepare clocks for eMMC enablement
Hi Lukasz, Sean, Tom, If there are no comments on this series, can you please apply it? Thanks! On Thu, Mar 7, 2024 at 8:18 PM Sam Protsenko wrote: > > This short series features a couple of Exynos850 clock driver fixes and > adds new clocks needed for further eMMC and SD card enablement. > > Sam Protsenko (4): > clk: exynos: Re-arrange clocks in Exynos850 CMU_TOP > clk: exynos: Don't expose prototypes for not used functions > clk: exynos: Fix incorrect clock lookup for non-top CMUs > clk: exynos: Add CMU_CORE and CMU_HSI for Exynos850 > > drivers/clk/exynos/clk-exynos850.c | 326 ++--- > drivers/clk/exynos/clk-pll.c | 6 +- > drivers/clk/exynos/clk-pll.h | 6 + > drivers/clk/exynos/clk.c | 47 +++-- > drivers/clk/exynos/clk.h | 70 +-- > 5 files changed, 384 insertions(+), 71 deletions(-) > > -- > 2.39.2 >
Re: [PATCH] clk: Fix error message in clk_get_bulk
On Sat, Mar 9, 2024 at 6:27 AM Jan Kiszka wrote:
>
> From: Jan Kiszka
>
> Fix a logical inversion of the printed text.
>
> Signed-off-by: Jan Kiszka
> ---
Reviewed-by: Sam Protsenko
> drivers/clk/clk-uclass.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index ed6e60bc484..78d8ea94c65 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -180,7 +180,7 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk
> *bulk)
> bulk_get_err:
> err = clk_release_all(bulk->clks, bulk->count);
> if (err)
> - debug("%s: could release all clocks for %p\n",
> + debug("%s: could not release all clocks for %p\n",
> __func__, dev);
>
> return ret;
> --
> 2.35.3
Re: [PATCH v3 0/2] Fix Android A/B backup
On Fri, Mar 8, 2024 at 1:24 PM McAllister, Colin wrote: > > > Ah, ok, I see you replied to my comment here. > > Yes, sorry. Outlook is terrible to send inline responses too. I figured > just adding responses in the patch contents would be better. Next time I'll > submit > my patch with a different email :) > > > So when that config option is not defined at all, the build still > > works, right? > > Yes, the default value for CONFIG_ANDROID_AB_BACKUP_OFFSET is 0x0, which > would evaluate to a false bool value in the if conditions. I did do some > testing with the config value not defined for my board and confirmed > back-up data is not used. > Looks good to me, thanks. > In your other emails you include your reviewed-by tag. For clarity, Am I > supposed to append my patches and upload a new version? This is my > first time contributing to u-boot, so I'm still learning the workflow. I > didn't see anything glancing through the "Sending patches" page in the > U-Boot documentation. > Welcome to the community! And thanks for your patches :) U-Boot workflow is quite similar to Linux kernel one. It's useful to collect all tags when sending out your next version. When the maintainer takes your patch, they usually also apply all R-b tags for the final patch version, so you only have to worry about that when sending out a new version. I know that U-Boot contributors are often using `patman' tool [1] for submitting patches (and corresponding updated versions), and I'm pretty sure it collects all pending tags automatically for you. FWIW, I'm not experienced with `patman', as I'm trying to use somehow unified submitting process for both U-Boot and Linux kernel, and I know that using `patman' is sometimes discouraged in Linux kernel community. [1] https://docs.u-boot.org/en/latest/develop/patman.html [snip]
Re: [PATCH v3 6/6] tee: remove common.h inclusion
On Mon, Mar 4, 2024 at 11:46 AM Igor Opaniuk wrote: > > The usage of the common.h include file is deprecated [1], and has already > been removed from several files. > Get rid of all inclusions in the "drivers/tee" directory, and replace it > with required include files directly where needed. > > [1] doc/develop/codingstyle.rst > > Signed-off-by: Igor Opaniuk > --- Reviewed-by: Sam Protsenko > > Changes in v2: > - Fixed chimp_optee.c:37:9: error: implicit declaration of function 'memset' > > drivers/tee/broadcom/chimp_optee.c | 3 ++- > drivers/tee/optee/core.c | 1 - > drivers/tee/optee/i2c.c| 1 - > drivers/tee/optee/rpmb.c | 1 - > drivers/tee/optee/supplicant.c | 2 +- > drivers/tee/sandbox.c | 2 +- > drivers/tee/tee-uclass.c | 1 - > 7 files changed, 4 insertions(+), 7 deletions(-) > > diff --git a/drivers/tee/broadcom/chimp_optee.c > b/drivers/tee/broadcom/chimp_optee.c > index 37f9b094f76..bd146ef2899 100644 > --- a/drivers/tee/broadcom/chimp_optee.c > +++ b/drivers/tee/broadcom/chimp_optee.c > @@ -3,9 +3,10 @@ > * Copyright 2020 Broadcom. > */ > > -#include > #include > #include > +#include > +#include > > #ifdef CONFIG_CHIMP_OPTEE > > diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c > index 47f845cffe3..5fc0505c788 100644 > --- a/drivers/tee/optee/core.c > +++ b/drivers/tee/optee/core.c > @@ -3,7 +3,6 @@ > * Copyright (c) 2018-2020 Linaro Limited > */ > > -#include > #include > #include > #include > diff --git a/drivers/tee/optee/i2c.c b/drivers/tee/optee/i2c.c > index ef4e10f9912..e3fb99897c5 100644 > --- a/drivers/tee/optee/i2c.c > +++ b/drivers/tee/optee/i2c.c > @@ -3,7 +3,6 @@ > * Copyright (c) 2020 Foundries.io Ltd > */ > > -#include > #include > #include > #include > diff --git a/drivers/tee/optee/rpmb.c b/drivers/tee/optee/rpmb.c > index 5bc13757ea8..bacced6af6c 100644 > --- a/drivers/tee/optee/rpmb.c > +++ b/drivers/tee/optee/rpmb.c > @@ -3,7 +3,6 @@ > * Copyright (c) 2018 Linaro Limited > */ > > -#include > #include > #include > #include > diff --git a/drivers/tee/optee/supplicant.c b/drivers/tee/optee/supplicant.c > index f9dd874b594..8a426f53ba8 100644 > --- a/drivers/tee/optee/supplicant.c > +++ b/drivers/tee/optee/supplicant.c > @@ -3,10 +3,10 @@ > * Copyright (c) 2018, Linaro Limited > */ > > -#include > #include > #include > #include > +#include > #include > > #include "optee_msg.h" > diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c > index ec66401878c..8ad7c09efdd 100644 > --- a/drivers/tee/sandbox.c > +++ b/drivers/tee/sandbox.c > @@ -2,7 +2,7 @@ > /* > * Copyright (C) 2018 Linaro Limited > */ > -#include > + > #include > #include > #include > diff --git a/drivers/tee/tee-uclass.c b/drivers/tee/tee-uclass.c > index 52412a4098e..0194d732193 100644 > --- a/drivers/tee/tee-uclass.c > +++ b/drivers/tee/tee-uclass.c > @@ -5,7 +5,6 @@ > > #define LOG_CATEGORY UCLASS_TEE > > -#include > #include > #include > #include > -- > 2.34.1 >
Re: [PATCH v3 2/2] android_ab: Fix ANDROID_AB_BACKUP_OFFSET
On Fri, Mar 8, 2024 at 11:50 AM Sam Protsenko
wrote:
>
> On Fri, Mar 8, 2024 at 11:00 AM Colin McAllister
> wrote:
> >
> > Currently, setting CONFIG_AB_BACKUP_OFFSET in a target's defconfig will
> > not actually enable the #if protected code in android_ab.c. This is
> > because "CONFIG_" should have been prepended to the config macro, or the
> > macros defined in kconfig.h could have been used.
> >
> > The code included by ANDROID_AB_BACKUP_OFFSET has been refactored to no
> > longer be conditionally compiled by preprocessor conditionals and
> > instead use C conditionals. This better aligns with the Linux kernel
> > style guide.
> >
> > Fixes: 3430f24bc6 ("android_ab: Try backup booloader_message")
> > Signed-off-by: Colin McAllister
> > Cc: Joshua Watt
> > Cc: Simon Glass
> > ---
> > v2:
> > - Replaced #if conditionals with C if conditionals
> > - Opted to use CONFIG_ANDROID_AB_BACKUP_OFFSET directly instead of
> > macros in kconfig.h as CONFIG_ANDROID_AB_BACKUP_OFFSET is not a
> > boolean or tristate value and doesn't have different values when
> > building SPL or TPL.
> > v3:
> > - Added "Fixes:" tag
>
> Can you please also address my comment about CONFIG_IS_ENABLED() in
> the previous mail? It might be just an answer if you think there are
> no issues with that, not necessarily v4.
>
Ok, I just saw your reply in patch #0. Given that you tested that this
change doesn't break any other boards/configuration (e.g. when the
mentioned config is not defined), feel free to add:
Reviewed-by: Sam Protsenko
> [snip]
Re: [PATCH v3 0/2] Fix Android A/B backup
On Fri, Mar 8, 2024 at 11:00 AM Colin McAllister wrote: > > - Addresses compiler error due to missing semicolon > - Removes use of preprocessor macros with ANDROID_AB_BACKUP_OFFSET > > Bug was found by noticing a semicolon was missing and not causing a > compiler error when CONFIG_ANDROID_AB_BACKUP_OFFSET was set. I submitted > a patch to fix the semicolon before fixing the #if's. Testing the latter > patch without the former with ANDORID_AB_BACKUP_OFFSET set will cause a > compiler error. > > What's changed in V2? > - > > The second verison of changes removes the #if preprocessor macros to use > C conditionals instead. There was some minor refactoring required to get > this to work, so I did more thourough testing to ensure the backup data > works as expected. > > I also realized that CONFIG_VAL is not needed because there's no reason > for the SPL or TPL to have different values for the backup address. I > opted to just use CONFIG_ANDROID_AB_BACKUP_OFFSET directly. > > What's changed in V3? > - > > Added "Fixes:" tag to patches. Performed additonal testing as described > in the second paragraph in the testing notes below. > > I opted to not use CONFIG_IS_ENABLED because that macro appears to only > be intended for y/n configurations. See note at top of linux/kconfig.h: > > "Note that these only work with boolean and tristate options." Ah, ok, I see you replied to my comment here. So when that config option is not defined at all, the build still works, right? One way to test that would be to use buildman tool for all boards. Although I have to say it might be very time consuming (I usually run it overnight), so I'm not asking you to do it in this case, it's just FYI. > > How was this patch series tested? > - > > I built for my target with CONFIG_ANDROID_AB_BACKUP_OFFSET set to > 0x1000. I first verified that the device can normally boot. I then ran > dd before rebooting to corrupt the primary data. I confirmed that the > backup was used to properly restore the primary. I then corrupted both > the primary and backup data and confirmed that the primary and backup > were both reinitialized to default values. Lastly, I corrupted the > backup data and not the primary data and confirmed that the backup was > restored the primary data. > > Addtionally, I disabled CONFIG_ANDROID_AB_BACKUP_OFFSET for my device > and confirmed that after I corrupt the primary data, no backup is used. > When the primary data is not corrupt, the device boots normally. This is > what I would expect, because CONFIG_ANDROID_AB_BACKUP_OFFSET's default > value is 0x0, which would evaluate to false for all C if conditions. > > Colin McAllister (2): > android_ab: Add missing semicolon > android_ab: Fix ANDROID_AB_BACKUP_OFFSET > > boot/android_ab.c | 97 ++- > 1 file changed, 45 insertions(+), 52 deletions(-) > > -- > 2.43.2 > > > > > CONFIDENTIALITY NOTICE: This email and any attachments are for the sole use > of the intended recipient(s) and contain information that may be Garmin > confidential and/or Garmin legally privileged. If you have received this > email in error, please notify the sender by reply email and delete the > message. Any disclosure, copying, distribution or use of this communication > (including attachments) by someone other than the intended recipient is > prohibited. Thank you.
Re: [PATCH v3 2/2] android_ab: Fix ANDROID_AB_BACKUP_OFFSET
On Fri, Mar 8, 2024 at 11:00 AM Colin McAllister
wrote:
>
> Currently, setting CONFIG_AB_BACKUP_OFFSET in a target's defconfig will
> not actually enable the #if protected code in android_ab.c. This is
> because "CONFIG_" should have been prepended to the config macro, or the
> macros defined in kconfig.h could have been used.
>
> The code included by ANDROID_AB_BACKUP_OFFSET has been refactored to no
> longer be conditionally compiled by preprocessor conditionals and
> instead use C conditionals. This better aligns with the Linux kernel
> style guide.
>
> Fixes: 3430f24bc6 ("android_ab: Try backup booloader_message")
> Signed-off-by: Colin McAllister
> Cc: Joshua Watt
> Cc: Simon Glass
> ---
> v2:
> - Replaced #if conditionals with C if conditionals
> - Opted to use CONFIG_ANDROID_AB_BACKUP_OFFSET directly instead of
> macros in kconfig.h as CONFIG_ANDROID_AB_BACKUP_OFFSET is not a
> boolean or tristate value and doesn't have different values when
> building SPL or TPL.
> v3:
> - Added "Fixes:" tag
Can you please also address my comment about CONFIG_IS_ENABLED() in
the previous mail? It might be just an answer if you think there are
no issues with that, not necessarily v4.
[snip]
Re: [PATCH v3 1/2] android_ab: Add missing semicolon
On Fri, Mar 8, 2024 at 11:00 AM Colin McAllister
wrote:
>
> Found a missing semicolon in code protected by a #if that will never
> evaluate to true due to a separate issue. Fixing this issue before
> addressing the #if.
>
> Fixes: 3430f24bc6 ("android_ab: Try backup booloader_message")
> Signed-off-by: Colin McAllister
> Cc: Joshua Watt
> Cc: Simon Glass
> ---
My R-b tag wasn't added in v3, adding it here so that whoever applies
this patch can add it as well:
Reviewed-by: Sam Protsenko
> v2: No changes
> v3: Added "Fixes:" tag
>
> boot/android_ab.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/boot/android_ab.c b/boot/android_ab.c
> index c9df6d2b4b..9a3d15ec60 100644
> --- a/boot/android_ab.c
> +++ b/boot/android_ab.c
> @@ -221,7 +221,7 @@ int ab_select_slot(struct blk_desc *dev_desc, struct
> disk_partition *part_info,
> #if ANDROID_AB_BACKUP_OFFSET
> crc32_le = ab_control_compute_crc(backup_abc);
> if (backup_abc->crc32_le != crc32_le) {
> - log_err("ANDROID: Invalid backup CRC-32 ")
> + log_err("ANDROID: Invalid backup CRC-32 ");
> log_err("expected %.8x, found %.8x),",
> crc32_le, backup_abc->crc32_le);
> #endif
> --
> 2.43.2
>
>
>
>
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> prohibited. Thank you.
[PATCH] Makefile: Improve generated_defconfig file handling
Commit 2027e99e61aa ("Makefile: Run defconfig files through the C
preprocessor") adds `generated_defconfig' file, but fails to clean that
up. It might be useful to have that file around after `make' is done,
but it's better to clean that up on `make clean'. Also we probably want
to hide it in `git status' list. This patch makes the described changes,
and also adds `-P' parameter to the CPP command that produces the
`generated_defconfig' to avoid generating linemarkers.
Signed-off-by: Sam Protsenko
Fixes: 2027e99e61aa ("Makefile: Run defconfig files through the C preprocessor")
---
.gitignore | 1 +
Makefile | 1 +
scripts/kconfig/Makefile | 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/.gitignore b/.gitignore
index 330148119264..d9a64d742fd7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -63,6 +63,7 @@ fit-dtb.blob*
/spl/
/tpl/
/defconfig
+/generated_defconfig
#
# Generated include files
diff --git a/Makefile b/Makefile
index a2bc9d590329..6fd0e92c7d5a 100644
--- a/Makefile
+++ b/Makefile
@@ -2205,6 +2205,7 @@ clean: $(clean-dirs)
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp'
\
-o -name 'dsdt_generated.c' \
+ -o -name 'generated_defconfig' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 5ce5845e8247..079add4d5dab 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -93,7 +93,7 @@ endif
endif
%_defconfig: $(obj)/conf
- $(Q)$(CPP) -nostdinc -I $(srctree) -undef -x assembler-with-cpp
$(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
+ $(Q)$(CPP) -nostdinc -P -I $(srctree) -undef -x assembler-with-cpp
$(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
$(Q)$< $(silent) --defconfig=generated_defconfig $(Kconfig)
# Added for U-Boot (backward compatibility)
--
2.39.2
[PATCH 4/4] clk: exynos: Add CMU_CORE and CMU_HSI for Exynos850
CMU_CORE generates clocks needed for eMMC enablement, and CMU_HSI
provides clocks for SD card and USB. Most of the code is copied from the
Linux kernel counterpart driver.
Signed-off-by: Sam Protsenko
---
drivers/clk/exynos/clk-exynos850.c | 252 +
1 file changed, 252 insertions(+)
diff --git a/drivers/clk/exynos/clk-exynos850.c
b/drivers/clk/exynos/clk-exynos850.c
index f11c1ff29bdd..0c09ba02de4a 100644
--- a/drivers/clk/exynos/clk-exynos850.c
+++ b/drivers/clk/exynos/clk-exynos850.c
@@ -13,6 +13,8 @@
enum exynos850_cmu_id {
CMU_TOP,
CMU_PERI,
+ CMU_CORE,
+ CMU_HSI,
};
/* CMU_TOP -
*/
@@ -24,9 +26,23 @@ enum exynos850_cmu_id {
#define PLL_CON3_PLL_SHARED0 0x014c
#define PLL_CON0_PLL_SHARED1 0x0180
#define PLL_CON3_PLL_SHARED1 0x018c
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS0x1014
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI0x1018
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS0x1020
+#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD0x1040
+#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD0x1044
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS0x1070
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
+#define CLK_CON_DIV_CLKCMU_CORE_BUS0x1820
+#define CLK_CON_DIV_CLKCMU_CORE_CCI0x1824
+#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
+#define CLK_CON_DIV_CLKCMU_CORE_SSS0x182c
+#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
+#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD0x184c
+#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD0x1850
#define CLK_CON_DIV_CLKCMU_PERI_BUS0x187c
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
@@ -36,6 +52,13 @@ enum exynos850_cmu_id {
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
+#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS0x2044
+#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
+#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
@@ -44,6 +67,25 @@ enum exynos850_cmu_id {
PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" };
PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" };
PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
+PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "dout_shared0_div4" };
+PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared1_div3" };
+PNAME(mout_core_mmc_embd_p)= { "clock-oscclk", "dout_shared0_div2",
+ "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "mout_mmc_pll",
+ "clock-oscclk", "clock-oscclk" };
+PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
+PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
+PNAME(mout_hsi_mmc_card_p) = { "clock-oscclk", "dout_shared0_div2",
+ "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "mout_mmc_pll",
+ "clock-oscclk", "clock-oscclk" };
+PNAME(mout_hsi_usb20drd_p) = { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
/* List of parent clocks for Muxes in CMU_TOP: for
[PATCH 3/4] clk: exynos: Fix incorrect clock lookup for non-top CMUs
Samsung clock drivers usually define the clock indices that are unique
per one CMU, but are not unique across all CMUs. That is, clock indices
start from 1 for each CMU, as provided in CMU bindings header. The way
the clock lookup via clk_get_by_index() works at the moment is by using
clk_of_xlate_default(), which returns globally non-unique clock ids for
for clocks registered with Samsung CCF API, which leads to incorrect
clocks being obtained. One way to fix that would be to make all clock
ids defined in the bindings header unique, but it'd make it incompatible
with Linux kernel bindings header. A better way to solve this issue is
to calculate the global clock id and use it when registering a clock
with clk_dm() and when obtaining it, in a custom .of_xlate function.
This patch adds an API for such mapping calculation, introducing the
necessary modifications to CMU registering functions in Samsung CCF.
Exynos850 clock driver (the only driver that uses Samsung CCF at the
moment) is modified accordingly, as it uses the changed API. So the
clock lookup with clk-exynos850.c driver is also fixed here.
The global clock id is calculated from CMU id and local clock id in
SAMSUNG_TO_CLK_ID() macro like this:
clk_id_global = cmu_id * 256 + clk_id_local
leaving a range of up to 256 clocks for each CMU. Then this mapping
macro is used in clk_dm() to register clocks using their global ids, and
in .of_xlate() to lookup the clock by its local id correctly. Because
.of_xlate() operation has a separate function for each CMU, it "knows"
the correct way of finding the correct clk_id_global by provided
clk_id_local.
Fixes: ff3e8b8c6c22 ("clk: exynos: Add Samsung clock framework")
Fixes: a36cc5e3ef4d ("clk: exynos: Add Exynos850 clock driver")
Signed-off-by: Sam Protsenko
---
drivers/clk/exynos/clk-exynos850.c | 18 +++---
drivers/clk/exynos/clk-pll.c | 6 ++--
drivers/clk/exynos/clk-pll.h | 2 +-
drivers/clk/exynos/clk.c | 43 ++--
drivers/clk/exynos/clk.h | 54 +++---
5 files changed, 95 insertions(+), 28 deletions(-)
diff --git a/drivers/clk/exynos/clk-exynos850.c
b/drivers/clk/exynos/clk-exynos850.c
index de4170cdc2f3..f11c1ff29bdd 100644
--- a/drivers/clk/exynos/clk-exynos850.c
+++ b/drivers/clk/exynos/clk-exynos850.c
@@ -10,6 +10,11 @@
#include
#include "clk.h"
+enum exynos850_cmu_id {
+ CMU_TOP,
+ CMU_PERI,
+};
+
/* CMU_TOP -
*/
/* Register Offset definitions for CMU_TOP (0x120e) */
@@ -124,7 +129,7 @@ static const struct samsung_clk_group top_cmu_clks[] = {
static int exynos850_cmu_top_probe(struct udevice *dev)
{
- return samsung_cmu_register_one(dev, top_cmu_clks,
+ return samsung_cmu_register_one(dev, CMU_TOP, top_cmu_clks,
ARRAY_SIZE(top_cmu_clks));
}
@@ -133,11 +138,13 @@ static const struct udevice_id exynos850_cmu_top_ids[] = {
{ }
};
+SAMSUNG_CLK_OPS(exynos850_cmu_top, CMU_TOP);
+
U_BOOT_DRIVER(exynos850_cmu_top) = {
.name = "exynos850-cmu-top",
.id = UCLASS_CLK,
.of_match = exynos850_cmu_top_ids,
- .ops= _clk_ops,
+ .ops= _cmu_top_clk_ops,
.probe = exynos850_cmu_top_probe,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -175,7 +182,8 @@ static const struct samsung_clk_group peri_cmu_clks[] = {
static int exynos850_cmu_peri_probe(struct udevice *dev)
{
- return samsung_register_cmu(dev, peri_cmu_clks, exynos850_cmu_top);
+ return samsung_register_cmu(dev, CMU_PERI, peri_cmu_clks,
+ exynos850_cmu_top);
}
static const struct udevice_id exynos850_cmu_peri_ids[] = {
@@ -183,11 +191,13 @@ static const struct udevice_id exynos850_cmu_peri_ids[] =
{
{ }
};
+SAMSUNG_CLK_OPS(exynos850_cmu_peri, CMU_PERI);
+
U_BOOT_DRIVER(exynos850_cmu_peri) = {
.name = "exynos850-cmu-peri",
.id = UCLASS_CLK,
.of_match = exynos850_cmu_peri_ids,
- .ops= _clk_ops,
+ .ops= _cmu_peri_clk_ops,
.probe = exynos850_cmu_peri_probe,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
index 4aacbc26b25d..542d577eaa6f 100644
--- a/drivers/clk/exynos/clk-pll.c
+++ b/drivers/clk/exynos/clk-pll.c
@@ -136,7 +136,7 @@ static struct clk *_samsung_clk_register_pll(void __iomem
*base,
return clk;
}
-void samsung_clk_register_pll(void __iomem *base,
+void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id,
const struct samsung_pll_clock *clk_list,
unsigned int nr_clk)
{
@@ -145,10 +145,12 @@ void samsung_clk_registe
[PATCH 0/4] clk: exynos: Prepare clocks for eMMC enablement
This short series features a couple of Exynos850 clock driver fixes and adds new clocks needed for further eMMC and SD card enablement. Sam Protsenko (4): clk: exynos: Re-arrange clocks in Exynos850 CMU_TOP clk: exynos: Don't expose prototypes for not used functions clk: exynos: Fix incorrect clock lookup for non-top CMUs clk: exynos: Add CMU_CORE and CMU_HSI for Exynos850 drivers/clk/exynos/clk-exynos850.c | 326 ++--- drivers/clk/exynos/clk-pll.c | 6 +- drivers/clk/exynos/clk-pll.h | 6 + drivers/clk/exynos/clk.c | 47 +++-- drivers/clk/exynos/clk.h | 70 +-- 5 files changed, 384 insertions(+), 71 deletions(-) -- 2.39.2
[PATCH 2/4] clk: exynos: Don't expose prototypes for not used functions
Samsung CCF is meant to be used from the clock drivers by calling the
CMU registration API, i.e.:
- samsung_cmu_register_one() -- for top-level CMU
- samsung_register_cmu() -- for the rest of CMUs
Functions for registering separate clocks is probably not going to be
very useful, and isn't used at the moment. Remove prototypes of those
functions to make the Samsung CCF interface more compact and clear.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/clk/exynos/clk-pll.h | 6 ++
drivers/clk/exynos/clk.c | 12 ++--
drivers/clk/exynos/clk.h | 16
3 files changed, 12 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
index bd79309fa1cf..00c750687072 100644
--- a/drivers/clk/exynos/clk-pll.h
+++ b/drivers/clk/exynos/clk-pll.h
@@ -15,9 +15,15 @@
#include
+struct samsung_pll_clock;
+
enum samsung_pll_type {
pll_0822x,
pll_0831x,
};
+void samsung_clk_register_pll(void __iomem *base,
+ const struct samsung_pll_clock *clk_list,
+ unsigned int nr_clk);
+
#endif /* __EXYNOS_CLK_PLL_H */
diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c
index 430767f072d8..14ccd2cba374 100644
--- a/drivers/clk/exynos/clk.c
+++ b/drivers/clk/exynos/clk.c
@@ -10,7 +10,7 @@
#include
#include "clk.h"
-void samsung_clk_register_mux(void __iomem *base,
+static void samsung_clk_register_mux(void __iomem *base,
const struct samsung_mux_clock *clk_list,
unsigned int nr_clk)
{
@@ -28,7 +28,7 @@ void samsung_clk_register_mux(void __iomem *base,
}
}
-void samsung_clk_register_div(void __iomem *base,
+static void samsung_clk_register_div(void __iomem *base,
const struct samsung_div_clock *clk_list,
unsigned int nr_clk)
{
@@ -46,7 +46,7 @@ void samsung_clk_register_div(void __iomem *base,
}
}
-void samsung_clk_register_gate(void __iomem *base,
+static void samsung_clk_register_gate(void __iomem *base,
const struct samsung_gate_clock *clk_list,
unsigned int nr_clk)
{
@@ -84,9 +84,9 @@ static const samsung_clk_register_fn
samsung_clk_register_fns[] = {
* Having the array of clock groups @clk_groups makes it possible to keep a
* correct clocks registration order.
*/
-void samsung_cmu_register_clocks(void __iomem *base,
-const struct samsung_clk_group *clk_groups,
-unsigned int nr_groups)
+static void samsung_cmu_register_clocks(void __iomem *base,
+ const struct samsung_clk_group *clk_groups,
+ unsigned int nr_groups)
{
unsigned int i;
diff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h
index 91a51b877a63..14e06b2030fb 100644
--- a/drivers/clk/exynos/clk.h
+++ b/drivers/clk/exynos/clk.h
@@ -179,22 +179,6 @@ struct samsung_clk_group {
unsigned int nr_clk;
};
-void samsung_clk_register_mux(void __iomem *base,
- const struct samsung_mux_clock *clk_list,
- unsigned int nr_clk);
-void samsung_clk_register_div(void __iomem *base,
- const struct samsung_div_clock *clk_list,
- unsigned int nr_clk);
-void samsung_clk_register_gate(void __iomem *base,
- const struct samsung_gate_clock *clk_list,
- unsigned int nr_clk);
-void samsung_clk_register_pll(void __iomem *base,
- const struct samsung_pll_clock *clk_list,
- unsigned int nr_clk);
-
-void samsung_cmu_register_clocks(void __iomem *base,
-const struct samsung_clk_group *clk_groups,
-unsigned int nr_groups);
int samsung_cmu_register_one(struct udevice *dev,
const struct samsung_clk_group *clk_groups,
unsigned int nr_groups);
--
2.39.2
[PATCH 1/4] clk: exynos: Re-arrange clocks in Exynos850 CMU_TOP
Group CMU_TOP clocks to make it easier to add the support for more CMUs.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/clk/exynos/clk-exynos850.c | 56 --
1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/clk/exynos/clk-exynos850.c
b/drivers/clk/exynos/clk-exynos850.c
index cf94a3e1b646..de4170cdc2f3 100644
--- a/drivers/clk/exynos/clk-exynos850.c
+++ b/drivers/clk/exynos/clk-exynos850.c
@@ -35,16 +35,7 @@
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
-static const struct samsung_pll_clock top_pure_pll_clks[] = {
- PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
- PLL_CON3_PLL_SHARED0),
- PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
- PLL_CON3_PLL_SHARED1),
- PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
- PLL_CON3_PLL_MMC),
-};
-
-/* List of parent clocks for Muxes in CMU_TOP */
+/* List of parent clocks for Muxes in CMU_TOP: for PURECLKCOMP */
PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" };
PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" };
PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" };
@@ -55,6 +46,17 @@ PNAME(mout_peri_uart_p) = { "clock-oscclk",
"dout_shared0_div4",
PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4",
"dout_shared1_div4", "clock-oscclk" };
+/* PURECLKCOMP */
+
+static const struct samsung_pll_clock top_pure_pll_clks[] = {
+ PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED0),
+ PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED1),
+ PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
+ PLL_CON3_PLL_MMC),
+};
+
static const struct samsung_mux_clock top_pure_mux_clks[] = {
MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
PLL_CON0_PLL_SHARED0, 4, 1),
@@ -64,15 +66,6 @@ static const struct samsung_mux_clock top_pure_mux_clks[] = {
PLL_CON0_PLL_MMC, 4, 1),
};
-static const struct samsung_mux_clock top_peri_mux_clks[] = {
- MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
- CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
- MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
- CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
- MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
- CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
-};
-
static const struct samsung_div_clock top_pure_div_clks[] = {
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
@@ -88,13 +81,15 @@ static const struct samsung_div_clock top_pure_div_clks[] =
{
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
};
-static const struct samsung_div_clock top_peri_div_clks[] = {
- DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
- CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
- DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
- CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
- DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
- CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+/* PERI */
+
+static const struct samsung_mux_clock top_peri_mux_clks[] = {
+ MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
+ MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
+ MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
};
static const struct samsung_gate_clock top_peri_gate_clks[] = {
@@ -106,6 +101,15 @@ static const struct samsung_gate_clock
top_peri_gate_clks[] = {
CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
};
+static const struct samsung_div_clock top_peri_div_clks[] = {
+ DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
+ CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
+ DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
+ CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
+ DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
+ CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+};
+
static const struct samsung_clk_group top_cmu_clks[] = {
/* CMU_TOP_PURECLKCOMP */
{ S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) },
--
2.39.2
[PATCH] clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present
Sometimes clocks provided to a consumer might not have .set_rate
operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag
set. In that case it's usually possible to find a parent up the tree
which is capable of setting the rate (div, pll, etc). Implement a simple
lookup procedure for such cases, to traverse the clock tree until
.set_rate capable parent is found, and use that parent to actually
change the rate. The search will stop once the first .set_rate capable
clock is found, which is usually enough to handle most cases.
Signed-off-by: Sam Protsenko
---
drivers/clk/clk-uclass.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ed6e60bc4841..755f05f34669 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -571,8 +571,20 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
return 0;
ops = clk_dev_ops(clk->dev);
- if (!ops->set_rate)
- return -ENOSYS;
+ /* Try to find parents which can set rate */
+ while (!ops->set_rate) {
+ struct clk *parent;
+
+ if (!(clk->flags & CLK_SET_RATE_PARENT))
+ return -ENOSYS;
+
+ parent = clk_get_parent(clk);
+ if (IS_ERR_OR_NULL(parent) || !clk_valid(parent))
+ return -ENODEV;
+
+ clk = parent;
+ ops = clk_dev_ops(clk->dev);
+ }
/* get private clock struct used for cache */
clk_get_priv(clk, );
--
2.39.2
Re: [PATCH v2 2/2] android_ab: Fix ANDROID_AB_BACKUP_OFFSET
On Thu, Mar 7, 2024 at 4:11 PM Colin McAllister
wrote:
>
> Currently, setting CONFIG_AB_BACKUP_OFFSET in a target's defconfig will
> not actually enable the #if protected code in android_ab.c. This is
> because "CONFIG_" should have been prepended to the config macro, or the
> macros defined in kconfig.h could have been used.
>
I think this change deserves "Fixes:" tag. Also, please keep a
changelog under "---" stanza for each patch in the series starting
with v2, otherwise it's hard for reviewers to track the changes
between different versions.
> The code included by ANDROID_AB_BACKUP_OFFSET has been refactored to no
> longer be conditionally compiled by preprocessor conditionals and
> instead use C conditionals. This better aligns with the Linux kernel
> style guide.
>
> Signed-off-by: Colin McAllister
> Cc: Joshua Watt
> Cc: Simon Glass
> ---
> boot/android_ab.c | 97 ++-
> 1 file changed, 45 insertions(+), 52 deletions(-)
>
> diff --git a/boot/android_ab.c b/boot/android_ab.c
> index 9a3d15ec60..f547aa64e4 100644
> --- a/boot/android_ab.c
> +++ b/boot/android_ab.c
> @@ -187,13 +187,12 @@ int ab_select_slot(struct blk_desc *dev_desc, struct
> disk_partition *part_info,
>bool dec_tries)
> {
> struct bootloader_control *abc = NULL;
> + struct bootloader_control *backup_abc = NULL;
> u32 crc32_le;
> int slot, i, ret;
> bool store_needed = false;
> + bool valid_backup = false;
> char slot_suffix[4];
> -#if ANDROID_AB_BACKUP_OFFSET
> - struct bootloader_control *backup_abc = NULL;
> -#endif
>
> ret = ab_control_create_from_disk(dev_desc, part_info, , 0);
> if (ret < 0) {
> @@ -205,53 +204,49 @@ int ab_select_slot(struct blk_desc *dev_desc, struct
> disk_partition *part_info,
> return ret;
> }
>
> -#if ANDROID_AB_BACKUP_OFFSET
> - ret = ab_control_create_from_disk(dev_desc, part_info, _abc,
> - ANDROID_AB_BACKUP_OFFSET);
> - if (ret < 0) {
> - free(abc);
> - return ret;
> + if (CONFIG_ANDROID_AB_BACKUP_OFFSET) {
> + ret = ab_control_create_from_disk(dev_desc, part_info,
> _abc,
> +
> CONFIG_ANDROID_AB_BACKUP_OFFSET);
> + if (ret < 0) {
> + free(abc);
> + return ret;
> + }
> }
> -#endif
>
> crc32_le = ab_control_compute_crc(abc);
> if (abc->crc32_le != crc32_le) {
> log_err("ANDROID: Invalid CRC-32 (expected %.8x, found
> %.8x),",
> crc32_le, abc->crc32_le);
> -#if ANDROID_AB_BACKUP_OFFSET
> - crc32_le = ab_control_compute_crc(backup_abc);
> - if (backup_abc->crc32_le != crc32_le) {
> - log_err("ANDROID: Invalid backup CRC-32 ");
> - log_err("expected %.8x, found %.8x),",
> - crc32_le, backup_abc->crc32_le);
> -#endif
> -
> - log_err("re-initializing A/B metadata.\n");
> + if (CONFIG_ANDROID_AB_BACKUP_OFFSET) {
Did you test what happens if this config option is not defined at all?
Maybe it'd be better to use CONFIG_IS_ENABLED() instead, here and in
other cases like this?
> + crc32_le = ab_control_compute_crc(backup_abc);
> + if (backup_abc->crc32_le != crc32_le) {
> + log_err(" ANDROID: Invalid backup CRC-32 ");
> + log_err("(expected %.8x, found %.8x),",
> + crc32_le, backup_abc->crc32_le);
> + } else {
> + valid_backup = true;
> + log_info(" copying A/B metadata from
> backup.\n");
> + memcpy(abc, backup_abc, sizeof(*abc));
> + }
> + }
>
> + if (!valid_backup) {
> + log_err(" re-initializing A/B metadata.\n");
> ret = ab_control_default(abc);
> if (ret < 0) {
> -#if ANDROID_AB_BACKUP_OFFSET
> - free(backup_abc);
> -#endif
> + if (CONFIG_ANDROID_AB_BACKUP_OFFSET)
> + free(backup_abc);
> free(abc);
> return -ENODATA;
> }
> -#if ANDROID_AB_BACKUP_OFFSET
> - } else {
> - /*
> -* Backup is valid. Copy it to the primary
> -*/
> - memcpy(abc, backup_abc, sizeof(*abc));
> }
> -#endif
> store_needed = true;
> }
>
> if
Re: [PATCH v2 1/2] android_ab: Add missing semicolon
On Thu, Mar 7, 2024 at 4:11 PM Colin McAllister
wrote:
>
> Found a missing semicolon in code protected by a #if that will never
> evaluate to true due to a separate issue. Fixing this issue before
> addressing the #if.
>
> Signed-off-by: Colin McAllister
> Cc: Joshua Watt
> Cc: Simon Glass
> ---
> boot/android_ab.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/boot/android_ab.c b/boot/android_ab.c
> index c9df6d2b4b..9a3d15ec60 100644
> --- a/boot/android_ab.c
> +++ b/boot/android_ab.c
> @@ -221,7 +221,7 @@ int ab_select_slot(struct blk_desc *dev_desc, struct
> disk_partition *part_info,
> #if ANDROID_AB_BACKUP_OFFSET
> crc32_le = ab_control_compute_crc(backup_abc);
> if (backup_abc->crc32_le != crc32_le) {
> - log_err("ANDROID: Invalid backup CRC-32 ")
> + log_err("ANDROID: Invalid backup CRC-32 ");
Good catch! Wonder why there is also a trailing space in the end of
the string. Anyways, I think this patch deserves "Fixes:" tag, would
you mind adding it? Other than that:
Reviewed-by: Sam Protsenko
> log_err("expected %.8x, found %.8x),",
> crc32_le, backup_abc->crc32_le);
> #endif
> --
> 2.43.2
>
>
>
>
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Re: [PATCH v1] include: android_bootloader_message.h: sync with AOSP upstream
On Mon, Feb 19, 2024 at 4:16 AM Igor Opaniuk wrote:
>
> This takes the latest changes from AOSP from [1][2] (as this
> header was split on two) with minimal changes (this could lead
> to warnings reported by checkpatch).
Do we want to maybe follow that and also carry two different headers
in U-Boot? Or it doesn't make much sense? I'm thinking in terms of
future portability mostly: how easy it's to update this header right
now, and how easy it's going to be further. I didn't form any opinion
on that, hence asking.
Another thing: are you sure that changing only the header won't break
anything in U-Boot .c files that use this header?
>
> Some local changes have been applied:
Is it possible to split this work into two patches:
1. Bring the original changes only
2. Apply all necessary changes for U-Boot
Or does it break the build, etc? Again, thinking in terms of
portability easiness, and not sure which approach is better -- just
asking basically.
> 1. Enable static_assert() for defined structures to be sure
> that all of them have correct sizes.
> 2. Adjuste types in bootloader_control structure with bitfields
Adjuste -> adjust
> (uint8_t -> uint16_t). It seems that gcc just doesn't like bitfields
I wonder if all those extra changes can be upstreamed back to AOSP?
Ideally we'd want to just copy those headers over from AOSP to U-Boot
with no changes, would make the porting work easier. What are your
thoughts on that?
> that cross the width of the type. Changing the type doesn't change
> the layout though.
> This addresses this gcc note:
> In file included from boot/android_ab.c:7:
> include/android_bootloader_message.h:230:1: note: offset of packed bit-field
> ‘merge_status’ has changed in GCC 4.4
> 230 | } __attribute__((packed));
>
> [1]
> https://android.googlesource.com/platform/bootable/recovery/+/main/bootloader_message/include/bootloader_message/bootloader_message.h
> [2]
> https://android.googlesource.com/platform/hardware/interfaces/+/main/boot/1.1/default/boot_control/include/private/boot_control_definition.h
>
> CC: Alex Deymo
> CC: Sam Protsenko
> CC: Eugeniu Rosca
> CC: Simon Glass
> Signed-off-by: Igor Opaniuk
> ---
>
> include/android_bootloader_message.h | 104 +++
> 1 file changed, 92 insertions(+), 12 deletions(-)
>
> diff --git a/include/android_bootloader_message.h
> b/include/android_bootloader_message.h
> index 286d7ab0f31..75198fc9dc2 100644
> --- a/include/android_bootloader_message.h
> +++ b/include/android_bootloader_message.h
> @@ -21,17 +21,22 @@
> * stddef.h
> */
> #include
> +#include
> #endif
>
> // Spaces used by misc partition are as below:
> // 0 - 2K For bootloader_message
> // 2K - 16KUsed by Vendor's bootloader (the 2K - 4K range may be
> optionally used
> // as bootloader_message_ab struct)
> -// 16K - 64KUsed by uncrypt and recovery to store wipe_package for A/B
> devices
> +// 16K - 32KUsed by uncrypt and recovery to store wipe_package for A/B
> devices
> +// 32K - 64KSystem space, used for miscellanious AOSP features. See
> below.
> // Note that these offsets are admitted by bootloader,recovery and uncrypt,
> so they
> // are not configurable without changing all of them.
> static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
> +static const size_t VENDOR_SPACE_OFFSET_IN_MISC = 2 * 1024;
> static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
> +static const size_t SYSTEM_SPACE_OFFSET_IN_MISC = 32 * 1024;
> +static const size_t SYSTEM_SPACE_SIZE_IN_MISC = 32 * 1024;
>
> /* Bootloader Message (2-KiB)
> *
> @@ -81,24 +86,67 @@ struct bootloader_message {
> char reserved[1184];
> };
>
> +// Holds Virtual A/B merge status information. Current version is 1. New
> fields
> +// must be added to the end.
> +struct misc_virtual_ab_message {
> + uint8_t version;
> + uint32_t magic;
> + uint8_t merge_status; // IBootControl 1.1, MergeStatus enum.
> + uint8_t source_slot; // Slot number when merge_status was written.
> + uint8_t reserved[57];
> +} __attribute__((packed));
> +
> +struct misc_memtag_message {
> + uint8_t version;
> + uint32_t magic; // magic string for treble compat
> + uint32_t memtag_mode;
> + uint8_t reserved[55];
> +} __attribute__((packed));
> +
> +struct misc_kcmdline_message {
> + uint8_t version;
> + uint32_t magic;
> + uint64_t kcmdline_flags;
> + uint8_t reserved[51];
> +} __attribute__((packed));
> +
> +#define MISC_VIRTUAL_AB_MESSAGE_VERSION 2
> +#define MISC_VIRTUAL_AB_MAGIC_HEADER 0x56740AB0
> +
> +#define MISC_MEMTAG_MESSAGE_VERSION 1
> +#define MISC_MEMTAG_MAGIC_HEADER 0x5afefe5a
> +#define MISC
Re: [PATCH v2 00/13] arm: exynos: Add E850-96 board
Hey Tom, Minkyu,
If there are no outstanding concerns about this series, can you please apply it?
Thanks!
On Wed, Jan 10, 2024 at 9:09 PM Sam Protsenko
wrote:
>
> Add Exynos850 SoC and WinLink's E850-96 board support. A short overview
> of series additions and modifications:
> * USI driver: configures UART block
> * PMU driver: connects AP UART lines to uart1 pins)
> * Exynos850 clock driver: generates UART clocks
> * Exynos850 pinctrl driver: mux UART pins
> * serial_s5p: UART driver
> * Exynos850 SoC: dtsi files and MMU maps
> * E850-96 board: dts files, defconfig, board file and doc
>
> Most of the code was borrowed from mainline Linux kernel (where this
> board is already enabled) and adapted for U-Boot. Preliminary
> preparation for this series includes next patches / series (already
> merged):
>
> * commit 585a2aaac2ac ("arm: exynos: Include missing CPU header in
> soc.c")
> * commit c9ab9f30c8e4 ("arm: exynos: Include missing CPU header in
> gpio.h")
> * commit 11bd2787deff ("watchdog: s5p_wdt: Include missing CPU
> header")
> * commit 08cfa971a717 ("exynos: Avoid duplicate reset_cpu with
> SYSRESET enabled")
> * commit f655090901dc ("clk: exynos: Add header guard for clk-pll.h")
> * commit 2227f4c0afed ("serial: s5p: Fix clk_get_by_index() error code
> check")
> * commit a0615ffc99a5 ("serial: s5p: Remove common.h inclusion")
> * commit 5ad21de6bae0 ("serial: s5p: Use livetree API to get "id"
> property")
> * commit e79f630dbf67 ("serial: s5p: Use named constants for register
> values")
> * commit a627f2802a71 ("serial: s5p: Improve coding style")
> * commit 33e7ca5a9b6a ("serial: s5p: Use dev_read_addr_ptr() to get
> base address")
> * commit 6219b47c4d91 ("board: samsung: Fix SYS_CONFIG_NAME configs in
> axy17lte Kconfig")
> * commit 470682ace1e0 ("configs: Remove unneeded SYS_CONFIG_NAME from
> a*y17lte defconfigs")
>
> and series [1]. For more detailed description please see the board
> documentation (added in PATCH #12) and corresponding commit messages.
>
> Changes in v2:
> - PATCH 4: Removed unnecessary mode param
> - PATCH 4: Removed usi->dev and used priv data instead
> - PATCH 4: Used .of_plat_data callback for dts parsing
> - PATCH 7: Fixed Thomas Abraham e-mail
> - PATCH 9: Fixed incorrect driver description (comment)
> - Collected Reviewed-by tags
> - Rebased on top of most recent U-Boot/master
>
> [1] https://lists.denx.de/pipermail/u-boot/2023-November/539033.html
>
> Sam Protsenko (13):
> dt-bindings: soc: samsung: Add Exynos USI
> dt-bindings: soc: samsung: Add Exynos PMU
> dt-bindings: clock: Add Exynos850 clock controller
> soc: samsung: Add Exynos USI driver
> soc: samsung: Add Exynos PMU driver
> clk: exynos: Move pll code into clk-exynos7420
> clk: exynos: Add Samsung clock framework
> clk: exynos: Add Exynos850 clock driver
> pinctrl: exynos: Add pinctrl support for Exynos850
> serial: s5p: Add Exynos850 compatible
> arm: exynos: Add Exynos850 SoC support
> board: samsung: Add support for E850-96 board
> MAINTAINERS: Add new Samsung subsystems
>
> MAINTAINERS | 25 +
> arch/arm/dts/Makefile |1 +
> arch/arm/dts/exynos-pinctrl.h | 79 +
> arch/arm/dts/exynos850-e850-96-u-boot.dtsi| 37 +
> arch/arm/dts/exynos850-e850-96.dts| 273
> arch/arm/dts/exynos850-pinctrl.dtsi | 663 +
> arch/arm/dts/exynos850.dtsi | 809 +++
> arch/arm/mach-exynos/Kconfig | 28 +-
> arch/arm/mach-exynos/mmu-arm64.c | 34 +
> board/samsung/e850-96/Kconfig | 16 +
> board/samsung/e850-96/MAINTAINERS |9 +
> board/samsung/e850-96/Makefile|6 +
> board/samsung/e850-96/e850-96.c | 22 +
> configs/e850-96_defconfig | 21 +
> doc/board/samsung/e850-96.rst | 87 ++
> .../img/exynos850-boot-architecture.svg | 1283 +
> doc/board/samsung/index.rst |1 +
> .../clock/samsung,exynos850-clock.yaml| 307
> .../soc/samsung/exynos-pmu.yaml | 85 ++
> .../soc/samsung/exynos-usi.yaml | 162 +++
Re: [PATCH 2/2] MAINTAINERS: add Mattijs for Android AVB
On Fri, Jan 12, 2024 at 2:40 AM Mattijs Korpershoek wrote: > > Igor has not been active for quite some time on lore: > https://lore.kernel.org/all/?q=igor.opan...@gmail.com > > I'm interested in helping with maintaining the android_avb > command. I'm a long time android/aosp developer and my daily job is > still doing android work. > > Add myself as maintainer for Android AVB. > > Signed-off-by: Mattijs Korpershoek > --- Reviewed-by: Sam Protsenko > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 3c73d8c35c4a..4978470c1664 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -70,6 +70,7 @@ F:test/py/tests/test_android/test_ab.py > > ANDROID AVB > M: Igor Opaniuk > +M: Mattijs Korpershoek > S: Maintained > F: cmd/avb.c > F: common/avb_verify.c > > -- > 2.43.0 >
Re: [PATCH 1/2] MAINTAINERS: add Mattijs for Android AB
On Fri, Jan 12, 2024 at 2:40 AM Mattijs Korpershoek wrote: > > Igor has not been active for quite some time on lore: > https://lore.kernel.org/all/?q=igor.opan...@gmail.com > > I'm interested in helping with maintaining the android_ab > command. I'm a long time android/aosp developer and my daily job is > still doing android work. > > Add myself as maintainer for Android AB. > > Signed-off-by: Mattijs Korpershoek > --- Reviewed-by: Sam Protsenko > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 4fec063a242f..3c73d8c35c4a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -59,6 +59,7 @@ F:lib/acpi/ > > ANDROID AB > M: Igor Opaniuk > +M: Mattijs Korpershoek > R: Sam Protsenko > S: Maintained > F: boot/android_ab.c > > -- > 2.43.0 >
[PATCH v2 12/13] board: samsung: Add support for E850-96 board
Add support for WinLink E850-96 board [1]. It's based on Exynos850 SoC
and follows 96boards specification, so it's compatible with 96boards
mezzanine boards [2]. This patch enables next features:
* Serial console
* USI
* PMU (muxing AP UART path)
* Pinctrl
* Clocks
* Timer (ARMv8 architected)
* Reset control
It's quite a minimal enablement. Features like MMC, USB and Ethernet
will be enabled later.
The rationale for config values is as follows:
* TEXT_BASE = 0xf880
That's where BL2 loads the U-Boot payload, so TEXT_BASE must be
exactly this value. Overall the memory map is designed in a way to
keep the bootloader in the upper 128 MiB area of RAM, which is
0xf800..0x. That includes bootloader's code, stack,
data, heap, MMU tables, etc. All the memory below that 128 MiB chunk
can be used for storing boot images (0x8000..0xf800).
* CUSTOM_SYS_INIT_SP_ADDR = 0xf8c0
Just 4 MiB above the TEXT_BASE address, to leave enough space for
U-Boot code and stack itself (grows downwards).
* SYS_LOAD_ADDR = 0x8000
The beginning of RAM. That's where Linux kernel image must be
loaded.
* SYS_MALLOC_LEN = 0x81f000
8 MiB for malloc() + ENV_SIZE (128 KiB)
* SYS_MALLOC_F_LEN = 0x4000
Increase malloc() pool size available before relocation from 8 KiB
(default) to 16 KiB. Otherwise "alloc space exhausted" message
appears in U-Boot log during board_init_f() stage. There are next
reasons for doing so:
1. Having "bootph-all" flags in some dts nodes leads to binding
those during pre-relocation stage, and binding (DM) uses
dynamic memory allocation
2. clk-exynos850 driver uses CCF clocks, which in turn use dynamic
memory allocation
Device tree file was imported from Linux kernel. All nodes and boot
phase flags added in exynos850-e850-96-u-boot.dtsi are only needed to
enable serial console:
* oscclk -> cmu_top -> cmu_peri: generate UART/USI clocks
* pinctrl_alive and uart1_pins: needed to mux UART pins
* pmu_system_controller: configures AP UART path to uart1_pins
* usi_uart: configures USI block to operate as a UART protocol
* serial_0: enables serial console (UART)
[1] https://www.96boards.org/product/e850-96b/
[2] https://www.96boards.org/products/mezzanine/
Signed-off-by: Sam Protsenko
---
Changes in v2:
- (none)
arch/arm/dts/Makefile |1 +
arch/arm/dts/exynos850-e850-96-u-boot.dtsi| 37 +
arch/arm/dts/exynos850-e850-96.dts| 273
arch/arm/mach-exynos/Kconfig | 19 +-
board/samsung/e850-96/Kconfig | 16 +
board/samsung/e850-96/MAINTAINERS |9 +
board/samsung/e850-96/Makefile|6 +
board/samsung/e850-96/e850-96.c | 22 +
configs/e850-96_defconfig | 21 +
doc/board/samsung/e850-96.rst | 87 ++
.../img/exynos850-boot-architecture.svg | 1283 +
doc/board/samsung/index.rst |1 +
include/configs/e850-96.h | 12 +
13 files changed, 1786 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos850-e850-96-u-boot.dtsi
create mode 100644 arch/arm/dts/exynos850-e850-96.dts
create mode 100644 board/samsung/e850-96/Kconfig
create mode 100644 board/samsung/e850-96/MAINTAINERS
create mode 100644 board/samsung/e850-96/Makefile
create mode 100644 board/samsung/e850-96/e850-96.c
create mode 100644 configs/e850-96_defconfig
create mode 100644 doc/board/samsung/e850-96.rst
create mode 100644 doc/board/samsung/img/exynos850-boot-architecture.svg
create mode 100644 include/configs/e850-96.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 773c2546131c..84b8203e0f6a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
+dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
new file mode 100644
index ..7ad11e9faab2
--- /dev/null
+++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+
+_top {
+ bootph-all;
+};
+
+_peri {
+ bootph-all;
+};
+
+ {
+ bootph-all;
+};
+
+_alive {
+ bootph-all;
+};
+
+_system_controller {
+ bootph-all;
+ samsung,uart-debug-1;
+};
+
+_0 {
+ bootph-all;
+};
+
+_pins {
+ bootph-all;
+};
+
+_uart {
+ bootph-all;
+};
diff --git a/arch/arm/dts/exynos850-e850-96.dts
b/arch/arm/dts/exyn
[PATCH v2 11/13] arm: exynos: Add Exynos850 SoC support
Samsung Exynos850 is ARMv8-based mobile-oriented SoC. It features
Cortex-A55 CPU (8 cores) and it's built using 8nm process.
Add Exynos850 support by enabling next features:
* Import Exynos850 SoC dtsi files from Linux kernel
* Add Exynos850 MMU memory map
* Introduce ARCH_EXYNOS9 platform config option
Signed-off-by: Sam Protsenko
---
Changes in v2:
- (none)
arch/arm/dts/exynos-pinctrl.h | 79 +++
arch/arm/dts/exynos850-pinctrl.dtsi | 663 +++
arch/arm/dts/exynos850.dtsi | 809
arch/arm/mach-exynos/Kconfig| 9 +
arch/arm/mach-exynos/mmu-arm64.c| 34 ++
5 files changed, 1594 insertions(+)
create mode 100644 arch/arm/dts/exynos-pinctrl.h
create mode 100644 arch/arm/dts/exynos850-pinctrl.dtsi
create mode 100644 arch/arm/dts/exynos850.dtsi
diff --git a/arch/arm/dts/exynos-pinctrl.h b/arch/arm/dts/exynos-pinctrl.h
new file mode 100644
index ..7dd94a9b3652
--- /dev/null
+++ b/arch/arm/dts/exynos-pinctrl.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung Exynos DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski
+ */
+
+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+
+#define EXYNOS_PIN_PULL_NONE 0
+#define EXYNOS_PIN_PULL_DOWN 1
+#define EXYNOS_PIN_PULL_UP 3
+
+/* Pin function in power down mode */
+#define EXYNOS_PIN_PDN_OUT00
+#define EXYNOS_PIN_PDN_OUT11
+#define EXYNOS_PIN_PDN_INPUT 2
+#define EXYNOS_PIN_PDN_PREV3
+
+/*
+ * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885,
Exynos850
+ * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
+ */
+#define EXYNOS5420_PIN_DRV_LV1 0
+#define EXYNOS5420_PIN_DRV_LV2 1
+#define EXYNOS5420_PIN_DRV_LV3 2
+#define EXYNOS5420_PIN_DRV_LV4 3
+
+/* Drive strengths for Exynos5433 */
+#define EXYNOS5433_PIN_DRV_FAST_SR10
+#define EXYNOS5433_PIN_DRV_FAST_SR21
+#define EXYNOS5433_PIN_DRV_FAST_SR32
+#define EXYNOS5433_PIN_DRV_FAST_SR43
+#define EXYNOS5433_PIN_DRV_FAST_SR54
+#define EXYNOS5433_PIN_DRV_FAST_SR65
+#define EXYNOS5433_PIN_DRV_SLOW_SR18
+#define EXYNOS5433_PIN_DRV_SLOW_SR29
+#define EXYNOS5433_PIN_DRV_SLOW_SR30xa
+#define EXYNOS5433_PIN_DRV_SLOW_SR40xb
+#define EXYNOS5433_PIN_DRV_SLOW_SR50xc
+#define EXYNOS5433_PIN_DRV_SLOW_SR60xf
+
+/* Drive strengths for Exynos7 (except FSYS1) */
+#define EXYNOS7_PIN_DRV_LV10
+#define EXYNOS7_PIN_DRV_LV22
+#define EXYNOS7_PIN_DRV_LV31
+#define EXYNOS7_PIN_DRV_LV43
+
+/* Drive strengths for Exynos7 FSYS1 block */
+#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
+#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
+#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
+#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
+#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
+#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
+
+/* Drive strengths for Exynos850 GPIO_HSI block */
+#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */
+#define EXYNOS850_HSI_PIN_DRV_LV1_51 /* 1.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */
+#define EXYNOS850_HSI_PIN_DRV_LV2_53 /* 2.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */
+#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */
+
+#define EXYNOS_PIN_FUNC_INPUT 0
+#define EXYNOS_PIN_FUNC_OUTPUT 1
+#define EXYNOS_PIN_FUNC_2 2
+#define EXYNOS_PIN_FUNC_3 3
+#define EXYNOS_PIN_FUNC_4 4
+#define EXYNOS_PIN_FUNC_5 5
+#define EXYNOS_PIN_FUNC_6 6
+#define EXYNOS_PIN_FUNC_EINT 0xf
+#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */
diff --git a/arch/arm/dts/exynos850-pinctrl.dtsi
b/arch/arm/dts/exynos850-pinctrl.dtsi
new file mode 100644
index ..424bc80bde68
--- /dev/null
+++ b/arch/arm/dts/exynos850-pinctrl.dtsi
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (C) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
+ * tree nodes in this file.
+ */
+
+#include
+#include "exynos-pinctrl.h"
+
+_alive {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <>
[PATCH v2 13/13] MAINTAINERS: Add new Samsung subsystems
Add next Samsung subsystems with Sam Protsenko as a maintainer: - Samsung CCF Clock Framework - Exynos850 SoC Support - Samsung SoC Drivers Signed-off-by: Sam Protsenko --- Changes in v2: - (none) MAINTAINERS | 25 + 1 file changed, 25 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4fec063a242f..33e96cd4231f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -563,6 +563,31 @@ F: arch/arm/mach-exynos/ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ +ARM SAMSUNG CLOCK +M: Sam Protsenko +S: Maintained +F: drivers/clk/exynos/clk-pll.c +F: drivers/clk/exynos/clk-pll.h +F: drivers/clk/exynos/clk.c +F: drivers/clk/exynos/clk.h + +ARM SAMSUNG EXYNOS850 SOC +M: Sam Protsenko +S: Maintained +F: arch/arm/dts/exynos850-pinctrl.dtsi +F: arch/arm/dts/exynos850.dtsi +F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml +F: drivers/clk/exynos/clk-exynos850.c +F: drivers/pinctrl/exynos/pinctrl-exynos850.c +F: include/dt-bindings/clock/exynos850.h + +ARM SAMSUNG SOC DRIVERS +M: Sam Protsenko +S: Maintained +F: doc/device-tree-bindings/soc/samsung/* +F: drivers/soc/samsung/* +F: include/dt-bindings/soc/samsung,*.h + ARM SANCLOUD M: Paul Barker R: Marc Murphy -- 2.39.2
[PATCH v2 10/13] serial: s5p: Add Exynos850 compatible
Enable serial support for Exynos850 SoC by adding the corresponding
compatible string. No additional changes needed, the driver works as is
on Exynos850. Related USI and PMU configuration is enabled in separate
drivers. The only other dependencies are clock and pinctrl drivers,
which are already enabled too.
Signed-off-by: Sam Protsenko
---
Changes in v2:
- (none)
drivers/serial/serial_s5p.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 7d04dcff54fc..801b7645afa4 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -257,6 +257,7 @@ static const struct dm_serial_ops s5p_serial_ops = {
static const struct udevice_id s5p_serial_ids[] = {
{ .compatible = "samsung,exynos4210-uart", .data = PORT_S5P },
+ { .compatible = "samsung,exynos850-uart", .data = PORT_S5P },
{ .compatible = "apple,s5l-uart", .data = PORT_S5L },
{ }
};
--
2.39.2
[PATCH v2 09/13] pinctrl: exynos: Add pinctrl support for Exynos850
Add pinctrl support for Exynos850 SoC. It was mostly extracted from
corresponding Linux kernel code [1]. Power down modes and external
interrupt data were removed while converting the code for U-Boot, but
everything else was kept almost unchanged.
[1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
Signed-off-by: Sam Protsenko
Reviewed-by: Chanho Park
---
Changes in v2:
- Fixed driver description in the comment
- Added R-b tag
drivers/pinctrl/exynos/Kconfig | 8 ++
drivers/pinctrl/exynos/Makefile| 1 +
drivers/pinctrl/exynos/pinctrl-exynos850.c | 125 +
3 files changed, 134 insertions(+)
create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos850.c
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
index a60f49869b45..1b7fb62bc4ba 100644
--- a/drivers/pinctrl/exynos/Kconfig
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0
help
Support pin multiplexing and pin configuration control on
Samsung's Exynos78x0 SoC.
+
+config PINCTRL_EXYNOS850
+ bool "Samsung Exynos850 pinctrl driver"
+ depends on ARCH_EXYNOS && PINCTRL_FULL
+ select PINCTRL_EXYNOS
+ help
+ Support pin multiplexing and pin configuration control on
+ Samsung's Exynos850 SoC.
diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile
index 07db970ca942..3abe1226eb74 100644
--- a/drivers/pinctrl/exynos/Makefile
+++ b/drivers/pinctrl/exynos/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o
obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o
+obj-$(CONFIG_PINCTRL_EXYNOS850)+= pinctrl-exynos850.o
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c
b/drivers/pinctrl/exynos/pinctrl-exynos850.c
new file mode 100644
index ..3ec2636e0d87
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko
+ *
+ * Exynos850 pinctrl driver.
+ */
+
+#include
+#include
+#include "pinctrl-exynos.h"
+
+#define EXYNOS850_PIN_BANK(pins, reg, id) \
+ { \
+ .type = _bank_type, \
+ .offset = reg, \
+ .nr_pins= pins, \
+ .name = id\
+ }
+
+/* CON, DAT, PUD, DRV */
+static const struct samsung_pin_bank_type exynos850_bank_type = {
+ .fld_width = { 4, 1, 4, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
+static const struct pinctrl_ops exynos850_pinctrl_ops = {
+ .set_state = exynos_pinctrl_set_state
+};
+
+/* pin banks of exynos850 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks0[] = {
+ EXYNOS850_PIN_BANK(8, 0x000, "gpa0"),
+ EXYNOS850_PIN_BANK(8, 0x020, "gpa1"),
+ EXYNOS850_PIN_BANK(8, 0x040, "gpa2"),
+ EXYNOS850_PIN_BANK(8, 0x060, "gpa3"),
+ EXYNOS850_PIN_BANK(4, 0x080, "gpa4"),
+ EXYNOS850_PIN_BANK(3, 0x0a0, "gpq0"),
+};
+
+/* pin banks of exynos850 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos850_pin_banks1[] = {
+ EXYNOS850_PIN_BANK(1, 0x000, "gpm0"),
+ EXYNOS850_PIN_BANK(1, 0x020, "gpm1"),
+ EXYNOS850_PIN_BANK(1, 0x040, "gpm2"),
+ EXYNOS850_PIN_BANK(1, 0x060, "gpm3"),
+ EXYNOS850_PIN_BANK(1, 0x080, "gpm4"),
+ EXYNOS850_PIN_BANK(1, 0x0a0, "gpm5"),
+ EXYNOS850_PIN_BANK(1, 0x0c0, "gpm6"),
+ EXYNOS850_PIN_BANK(1, 0x0e0, "gpm7"),
+};
+
+/* pin banks of exynos850 pin-controller 2 (AUD) */
+static const struct samsung_pin_bank_data exynos850_pin_banks2[] = {
+ EXYNOS850_PIN_BANK(5, 0x000, "gpb0"),
+ EXYNOS850_PIN_BANK(5, 0x020, "gpb1"),
+};
+
+/* pin banks of exynos850 pin-controller 3 (HSI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks3[] = {
+ EXYNOS850_PIN_BANK(6, 0x000, "gpf2"),
+};
+
+/* pin banks of exynos850 pin-controller 4 (CORE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks4[] = {
+ EXYNOS850_PIN_BANK(4, 0x000, "gpf0"),
+ EXYNOS850_PIN_BANK(8, 0x020, "gpf1"),
+};
+
+/* pin banks of exynos850 pin-controller 5 (PERI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks5[] = {
+ EXYNOS850_PIN_BANK(2, 0x000, "gpg0"),
+ EXYNOS850_PIN_BANK(6, 0x020, "gpp0"),
+ EXYNOS850_PIN_BANK(4, 0x040, "gpp1"),
+ EXYNOS850_PIN_BANK(4, 0x060, "gpp2"),
+ EXYNOS8
[PATCH v2 08/13] clk: exynos: Add Exynos850 clock driver
Heavily influenced by its Linux kernel counterpart. It's implemented on
top of recently added Samsung CCF clock framework API. For now only UART
leaf clocks are implemented, along with all preceding clocks in CMU_TOP
and CMU_PERI. The UART baud clock is required in the serial driver, to
get its rate for the consequent baud rate calculation.
Signed-off-by: Sam Protsenko
Reviewed-by: Chanho Park
---
Changes in v2:
- Added R-b tag
drivers/clk/exynos/Kconfig | 7 ++
drivers/clk/exynos/Makefile| 1 +
drivers/clk/exynos/clk-exynos850.c | 189 +
3 files changed, 197 insertions(+)
create mode 100644 drivers/clk/exynos/clk-exynos850.c
diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
index eb0efa97d15c..85ce9d6e2418 100644
--- a/drivers/clk/exynos/Kconfig
+++ b/drivers/clk/exynos/Kconfig
@@ -15,4 +15,11 @@ config CLK_EXYNOS7420
This enables common clock driver support for platforms based
on Samsung Exynos7420 SoC.
+config CLK_EXYNOS850
+ bool "Clock driver for Samsung's Exynos850 SoC"
+ select CLK_CCF
+ help
+ This enables common clock driver support for platforms based
+ on Samsung Exynos850 SoC.
+
endmenu
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index 04c5b9a39e16..734100e2bff3 100644
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -9,3 +9,4 @@
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
+obj-$(CONFIG_CLK_EXYNOS850)+= clk-exynos850.o
diff --git a/drivers/clk/exynos/clk-exynos850.c
b/drivers/clk/exynos/clk-exynos850.c
new file mode 100644
index ..cf94a3e1b646
--- /dev/null
+++ b/drivers/clk/exynos/clk-exynos850.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung Exynos850 clock driver.
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko
+ */
+
+#include
+#include
+#include
+#include "clk.h"
+
+/* CMU_TOP -
*/
+
+/* Register Offset definitions for CMU_TOP (0x120e) */
+#define PLL_CON0_PLL_MMC 0x0100
+#define PLL_CON3_PLL_MMC 0x010c
+#define PLL_CON0_PLL_SHARED0 0x0140
+#define PLL_CON3_PLL_SHARED0 0x014c
+#define PLL_CON0_PLL_SHARED1 0x0180
+#define PLL_CON3_PLL_SHARED1 0x018c
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
+#define CLK_CON_DIV_CLKCMU_PERI_BUS0x187c
+#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
+#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
+
+static const struct samsung_pll_clock top_pure_pll_clks[] = {
+ PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED0),
+ PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED1),
+ PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
+ PLL_CON3_PLL_MMC),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP */
+PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" };
+PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" };
+PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
+PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
+PNAME(mout_peri_uart_p)= { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
+PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
+
+static const struct samsung_mux_clock top_pure_mux_clks[] = {
+ MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
+ PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_p
[PATCH v2 06/13] clk: exynos: Move pll code into clk-exynos7420
PLL utilities code is only used by clk-exynos7420 driver at the moment.
Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
clocks implementation, which is coming in the next patches.
Signed-off-by: Sam Protsenko
Reviewed-by: Chanho Park
---
Changes in v2:
- Added R-b tag
drivers/clk/exynos/Makefile | 1 -
drivers/clk/exynos/clk-exynos7420.c | 25 +-
drivers/clk/exynos/clk-pll.c| 32 -
drivers/clk/exynos/clk-pll.h| 13
4 files changed, 24 insertions(+), 47 deletions(-)
delete mode 100644 drivers/clk/exynos/clk-pll.c
delete mode 100644 drivers/clk/exynos/clk-pll.h
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index c9f29c873e9b..7faf238571ef 100644
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -3,5 +3,4 @@
# Copyright (C) 2016 Samsung Electronics
# Thomas Abraham
-obj-y += clk-pll.o
obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
diff --git a/drivers/clk/exynos/clk-exynos7420.c
b/drivers/clk/exynos/clk-exynos7420.c
index 7d869eb02b8e..9caa932e12fb 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -10,8 +10,15 @@
#include
#include
#include
+#include
#include
-#include "clk-pll.h"
+
+#define PLL145X_MDIV_SHIFT 16
+#define PLL145X_MDIV_MASK 0x3ff
+#define PLL145X_PDIV_SHIFT 8
+#define PLL145X_PDIV_MASK 0x3f
+#define PLL145X_SDIV_SHIFT 0
+#define PLL145X_SDIV_MASK 0x7
#define DIVIDER(reg, shift, mask) \
(((readl(reg) >> shift) & mask) + 1)
@@ -64,6 +71,22 @@ struct exynos7420_clk_top0_priv {
unsigned long sclk_uart2;
};
+static unsigned long pll145x_get_rate(unsigned int *con1,
+ unsigned long fin_freq)
+{
+ unsigned long pll_con1 = readl(con1);
+ unsigned long mdiv, sdiv, pdiv;
+ u64 fvco = fin_freq;
+
+ mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+ pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+ sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+ return (unsigned long)fvco;
+}
+
static ulong exynos7420_topc_get_rate(struct clk *clk)
{
struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
deleted file mode 100644
index 407fc71d415b..
--- a/drivers/clk/exynos/clk-pll.c
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Exynos PLL helper functions for clock drivers.
- * Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham
- */
-
-#include
-#include
-#include
-
-#define PLL145X_MDIV_SHIFT 16
-#define PLL145X_MDIV_MASK 0x3ff
-#define PLL145X_PDIV_SHIFT 8
-#define PLL145X_PDIV_MASK 0x3f
-#define PLL145X_SDIV_SHIFT 0
-#define PLL145X_SDIV_MASK 0x7
-
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
-{
- unsigned long pll_con1 = readl(con1);
- unsigned long mdiv, sdiv, pdiv;
- uint64_t fvco = fin_freq;
-
- mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
- pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
- sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
-
- fvco *= mdiv;
- do_div(fvco, (pdiv << sdiv));
- return (unsigned long)fvco;
-}
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
deleted file mode 100644
index 7b7af5e67612..
--- a/drivers/clk/exynos/clk-pll.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Exynos PLL helper functions for clock drivers.
- * Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham
- */
-
-#ifndef __EXYNOS_CLK_PLL_H
-#define __EXYNOS_CLK_PLL_H
-
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
-
-#endif /* __EXYNOS_CLK_PLL_H */
--
2.39.2
[PATCH v2 07/13] clk: exynos: Add Samsung clock framework
Heavily based on Linux kernel Samsung clock framework, with some changes
to accommodate the differences in U-Boot CCF implementation. It's also
quite minimal as compared to the Linux version.
Signed-off-by: Sam Protsenko
Reviewed-by: Chanho Park
---
Changes in v2:
- Corrected Thomas Abraham's e-mail
- Added R-b tag
drivers/clk/exynos/Makefile | 9 +-
drivers/clk/exynos/clk-pll.c | 167 +
drivers/clk/exynos/clk-pll.h | 23
drivers/clk/exynos/clk.c | 121 +++
drivers/clk/exynos/clk.h | 228 +++
5 files changed, 546 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/exynos/clk-pll.c
create mode 100644 drivers/clk/exynos/clk-pll.h
create mode 100644 drivers/clk/exynos/clk.c
create mode 100644 drivers/clk/exynos/clk.h
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index 7faf238571ef..04c5b9a39e16 100644
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -1,6 +1,11 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2016 Samsung Electronics
-# Thomas Abraham
+# Copyright (C) 2023 Linaro Ltd.
+#
+# Authors:
+# Thomas Abraham
+# Sam Protsenko
-obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
new file mode 100644
index ..4aacbc26b25d
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Copyright (C) 2023 Linaro Ltd.
+ *
+ * Authors:
+ * Thomas Abraham
+ * Sam Protsenko
+ *
+ * This file contains the utility functions to register the pll clocks.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define UBOOT_DM_CLK_SAMSUNG_PLL0822X "samsung_clk_pll0822x"
+#define UBOOT_DM_CLK_SAMSUNG_PLL0831X "samsung_clk_pll0831x"
+
+struct samsung_clk_pll {
+ struct clk clk;
+ void __iomem*con_reg;
+ enum samsung_pll_type type;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct samsung_clk_pll, clk)
+
+/*
+ * PLL0822x Clock Type
+ */
+
+#define PLL0822X_MDIV_MASK 0x3ff
+#define PLL0822X_PDIV_MASK 0x3f
+#define PLL0822X_SDIV_MASK 0x7
+#define PLL0822X_MDIV_SHIFT16
+#define PLL0822X_PDIV_SHIFT8
+#define PLL0822X_SDIV_SHIFT0
+
+static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(clk);
+ u32 mdiv, pdiv, sdiv, pll_con3;
+ u64 fvco = clk_get_parent_rate(clk);
+
+ pll_con3 = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
+ pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
+ sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll0822x_clk_min_ops = {
+ .get_rate = samsung_pll0822x_recalc_rate,
+};
+
+/*
+ * PLL0831x Clock Type
+ */
+
+#define PLL0831X_KDIV_MASK 0x
+#define PLL0831X_MDIV_MASK 0x1ff
+#define PLL0831X_PDIV_MASK 0x3f
+#define PLL0831X_SDIV_MASK 0x7
+#define PLL0831X_MDIV_SHIFT16
+#define PLL0831X_PDIV_SHIFT8
+#define PLL0831X_SDIV_SHIFT0
+#define PLL0831X_KDIV_SHIFT0
+
+static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(clk);
+ u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
+ s16 kdiv;
+ u64 fvco = clk_get_parent_rate(clk);
+
+ pll_con3 = readl_relaxed(pll->con_reg);
+ pll_con5 = readl_relaxed(pll->con_reg + 8);
+ mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
+ pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
+ sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
+ kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll0831x_clk_min_ops = {
+ .get_rate = samsung_pll0831x_recalc_rate,
+};
+
+static struct clk *_samsung_clk_register_pll(void __iomem *base,
+ const struct samsung_pll_clock *pll_clk)
+{
+ struct samsung_clk_pll *pll;
+ struct clk *clk;
+ const char *drv_name;
+ int ret;
+
+ pll = kzalloc(size
[PATCH v2 05/13] soc: samsung: Add Exynos PMU driver
Add basic Power Management Unit (PMU) driver for Exynos SoCs. For now
it's only capable of changing UART path in PMU, which is needed for
E850-96 board. The driver's structure resembles the exynos-pmu driver
from Linux kernel, and although it's very basic and slim at the moment,
it can be easily extended in future if the need arises.
UCLASS_NOP is used, as there are no benefits in using more elaborate
classes like UCLASS_MISC in this case. The DM_FLAG_PROBE_AFTER_BIND flag
is added in bind function, as the probe function must be always called
for this driver.
Signed-off-by: Sam Protsenko
Reviewed-by: Chanho Park
---
Changes in v2:
- Added R-b tag
drivers/soc/samsung/Kconfig | 10 +++
drivers/soc/samsung/Makefile | 1 +
drivers/soc/samsung/exynos-pmu.c | 102 +++
3 files changed, 113 insertions(+)
create mode 100644 drivers/soc/samsung/exynos-pmu.c
diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
index ffb87fe79316..737b7ca8cd19 100644
--- a/drivers/soc/samsung/Kconfig
+++ b/drivers/soc/samsung/Kconfig
@@ -5,6 +5,16 @@ menuconfig SOC_SAMSUNG
if SOC_SAMSUNG
+config EXYNOS_PMU
+ bool "Exynos PMU controller driver"
+ depends on ARCH_EXYNOS
+ select REGMAP
+ select SYSCON
+ help
+ Enable support for system controller configuration driver. It allows
+ one to configure system controller registers (e.g. some register in
+ PMU syscon) by providing register's offset, mask and value.
+
config EXYNOS_USI
bool "Exynos USI (Universal Serial Interface) driver"
depends on ARCH_EXYNOS
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
index 833ac073fbfa..0eb3ed8353b0 100644
--- a/drivers/soc/samsung/Makefile
+++ b/drivers/soc/samsung/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
new file mode 100644
index ..233ad4a908f5
--- /dev/null
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko
+ *
+ * Exynos PMU (Power Management Unit) driver.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EXYNOS850_UART_IO_SHARE_CTRL 0x0760
+#define SEL_RXD_AP_UART_SHIFT 16
+#define SEL_RXD_AP_UART_MASK GENMASK(17, 16)
+#define SEL_TXD_GPIO_1_SHIFT 20
+#define SEL_TXD_GPIO_1_MASKGENMASK(21, 20)
+#define RXD_GPIO_1 0x3
+#define TXD_AP_UART0x0
+
+struct exynos_pmu {
+ struct udevice *dev;
+ const struct exynos_pmu_data *pmu_data;
+ struct regmap *regmap;
+};
+
+struct exynos_pmu_data {
+ int (*pmu_init)(struct exynos_pmu *priv);
+};
+
+static int exynos850_pmu_init(struct exynos_pmu *priv)
+{
+ ofnode node;
+ bool uart_debug_1;
+ unsigned int offset, mask, value;
+
+ node = dev_ofnode(priv->dev);
+ uart_debug_1 = ofnode_read_bool(node, "samsung,uart-debug-1");
+ if (!uart_debug_1)
+ return 0;
+
+ /*
+* If uart1_pins are used for serial, AP UART lines have to be muxed
+* in PMU block to UART_DEBUG_1 path (GPIO_1). By default (reset value)
+* UART_DEBUG_0 path (uart0_pins) is connected to AP UART lines.
+*/
+ offset = EXYNOS850_UART_IO_SHARE_CTRL;
+ mask = SEL_RXD_AP_UART_MASK | SEL_TXD_GPIO_1_MASK;
+ value = RXD_GPIO_1 << SEL_RXD_AP_UART_SHIFT |
+ TXD_AP_UART << SEL_TXD_GPIO_1_SHIFT;
+ return regmap_update_bits(priv->regmap, offset, mask, value);
+}
+
+static const struct exynos_pmu_data exynos850_pmu_data = {
+ .pmu_init = exynos850_pmu_init,
+};
+
+static int exynos_pmu_bind(struct udevice *dev)
+{
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+ return 0;
+}
+
+static int exynos_pmu_probe(struct udevice *dev)
+{
+ ofnode node;
+ struct exynos_pmu *priv;
+
+ priv = dev_get_priv(dev);
+ priv->dev = dev;
+
+ node = dev_ofnode(dev);
+ priv->regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->pmu_data = (struct exynos_pmu_data *)dev_get_driver_data(dev);
+ if (priv->pmu_data && priv->pmu_data->pmu_init)
+ return priv->pmu_data->pmu_init(priv);
+
+ return 0;
+}
+
+static const struct udevice_id exynos_pmu_ids[] = {
+ {
+ .compatible = "samsung,exynos850-pmu",
+ .data = (ulong)_pmu_data
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(exynos_pmu) = {
+ .name = "exynos-pmu",
+ .id
[PATCH v2 04/13] soc: samsung: Add Exynos USI driver
USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x1382 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Driver's code was copied over from Linux kernel [1] and adapted correspondingly for U-Boot API. UCLASS_MISC is used, and although no misc operations are implemented, it makes it easier to probe the driver this way (as compared to UCLASS_NOP) and keep the code compact. [1] drivers/soc/samsung/exynos-usi.c Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park Reviewed-by: Simon Glass --- Changes in v2: - Removed unnecessary 'mode' param in exynos_usi_set_sw_conf() - Removed usi->dev and used priv data instead - Used .of_plat_data callback for dts parsing - Added R-b tags drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/samsung/Kconfig | 23 drivers/soc/samsung/Makefile | 3 + drivers/soc/samsung/exynos-usi.c | 208 +++ 5 files changed, 236 insertions(+) create mode 100644 drivers/soc/samsung/Kconfig create mode 100644 drivers/soc/samsung/Makefile create mode 100644 drivers/soc/samsung/exynos-usi.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 85dac9de78a4..03433bc0e6d2 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -40,6 +40,7 @@ config SOC_XILINX_VERSAL_NET This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +source "drivers/soc/samsung/Kconfig" source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 84385650d46d..610bf816d40a 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig new file mode 100644 index ..ffb87fe79316 --- /dev/null +++ b/drivers/soc/samsung/Kconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0+ + +menuconfig SOC_SAMSUNG + bool "Samsung SoC drivers support" + +if SOC_SAMSUNG + +config EXYNOS_USI + bool "Exynos USI (Universal Serial Interface) driver" + depends on ARCH_EXYNOS + select MISC + select REGMAP + select SYSCON + help + Enable support for USI block. USI (Universal Serial Interface) is an + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and + ExynosAutoV9. USI block can be configured to provide one of the + following serial protocols: UART, SPI or High Speed I2C. + + This driver allows one to configure USI for desired protocol, which + is usually done in USI node in Device Tree. + +endif diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile new file mode 100644 index ..833ac073fbfa --- /dev/null +++ b/drivers/soc/samsung/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c new file mode 100644 index ..b746a7838e1f --- /dev/null +++ b/drivers/soc/samsung/exynos-usi.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko + * + * Samsung Exynos USI driver (Universal Serial Interface). + */ + +#include +#include +#include +#include +#include +#include +#includ
[PATCH v2 03/13] dt-bindings: clock: Add Exynos850 clock controller
Add bindings documentation and the header file for Exynos850 clock controller. It was taken from Linux kernel [1,2]. [1] Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml [2] include/dt-bindings/clock/exynos850.h Signed-off-by: Sam Protsenko --- Changes in v2: - (none) .../clock/samsung,exynos850-clock.yaml| 307 include/dt-bindings/clock/exynos850.h | 337 ++ 2 files changed, 644 insertions(+) create mode 100644 doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml create mode 100644 include/dt-bindings/clock/exynos850.h diff --git a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml new file mode 100644 index ..a0906efe1223 --- /dev/null +++ b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml @@ -0,0 +1,307 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos850 SoC clock controller + +maintainers: + - Sam Protsenko + +description: | + Exynos850 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external + clocks must be defined as fixed-rate clocks in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos850.h' header. + +properties: + compatible: +enum: + - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-aud + - samsung,exynos850-cmu-cmgp + - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d + - samsung,exynos850-cmu-hsi + - samsung,exynos850-cmu-is + - samsung,exynos850-cmu-mfcmscl + - samsung,exynos850-cmu-peri + + clocks: +minItems: 1 +maxItems: 5 + + clock-names: +minItems: 1 +maxItems: 5 + + "#clock-cells": +const: 1 + + reg: +maxItems: 1 + +allOf: + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-top + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) + +clock-names: + items: +- const: oscclk + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-apm + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: CMU_APM bus clock (from CMU_TOP) + +clock-names: + items: +- const: oscclk +- const: dout_clkcmu_apm_bus + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-aud + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: AUD clock (from CMU_TOP) + +clock-names: + items: +- const: oscclk +- const: dout_aud + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-cmgp + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: CMU_CMGP bus clock (from CMU_APM) + +clock-names: + items: +- const: oscclk +- const: gout_clkcmu_cmgp_bus + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-core + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: CMU_CORE bus clock (from CMU_TOP) +- description: CCI clock (from CMU_TOP) +- description: eMMC clock (from CMU_TOP) +- description: SSS clock (from CMU_TOP) + +clock-names: + items: +- const: oscclk +- const: dout_core_bus +- const: dout_core_cci +- const: dout_core_mmc_embd +- const: dout_core_sss + + - if: + properties: +compatible: + contains: +const: samsung,exynos8
[PATCH v2 01/13] dt-bindings: soc: samsung: Add Exynos USI
Add USI bindings documentation and header file. Those are taken from
Linux kernel [1,2], but the documentation was reworked a bit to only
describe the compatibles that will be supported in U-Boot soon.
[1] Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
[2] include/dt-bindings/soc/samsung,exynos-usi.h
Signed-off-by: Sam Protsenko
---
Changes in v2:
- (none)
.../soc/samsung/exynos-usi.yaml | 162 ++
include/dt-bindings/soc/samsung,exynos-usi.h | 17 ++
2 files changed, 179 insertions(+)
create mode 100644 doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
create mode 100644 include/dt-bindings/soc/samsung,exynos-usi.h
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
new file mode 100644
index ..8e6423f11568
--- /dev/null
+++ b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung's Exynos USI (Universal Serial Interface)
+
+maintainers:
+ - Sam Protsenko
+
+description: |
+ USI IP-core provides selectable serial protocol (UART, SPI or High-Speed
I2C).
+ USI shares almost all internal circuits within each protocol, so only one
+ protocol can be chosen at a time. USI is modeled as a node with zero or more
+ child nodes, each representing a serial sub-node device. The mode setting
+ selects which particular function will be used.
+
+properties:
+ $nodename:
+pattern: "^usi@[0-9a-f]+$"
+
+ compatible:
+enum:
+ - samsung,exynos850-usi
+
+ reg: true
+
+ clocks: true
+
+ clock-names: true
+
+ ranges: true
+
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 1
+
+ samsung,sysreg:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+items:
+ - items:
+ - description: phandle to System Register syscon node
+ - description: offset of SW_CONF register for this USI controller
+description:
+ Should be phandle/offset pair. The phandle to System Register syscon node
+ (for the same domain where this USI controller resides) and the offset
+ of SW_CONF register for this USI controller.
+
+ samsung,mode:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ Selects USI function (which serial protocol to use). Refer to
+ for valid USI mode values.
+
+ samsung,clkreq-on:
+type: boolean
+description:
+ Enable this property if underlying protocol requires the clock to be
+ continuously provided without automatic gating. As suggested by SoC
+ manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
+ multi-master mode. Usually this property is needed if USI mode is set
+ to "UART".
+
+ This property is optional.
+
+patternProperties:
+ "^i2c@[0-9a-f]+$":
+$ref: /schemas/i2c/i2c-exynos5.yaml
+description: Child node describing underlying I2C
+
+ "^serial@[0-9a-f]+$":
+$ref: /schemas/serial/samsung_uart.yaml
+description: Child node describing underlying UART/serial
+
+ "^spi@[0-9a-f]+$":
+$ref: /schemas/spi/samsung,spi.yaml
+description: Child node describing underlying SPI
+
+required:
+ - compatible
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+ - samsung,sysreg
+ - samsung,mode
+
+if:
+ properties:
+compatible:
+ contains:
+enum:
+ - samsung,exynos850-usi
+
+then:
+ properties:
+reg:
+ maxItems: 1
+
+clocks:
+ items:
+- description: Bus (APB) clock
+- description: Operating clock for UART/SPI/I2C protocol
+
+clock-names:
+ items:
+- const: pclk
+- const: ipclk
+
+ required:
+- reg
+- clocks
+- clock-names
+
+else:
+ properties:
+reg: false
+clocks: false
+clock-names: false
+samsung,clkreq-on: false
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+usi0: usi@138200c0 {
+compatible = "samsung,exynos850-usi";
+reg = <0x138200c0 0x20>;
+samsung,sysreg = <_peri 0x1010>;
+samsung,mode = ;
+samsung,clkreq-on; /* needed for UART mode */
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+clocks = <_peri 32>, <_peri 31>;
+clock-names = "pclk", "ipclk";
+
+serial_0: serial@1382 {
+compatible = "samsung,exynos850-uart";
+reg = <0x1382 0xc0>;
+interrupts = ;
+clocks = <_peri 32>, <_peri 31>;
+clock-names = "uart", "clk_uart_baud0";
+status
[PATCH v2 02/13] dt-bindings: soc: samsung: Add Exynos PMU
Add bindings documentation for Exynos PMU hardware block. It was taken
from Linux kernel [1], but minimized and modified to reflect features
that will be actually supported in U-Boot soon. For example,
the "samsung,uart-debug-1" property is not available in Linux kernel
bindings and only present in U-Boot.
[1] Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
Signed-off-by: Sam Protsenko
---
Changes in v2:
- (none)
.../soc/samsung/exynos-pmu.yaml | 85 +++
1 file changed, 85 insertions(+)
create mode 100644 doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
new file mode 100644
index ..c3e95c33b01d
--- /dev/null
+++ b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC series Power Management Unit (PMU)
+
+maintainers:
+ - Sam Protsenko
+
+description: |+
+ PMU block controls the power and operation states of Exynos SoC. It contains
+ registers for changing the state of next features::
+
+ - Local power control. Exynos SoCs have various power domains, and it's
+possible to turn them on and off independently, using corresponding
+registers in PMU block
+ - System-level power control. That allows putting the system into power-down
+modes (sleep) by turning off the power for most of the domains
+ - Miscellaneous PMU related features
+
+# Custom select to avoid matching all nodes with 'syscon'
+select:
+ properties:
+compatible:
+ contains:
+enum:
+ - samsung,exynos850-pmu
+ required:
+- compatible
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - enum:
+ - samsung,exynos850-pmu
+ - const: syscon
+
+ reg:
+maxItems: 1
+
+ samsung,uart-debug-1:
+type: boolean
+description:
+ Enable this property if AP UART lines (Application Processor UART) must
be
+ connected to UART_DEBUG_1 path in PMU block. That's usually needed when
+ the serial console is provided by uart1_pins. If this property is not
+ specified, the default behavior will be used (AP UART lines connected to
+ UART_DEBUG_0 path, which usually means uart0_pins are used for the serial
+ console).
+
+ syscon-poweroff:
+$ref: /schemas/power/reset/syscon-poweroff.yaml#
+type: object
+description:
+ Node for power off method
+
+ syscon-reboot:
+$ref: /schemas/power/reset/syscon-reboot.yaml#
+type: object
+description:
+ Node for reboot method
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+pmu_system_controller: system-controller@1186 {
+compatible = "samsung,exynos850-pmu", "syscon";
+reg = <0x1186 0x1>;
+
+reboot: syscon-reboot {
+compatible = "syscon-reboot";
+regmap = <_system_controller>;
+offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
+mask = <0x2>; /* SWRESET_SYSTEM */
+value = <0x2>; /* reset value */
+};
+};
--
2.39.2
[PATCH v2 00/13] arm: exynos: Add E850-96 board
Add Exynos850 SoC and WinLink's E850-96 board support. A short overview
of series additions and modifications:
* USI driver: configures UART block
* PMU driver: connects AP UART lines to uart1 pins)
* Exynos850 clock driver: generates UART clocks
* Exynos850 pinctrl driver: mux UART pins
* serial_s5p: UART driver
* Exynos850 SoC: dtsi files and MMU maps
* E850-96 board: dts files, defconfig, board file and doc
Most of the code was borrowed from mainline Linux kernel (where this
board is already enabled) and adapted for U-Boot. Preliminary
preparation for this series includes next patches / series (already
merged):
* commit 585a2aaac2ac ("arm: exynos: Include missing CPU header in
soc.c")
* commit c9ab9f30c8e4 ("arm: exynos: Include missing CPU header in
gpio.h")
* commit 11bd2787deff ("watchdog: s5p_wdt: Include missing CPU
header")
* commit 08cfa971a717 ("exynos: Avoid duplicate reset_cpu with
SYSRESET enabled")
* commit f655090901dc ("clk: exynos: Add header guard for clk-pll.h")
* commit 2227f4c0afed ("serial: s5p: Fix clk_get_by_index() error code
check")
* commit a0615ffc99a5 ("serial: s5p: Remove common.h inclusion")
* commit 5ad21de6bae0 ("serial: s5p: Use livetree API to get "id"
property")
* commit e79f630dbf67 ("serial: s5p: Use named constants for register
values")
* commit a627f2802a71 ("serial: s5p: Improve coding style")
* commit 33e7ca5a9b6a ("serial: s5p: Use dev_read_addr_ptr() to get
base address")
* commit 6219b47c4d91 ("board: samsung: Fix SYS_CONFIG_NAME configs in
axy17lte Kconfig")
* commit 470682ace1e0 ("configs: Remove unneeded SYS_CONFIG_NAME from
a*y17lte defconfigs")
and series [1]. For more detailed description please see the board
documentation (added in PATCH #12) and corresponding commit messages.
Changes in v2:
- PATCH 4: Removed unnecessary mode param
- PATCH 4: Removed usi->dev and used priv data instead
- PATCH 4: Used .of_plat_data callback for dts parsing
- PATCH 7: Fixed Thomas Abraham e-mail
- PATCH 9: Fixed incorrect driver description (comment)
- Collected Reviewed-by tags
- Rebased on top of most recent U-Boot/master
[1] https://lists.denx.de/pipermail/u-boot/2023-November/539033.html
Sam Protsenko (13):
dt-bindings: soc: samsung: Add Exynos USI
dt-bindings: soc: samsung: Add Exynos PMU
dt-bindings: clock: Add Exynos850 clock controller
soc: samsung: Add Exynos USI driver
soc: samsung: Add Exynos PMU driver
clk: exynos: Move pll code into clk-exynos7420
clk: exynos: Add Samsung clock framework
clk: exynos: Add Exynos850 clock driver
pinctrl: exynos: Add pinctrl support for Exynos850
serial: s5p: Add Exynos850 compatible
arm: exynos: Add Exynos850 SoC support
board: samsung: Add support for E850-96 board
MAINTAINERS: Add new Samsung subsystems
MAINTAINERS | 25 +
arch/arm/dts/Makefile |1 +
arch/arm/dts/exynos-pinctrl.h | 79 +
arch/arm/dts/exynos850-e850-96-u-boot.dtsi| 37 +
arch/arm/dts/exynos850-e850-96.dts| 273
arch/arm/dts/exynos850-pinctrl.dtsi | 663 +
arch/arm/dts/exynos850.dtsi | 809 +++
arch/arm/mach-exynos/Kconfig | 28 +-
arch/arm/mach-exynos/mmu-arm64.c | 34 +
board/samsung/e850-96/Kconfig | 16 +
board/samsung/e850-96/MAINTAINERS |9 +
board/samsung/e850-96/Makefile|6 +
board/samsung/e850-96/e850-96.c | 22 +
configs/e850-96_defconfig | 21 +
doc/board/samsung/e850-96.rst | 87 ++
.../img/exynos850-boot-architecture.svg | 1283 +
doc/board/samsung/index.rst |1 +
.../clock/samsung,exynos850-clock.yaml| 307
.../soc/samsung/exynos-pmu.yaml | 85 ++
.../soc/samsung/exynos-usi.yaml | 162 +++
drivers/clk/exynos/Kconfig|7 +
drivers/clk/exynos/Makefile | 11 +-
drivers/clk/exynos/clk-exynos7420.c | 25 +-
drivers/clk/exynos/clk-exynos850.c| 189 +++
drivers/clk/exynos/clk-pll.c | 167 ++-
drivers/clk/exynos/clk-pll.h | 16 +-
drivers/clk/exynos/clk.c | 121 ++
drivers/clk/exynos/clk.h | 228 +++
drivers/pinctrl/exynos/Kconfig|8 +
drivers/pinctrl/exynos/Makefile |1 +
drivers/pinctrl/exynos/pinctrl-exynos
Re: [PATCH 07/13] clk: exynos: Add Samsung clock framework
On Tue, Dec 19, 2023 at 5:38 AM Chanho Park wrote: > [snip] > > diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c > > new file mode 100644 > > index ..9e496ff83aaf > > --- /dev/null > > +++ b/drivers/clk/exynos/clk-pll.c > > @@ -0,0 +1,167 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2016 Samsung Electronics > > + * Copyright (C) 2023 Linaro Ltd. > > + * > > + * Authors: > > + * Thomas Abraham > > Need to correct Thomas's email to samsung.com if you want to keep his > original credit even though his e-mail was already stale since he left the > company. > Thanks for the review, will do in v2! [snip] > > + * > > + * Authors: > > + * Thomas Abraham > > Ditto. > > Othewise, > Reviewed-by: Chanho Park >
Re: [PATCH 04/13] soc: samsung: Add Exynos USI driver
On Wed, Dec 27, 2023 at 11:49 AM Simon Glass wrote:
>
> Hi Sam,
>
[snip]
>
> Just a few nits here
>
> Reviewed-by: Simon Glass
>
[snip]
> > +
> > +struct exynos_usi {
> > + struct udevice *dev;
>
> Can we drop this? It doesn't seem very useful and we try to avoid
> having bidirectional pointers. since it is possible to get the 'priv'
> pointer from the device.
>
Sure. I tried to keep the driver as close as possible to Linux
kernel's version, where I borrowed it from. But if it's the current
preference in U-Boot, I'll fix this in v2.
[snip]
> > +static int exynos_usi_parse_dt(struct exynos_usi *usi)
>
> Use of_to_plat() method?
>
Will do in v2. Thanks for the review!
[snip]
Re: [PATCH 04/13] soc: samsung: Add Exynos USI driver
On Wed, Dec 27, 2023 at 3:11 AM Minkyu Kang wrote:
>
> Hi
>
>
> 2023년 12월 13일 (수) 12:42, Sam Protsenko 님이 작성:
>>
[snip]
>> +
>> +/**
>> + * exynos_usi_set_sw_conf - Set USI block configuration mode
>> + * @usi: USI driver object
>> + * @mode: Mode index
>> + *
>> + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core.
>> + *
>> + * Return: 0 on success, or negative error code on failure.
>> + */
>> +static int exynos_usi_set_sw_conf(struct exynos_usi *usi, size_t mode)
>
>
> The value of mode is same as usi->mode, but is there a reason to pass it as a
> parameter?
>
>>
>> +{
>> + unsigned int val;
>> + int ret;
>> +
>> + if (mode < usi->data->min_mode || mode > usi->data->max_mode)
>> + return -EINVAL;
>> +
>> + val = exynos_usi_modes[mode].val;
>> + ret = regmap_update_bits(usi->sysreg, usi->sw_conf,
>> +usi->data->sw_conf_mask, val);
>> + if (ret)
>> + return ret;
>> +
>> + usi->mode = mode;
>
>
> This will obviously be the same value always.
>
Thanks for the review! Yes, you are right. This code was copy-pasted
from Linux kernel. So at the time I thought it was better to leave it
as is, for backporting reasons. But now that I look at it, this won't
be too helpful. So I'll get rid of it in v2.
[snip]
Re: [PATCH 07/13] clk: exynos: Add Samsung clock framework
On Wed, Dec 27, 2023 at 3:12 AM Minkyu Kang wrote:
>
> Hi,
>
>
> 2023년 12월 13일 (수) 12:27, Sam Protsenko 님이 작성:
>>
>> Heavily based on Linux kernel Samsung clock framework, with some changes
>> to accommodate the differences in U-Boot CCF implementation. It's also
>> quite minimal as compared to the Linux version.
>>
>> Signed-off-by: Sam Protsenko
>> ---
[snip]
>> diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
>> new file mode 100644
>> index ..3b477369aeb8
>> --- /dev/null
>> +++ b/drivers/clk/exynos/clk-pll.h
>> @@ -0,0 +1,23 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Copyright (C) 2023 Linaro Ltd.
>> + *
>> + * Authors:
>> + * Thomas Abraham
>> + * Sam Protsenko
>> + *
>> + * Common Clock Framework support for all PLL's in Samsung platforms.
>> + */
>> +
>> +#ifndef __EXYNOS_CLK_PLL_H
>> +#define __EXYNOS_CLK_PLL_H
>> +
>> +#include
>> +
>> +enum samsung_pll_type {
>> + pll_0822x,
>> + pll_0831x,
>
>
> why don't you modify to uppercase?
>
That code was basically copied over from Linux kernel (from
drivers/clk/samsung/clk-pll.h file). I'm trying to keep it as close to
the original as possible, to ease any possible backporting in future.
Although kernel coding style indeed tends to stick to uppercase in
enums, in my opinion the backporting/compatibility concern outweighs
the style one. Hope it's ok with you if I keep it as is in v2?
>>
>> +};
>> +
>> +#endif /* __EXYNOS_CLK_PLL_H */
>> diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c
>> new file mode 100644
>> index ..430767f072d8
>> --- /dev/null
>> +++ b/drivers/clk/exynos/clk.c
>> @@ -0,0 +1,121 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (C) 2023 Linaro Ltd.
>> + * Sam Protsenko
>> + *
>> + * This file includes utility functions to register clocks to common
>> + * clock framework for Samsung platforms.
>> + */
>> +
>> +#include
>> +#include "clk.h"
>> +
>> +void samsung_clk_register_mux(void __iomem *base,
>> + const struct samsung_mux_clock *clk_list,
>> + unsigned int nr_clk)
>> +{
>> + unsigned int cnt;
>> +
>> + for (cnt = 0; cnt < nr_clk; cnt++) {
>> + struct clk *clk;
>> + const struct samsung_mux_clock *m;
>
>
> wouldn't it be better if use a more meaningful name like mux?
>
My reasoning for choosing the name that short in this case was because
of super-short scope (3 lines of code), and OTOH this variable is
massively used during that scope, like this:
clk = clk_register_mux(NULL, m->name, m->parent_names,
m->num_parents, m->flags, base + m->offset, m->shift,
m->width, m->mux_flags);
Hope it makes sense. If you still prefer 'mux', please let me know and
I'll use it in v2.
>>
>> +
>> + m = _list[cnt];
>
>
> Is there any possibility that the value is null or wrong (e.g. overflow)
>
I decided to keep it with no error handling because I didn't feel like
it would bring much value. Because this code is supposed to be used
via samsung_cmu_register_one(), and the CMU structure passed to that
function is usually going to be defined in this idiomatic way (as can
be seen in clk-exynos850.c driver):
static const struct samsung_clk_group top_cmu_clks[] = {
{ S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) },
{ S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) },
...
and the corresponding clocks structures are also defined like this:
static const struct samsung_mux_clock top_pure_mux_clks[] = {
MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll",
mout_shared0_pll_p,
PLL_CON0_PLL_SHARED0, 4, 1),
MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll",
mout_shared1_pll_p,
PLL_CON0_PLL_SHARED1, 4, 1),
...
I'd say the odds for messing this up are next to none, because of
using ARRAY_SIZE() and clock macros like MUX(). Especially because the
example is already set in clk-exynos850 driver and I assume everybody
would just use it as a template, which usually happens. So after
exploring the alternative approach (with added error handling) I felt
it was unjustifiable cluttered comparing to the more concise version
present in this series, at least in this particular
Re: [PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850
On Tue, Dec 19, 2023 at 5:32 AM Chanho Park wrote: > > > -Original Message- > > From: U-Boot On Behalf Of Sam Protsenko > > Sent: Wednesday, December 13, 2023 12:17 PM > > To: Minkyu Kang ; Tom Rini ; > > Lukasz Majewski ; Sean Anderson > > Cc: Simon Glass ; Heinrich Schuchardt > > ; u-boot@lists.denx.de > > Subject: [PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850 > > > > Add pinctrl support for Exynos850 SoC. It was mostly extracted from > > corresponding Linux kernel code [1]. Power down modes and external > > interrupt data were removed while converting the code for U-Boot, but > > everything else was kept almost unchanged. > > > > [1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > > > Signed-off-by: Sam Protsenko > > --- > > drivers/pinctrl/exynos/Kconfig | 8 ++ > > drivers/pinctrl/exynos/Makefile| 1 + > > drivers/pinctrl/exynos/pinctrl-exynos850.c | 125 + > > 3 files changed, 134 insertions(+) > > create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos850.c > > > > diff --git a/drivers/pinctrl/exynos/Kconfig > > b/drivers/pinctrl/exynos/Kconfig > > index a60f49869b45..1b7fb62bc4ba 100644 > > --- a/drivers/pinctrl/exynos/Kconfig > > +++ b/drivers/pinctrl/exynos/Kconfig > > @@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0 > > help > > Support pin multiplexing and pin configuration control on > > Samsung's Exynos78x0 SoC. > > + > > +config PINCTRL_EXYNOS850 > > + bool "Samsung Exynos850 pinctrl driver" > > + depends on ARCH_EXYNOS && PINCTRL_FULL > > + select PINCTRL_EXYNOS > > + help > > + Support pin multiplexing and pin configuration control on > > + Samsung's Exynos850 SoC. > > diff --git a/drivers/pinctrl/exynos/Makefile > > b/drivers/pinctrl/exynos/Makefile > > index 07db970ca942..3abe1226eb74 100644 > > --- a/drivers/pinctrl/exynos/Makefile > > +++ b/drivers/pinctrl/exynos/Makefile > > @@ -6,3 +6,4 @@ > > obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o > > obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o > > obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o > > +obj-$(CONFIG_PINCTRL_EXYNOS850) += pinctrl-exynos850.o > > diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c > > b/drivers/pinctrl/exynos/pinctrl-exynos850.c > > new file mode 100644 > > index ..2445dd752ea8 > > --- /dev/null > > +++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c > > @@ -0,0 +1,125 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2023 Linaro Ltd. > > + * Author: Sam Protsenko > > + * > > + * Samsung Exynos USI driver (Universal Serial Interface). > > Typo. It should be a subject for the pinctrl driver. > Nice catch! Will be fixed in v2. > Otherwise, > Reviewed-by: Chanho Park Thanks for the review! >
Re: [PATCH] MAINTAINERS: Fix ANDROID AB unknown file entry
Hi Mattijs,
On Wed, Dec 20, 2023 at 10:43 AM Mattijs Korpershoek
wrote:
>
> Commit 19a91f2464a8 ("Create a new boot/ directory") moved the
> android_ab.c code under boot/android_ab but did not update
> the MAINTAINERS entry.
Thanks for the patch! Would you mind adding corresponding "Fixes" tag
below your Signed-off?
Other than that LGTM:
Reviewed-by: Sam Protsenko
>
> Update it so that the maintainer will get cc'ed again.
>
> Signed-off-by: Mattijs Korpershoek
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7c1cb2dc4dc0..f6de883a7d8f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -60,8 +60,8 @@ ANDROID AB
> M: Igor Opaniuk
> R: Sam Protsenko
> S: Maintained
> +F: boot/android_ab.c
> F: cmd/ab_select.c
> -F: common/android_ab.c
> F: doc/android/ab.rst
> F: include/android_ab.h
> F: test/py/tests/test_android/test_ab.py
>
> ---
> base-commit: 9e53e45292ee2f1d9d2ccc59914b161bef9b10d7
> change-id: 20231220-maintainers-fix-ab-2afa7cee97bd
>
> Best regards,
> --
> Mattijs Korpershoek
>
Re: [PATCH 00/13] arm: exynos: Add E850-96 board
On Tue, Dec 12, 2023 at 9:16 PM Sam Protsenko
wrote:
>
> NOTE: This patch series depends on "pinctrl: exynos: Prepare for other
> SoCs support" series [1]. It should be applied first.
>
> Add Exynos850 SoC and WinLink's E850-96 board support. A short overview
> of series additions and modifications:
> * USI driver: configures UART block
> * PMU driver: connects AP UART lines to uart1 pins)
> * Exynos850 clock driver: generates UART clocks
> * Exynos850 pinctrl driver: mux UART pins
> * serial_s5p: UART driver
> * Exynos850 SoC: dtsi files and MMU maps
> * E850-96 board: dts files, defconfig, board file and doc
>
> Most of the code was borrowed from mainline Linux kernel (where this
> board is already enabled) and adapted for U-Boot. Preliminary
> preparation for this series includes next patches / series (already
> merged):
>
> * commit 585a2aaac2ac ("arm: exynos: Include missing CPU header in
> soc.c")
> * commit c9ab9f30c8e4 ("arm: exynos: Include missing CPU header in
> gpio.h")
> * commit 11bd2787deff ("watchdog: s5p_wdt: Include missing CPU
> header")
> * commit 08cfa971a717 ("exynos: Avoid duplicate reset_cpu with
> SYSRESET enabled")
> * commit f655090901dc ("clk: exynos: Add header guard for clk-pll.h")
> * commit 2227f4c0afed ("serial: s5p: Fix clk_get_by_index() error code
> check")
> * commit a0615ffc99a5 ("serial: s5p: Remove common.h inclusion")
> * commit 5ad21de6bae0 ("serial: s5p: Use livetree API to get "id"
> property")
> * commit e79f630dbf67 ("serial: s5p: Use named constants for register
> values")
> * commit a627f2802a71 ("serial: s5p: Improve coding style")
> * commit 33e7ca5a9b6a ("serial: s5p: Use dev_read_addr_ptr() to get
> base address")
> * commit 6219b47c4d91 ("board: samsung: Fix SYS_CONFIG_NAME configs in
> axy17lte Kconfig")
> * commit 470682ace1e0 ("configs: Remove unneeded SYS_CONFIG_NAME from
> a*y17lte defconfigs")
>
> and series [1] (dependency) is still pending.
>
> For more detailed description please see the board documentation (added
> in PATCH #12) and corresponding commit messages.
>
> [1] https://lists.denx.de/pipermail/u-boot/2023-November/539033.html
>
> Sam Protsenko (13):
> dt-bindings: soc: samsung: Add Exynos USI
> dt-bindings: soc: samsung: Add Exynos PMU
> dt-bindings: clock: Add Exynos850 clock controller
> soc: samsung: Add Exynos USI driver
> soc: samsung: Add Exynos PMU driver
> clk: exynos: Move pll code into clk-exynos7420
> clk: exynos: Add Samsung clock framework
> clk: exynos: Add Exynos850 clock driver
> pinctrl: exynos: Add pinctrl support for Exynos850
> serial: s5p: Add Exynos850 compatible
> arm: exynos: Add Exynos850 SoC support
> board: samsung: Add support for E850-96 board
> MAINTAINERS: Add new Samsung subsystems
>
> MAINTAINERS | 25 +
> arch/arm/dts/Makefile |1 +
> arch/arm/dts/exynos-pinctrl.h | 79 +
> arch/arm/dts/exynos850-e850-96-u-boot.dtsi| 37 +
> arch/arm/dts/exynos850-e850-96.dts| 273
> arch/arm/dts/exynos850-pinctrl.dtsi | 663 +
> arch/arm/dts/exynos850.dtsi | 809 +++
> arch/arm/mach-exynos/Kconfig | 28 +-
> arch/arm/mach-exynos/mmu-arm64.c | 34 +
> board/samsung/e850-96/Kconfig | 16 +
> board/samsung/e850-96/MAINTAINERS |9 +
> board/samsung/e850-96/Makefile|6 +
> board/samsung/e850-96/e850-96.c | 22 +
> configs/e850-96_defconfig | 21 +
> doc/board/samsung/e850-96.rst | 87 ++
> .../img/exynos850-boot-architecture.svg | 1283 +
> doc/board/samsung/index.rst |1 +
> .../clock/samsung,exynos850-clock.yaml| 307
> .../soc/samsung/exynos-pmu.yaml | 85 ++
> .../soc/samsung/exynos-usi.yaml | 162 +++
> drivers/clk/exynos/Kconfig|7 +
> drivers/clk/exynos/Makefile | 11 +-
> drivers/clk/exynos/clk-exynos7420.c | 25 +-
> drivers/clk/exynos/clk-exynos850.c| 189 +++
> drivers/clk/exynos/clk-pll.c | 167 ++-
> drivers
Re: [PATCH v2 09/16] doc: Mention fastboot dependency on CMDLINE
On Thu, Dec 14, 2023 at 10:20 PM Simon Glass wrote: > > The fastboot 'boot' command only supports running a U-Boot command if > CONFIG_CMDLINE is enabled. Mention this in the documentation. > > Signed-off-by: Simon Glass > Suggested-by: Tom Rini > --- Reviewed-by: Sam Protsenko > > (no changes since v1) > > doc/android/fastboot.rst | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst > index 1ad8a897c853..933a652538c7 100644 > --- a/doc/android/fastboot.rst > +++ b/doc/android/fastboot.rst > @@ -127,6 +127,7 @@ Boot command > > When executing the fastboot ``boot`` command, if ``fastboot_bootcmd`` is set > then that will be executed in place of ``bootm ``. > +This is supported if CONFIG_CMDLINE is enabled, which it normally is. > > Partition Names > --- > -- > 2.43.0.472.g3155946c3a-goog >
[PATCH 12/13] board: samsung: Add support for E850-96 board
Add support for WinLink E850-96 board [1]. It's based on Exynos850 SoC
and follows 96boards specification, so it's compatible with 96boards
mezzanine boards [2]. This patch enables next features:
* Serial console
* USI
* PMU (muxing AP UART path)
* Pinctrl
* Clocks
* Timer (ARMv8 architected)
* Reset control
It's quite a minimal enablement. Features like MMC, USB and Ethernet
will be enabled later.
The rationale for config values is as follows:
* TEXT_BASE = 0xf880
That's where BL2 loads the U-Boot payload, so TEXT_BASE must be
exactly this value. Overall the memory map is designed in a way to
keep the bootloader in the upper 128 MiB area of RAM, which is
0xf800..0x. That includes bootloader's code, stack,
data, heap, MMU tables, etc. All the memory below that 128 MiB chunk
can be used for storing boot images (0x8000..0xf800).
* CUSTOM_SYS_INIT_SP_ADDR = 0xf8c0
Just 4 MiB above the TEXT_BASE address, to leave enough space for
U-Boot code and stack itself (grows downwards).
* SYS_LOAD_ADDR = 0x8000
The beginning of RAM. That's where Linux kernel image must be
loaded.
* SYS_MALLOC_LEN = 0x81f000
8 MiB for malloc() + ENV_SIZE (128 KiB)
* SYS_MALLOC_F_LEN = 0x4000
Increase malloc() pool size available before relocation from 8 KiB
(default) to 16 KiB. Otherwise "alloc space exhausted" message
appears in U-Boot log during board_init_f() stage. There are next
reasons for doing so:
1. Having "bootph-all" flags in some dts nodes leads to binding
those during pre-relocation stage, and binding (DM) uses
dynamic memory allocation
2. clk-exynos850 driver uses CCF clocks, which in turn use dynamic
memory allocation
Device tree file was imported from Linux kernel. All nodes and boot
phase flags added in exynos850-e850-96-u-boot.dtsi are only needed to
enable serial console:
* oscclk -> cmu_top -> cmu_peri: generate UART/USI clocks
* pinctrl_alive and uart1_pins: needed to mux UART pins
* pmu_system_controller: configures AP UART path to uart1_pins
* usi_uart: configures USI block to operate as a UART protocol
* serial_0: enables serial console (UART)
[1] https://www.96boards.org/product/e850-96b/
[2] https://www.96boards.org/products/mezzanine/
Signed-off-by: Sam Protsenko
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/exynos850-e850-96-u-boot.dtsi| 37 +
arch/arm/dts/exynos850-e850-96.dts| 273
arch/arm/mach-exynos/Kconfig | 19 +-
board/samsung/e850-96/Kconfig | 16 +
board/samsung/e850-96/MAINTAINERS |9 +
board/samsung/e850-96/Makefile|6 +
board/samsung/e850-96/e850-96.c | 22 +
configs/e850-96_defconfig | 21 +
doc/board/samsung/e850-96.rst | 87 ++
.../img/exynos850-boot-architecture.svg | 1283 +
doc/board/samsung/index.rst |1 +
include/configs/e850-96.h | 12 +
13 files changed, 1786 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos850-e850-96-u-boot.dtsi
create mode 100644 arch/arm/dts/exynos850-e850-96.dts
create mode 100644 board/samsung/e850-96/Kconfig
create mode 100644 board/samsung/e850-96/MAINTAINERS
create mode 100644 board/samsung/e850-96/Makefile
create mode 100644 board/samsung/e850-96/e850-96.c
create mode 100644 configs/e850-96_defconfig
create mode 100644 doc/board/samsung/e850-96.rst
create mode 100644 doc/board/samsung/img/exynos850-boot-architecture.svg
create mode 100644 include/configs/e850-96.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5fc888680b39..7d949a6798ee 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
+dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
new file mode 100644
index ..7ad11e9faab2
--- /dev/null
+++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+
+_top {
+ bootph-all;
+};
+
+_peri {
+ bootph-all;
+};
+
+ {
+ bootph-all;
+};
+
+_alive {
+ bootph-all;
+};
+
+_system_controller {
+ bootph-all;
+ samsung,uart-debug-1;
+};
+
+_0 {
+ bootph-all;
+};
+
+_pins {
+ bootph-all;
+};
+
+_uart {
+ bootph-all;
+};
diff --git a/arch/arm/dts/exynos850-e850-96.dts
b/arch/arm/dts/exynos850-e850-96.dts
[PATCH 11/13] arm: exynos: Add Exynos850 SoC support
Samsung Exynos850 is ARMv8-based mobile-oriented SoC. It features
Cortex-A55 CPU (8 cores) and it's built using 8nm process.
Add Exynos850 support by enabling next features:
* Import Exynos850 SoC dtsi files from Linux kernel
* Add Exynos850 MMU memory map
* Introduce ARCH_EXYNOS9 platform config option
Signed-off-by: Sam Protsenko
---
arch/arm/dts/exynos-pinctrl.h | 79 +++
arch/arm/dts/exynos850-pinctrl.dtsi | 663 +++
arch/arm/dts/exynos850.dtsi | 809
arch/arm/mach-exynos/Kconfig| 9 +
arch/arm/mach-exynos/mmu-arm64.c| 34 ++
5 files changed, 1594 insertions(+)
create mode 100644 arch/arm/dts/exynos-pinctrl.h
create mode 100644 arch/arm/dts/exynos850-pinctrl.dtsi
create mode 100644 arch/arm/dts/exynos850.dtsi
diff --git a/arch/arm/dts/exynos-pinctrl.h b/arch/arm/dts/exynos-pinctrl.h
new file mode 100644
index ..7dd94a9b3652
--- /dev/null
+++ b/arch/arm/dts/exynos-pinctrl.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung Exynos DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski
+ */
+
+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+
+#define EXYNOS_PIN_PULL_NONE 0
+#define EXYNOS_PIN_PULL_DOWN 1
+#define EXYNOS_PIN_PULL_UP 3
+
+/* Pin function in power down mode */
+#define EXYNOS_PIN_PDN_OUT00
+#define EXYNOS_PIN_PDN_OUT11
+#define EXYNOS_PIN_PDN_INPUT 2
+#define EXYNOS_PIN_PDN_PREV3
+
+/*
+ * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885,
Exynos850
+ * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
+ */
+#define EXYNOS5420_PIN_DRV_LV1 0
+#define EXYNOS5420_PIN_DRV_LV2 1
+#define EXYNOS5420_PIN_DRV_LV3 2
+#define EXYNOS5420_PIN_DRV_LV4 3
+
+/* Drive strengths for Exynos5433 */
+#define EXYNOS5433_PIN_DRV_FAST_SR10
+#define EXYNOS5433_PIN_DRV_FAST_SR21
+#define EXYNOS5433_PIN_DRV_FAST_SR32
+#define EXYNOS5433_PIN_DRV_FAST_SR43
+#define EXYNOS5433_PIN_DRV_FAST_SR54
+#define EXYNOS5433_PIN_DRV_FAST_SR65
+#define EXYNOS5433_PIN_DRV_SLOW_SR18
+#define EXYNOS5433_PIN_DRV_SLOW_SR29
+#define EXYNOS5433_PIN_DRV_SLOW_SR30xa
+#define EXYNOS5433_PIN_DRV_SLOW_SR40xb
+#define EXYNOS5433_PIN_DRV_SLOW_SR50xc
+#define EXYNOS5433_PIN_DRV_SLOW_SR60xf
+
+/* Drive strengths for Exynos7 (except FSYS1) */
+#define EXYNOS7_PIN_DRV_LV10
+#define EXYNOS7_PIN_DRV_LV22
+#define EXYNOS7_PIN_DRV_LV31
+#define EXYNOS7_PIN_DRV_LV43
+
+/* Drive strengths for Exynos7 FSYS1 block */
+#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
+#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
+#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
+#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
+#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
+#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
+
+/* Drive strengths for Exynos850 GPIO_HSI block */
+#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */
+#define EXYNOS850_HSI_PIN_DRV_LV1_51 /* 1.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */
+#define EXYNOS850_HSI_PIN_DRV_LV2_53 /* 2.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */
+#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */
+
+#define EXYNOS_PIN_FUNC_INPUT 0
+#define EXYNOS_PIN_FUNC_OUTPUT 1
+#define EXYNOS_PIN_FUNC_2 2
+#define EXYNOS_PIN_FUNC_3 3
+#define EXYNOS_PIN_FUNC_4 4
+#define EXYNOS_PIN_FUNC_5 5
+#define EXYNOS_PIN_FUNC_6 6
+#define EXYNOS_PIN_FUNC_EINT 0xf
+#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */
diff --git a/arch/arm/dts/exynos850-pinctrl.dtsi
b/arch/arm/dts/exynos850-pinctrl.dtsi
new file mode 100644
index ..424bc80bde68
--- /dev/null
+++ b/arch/arm/dts/exynos850-pinctrl.dtsi
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (C) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
+ * tree nodes in this file.
+ */
+
+#include
+#include "exynos-pinctrl.h"
+
+_alive {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <>
[PATCH 13/13] MAINTAINERS: Add new Samsung subsystems
Add next Samsung subsystems with Sam Protsenko as a maintainer: - Samsung CCF Clock Framework - Exynos850 SoC Support - Samsung SoC Drivers Signed-off-by: Sam Protsenko --- MAINTAINERS | 25 + 1 file changed, 25 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9f74c0aacaac..3efb3df99d89 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -560,6 +560,31 @@ F: arch/arm/mach-exynos/ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ +ARM SAMSUNG CLOCK +M: Sam Protsenko +S: Maintained +F: drivers/clk/exynos/clk-pll.c +F: drivers/clk/exynos/clk-pll.h +F: drivers/clk/exynos/clk.c +F: drivers/clk/exynos/clk.h + +ARM SAMSUNG EXYNOS850 SOC +M: Sam Protsenko +S: Maintained +F: arch/arm/dts/exynos850-pinctrl.dtsi +F: arch/arm/dts/exynos850.dtsi +F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml +F: drivers/clk/exynos/clk-exynos850.c +F: drivers/pinctrl/exynos/pinctrl-exynos850.c +F: include/dt-bindings/clock/exynos850.h + +ARM SAMSUNG SOC DRIVERS +M: Sam Protsenko +S: Maintained +F: doc/device-tree-bindings/soc/samsung/* +F: drivers/soc/samsung/* +F: include/dt-bindings/soc/samsung,*.h + ARM SANCLOUD M: Paul Barker R: Marc Murphy -- 2.39.2
[PATCH 10/13] serial: s5p: Add Exynos850 compatible
Enable serial support for Exynos850 SoC by adding the corresponding
compatible string. No additional changes needed, the driver works as is
on Exynos850. Related USI and PMU configuration is enabled in separate
drivers. The only other dependencies are clock and pinctrl drivers,
which are already enabled too.
Signed-off-by: Sam Protsenko
---
drivers/serial/serial_s5p.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 7d04dcff54fc..801b7645afa4 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -257,6 +257,7 @@ static const struct dm_serial_ops s5p_serial_ops = {
static const struct udevice_id s5p_serial_ids[] = {
{ .compatible = "samsung,exynos4210-uart", .data = PORT_S5P },
+ { .compatible = "samsung,exynos850-uart", .data = PORT_S5P },
{ .compatible = "apple,s5l-uart", .data = PORT_S5L },
{ }
};
--
2.39.2
[PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850
Add pinctrl support for Exynos850 SoC. It was mostly extracted from
corresponding Linux kernel code [1]. Power down modes and external
interrupt data were removed while converting the code for U-Boot, but
everything else was kept almost unchanged.
[1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/Kconfig | 8 ++
drivers/pinctrl/exynos/Makefile| 1 +
drivers/pinctrl/exynos/pinctrl-exynos850.c | 125 +
3 files changed, 134 insertions(+)
create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos850.c
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
index a60f49869b45..1b7fb62bc4ba 100644
--- a/drivers/pinctrl/exynos/Kconfig
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0
help
Support pin multiplexing and pin configuration control on
Samsung's Exynos78x0 SoC.
+
+config PINCTRL_EXYNOS850
+ bool "Samsung Exynos850 pinctrl driver"
+ depends on ARCH_EXYNOS && PINCTRL_FULL
+ select PINCTRL_EXYNOS
+ help
+ Support pin multiplexing and pin configuration control on
+ Samsung's Exynos850 SoC.
diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile
index 07db970ca942..3abe1226eb74 100644
--- a/drivers/pinctrl/exynos/Makefile
+++ b/drivers/pinctrl/exynos/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o
obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o
+obj-$(CONFIG_PINCTRL_EXYNOS850)+= pinctrl-exynos850.o
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c
b/drivers/pinctrl/exynos/pinctrl-exynos850.c
new file mode 100644
index ..2445dd752ea8
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko
+ *
+ * Samsung Exynos USI driver (Universal Serial Interface).
+ */
+
+#include
+#include
+#include "pinctrl-exynos.h"
+
+#define EXYNOS850_PIN_BANK(pins, reg, id) \
+ { \
+ .type = _bank_type, \
+ .offset = reg, \
+ .nr_pins= pins, \
+ .name = id\
+ }
+
+/* CON, DAT, PUD, DRV */
+static const struct samsung_pin_bank_type exynos850_bank_type = {
+ .fld_width = { 4, 1, 4, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
+static const struct pinctrl_ops exynos850_pinctrl_ops = {
+ .set_state = exynos_pinctrl_set_state
+};
+
+/* pin banks of exynos850 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks0[] = {
+ EXYNOS850_PIN_BANK(8, 0x000, "gpa0"),
+ EXYNOS850_PIN_BANK(8, 0x020, "gpa1"),
+ EXYNOS850_PIN_BANK(8, 0x040, "gpa2"),
+ EXYNOS850_PIN_BANK(8, 0x060, "gpa3"),
+ EXYNOS850_PIN_BANK(4, 0x080, "gpa4"),
+ EXYNOS850_PIN_BANK(3, 0x0a0, "gpq0"),
+};
+
+/* pin banks of exynos850 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos850_pin_banks1[] = {
+ EXYNOS850_PIN_BANK(1, 0x000, "gpm0"),
+ EXYNOS850_PIN_BANK(1, 0x020, "gpm1"),
+ EXYNOS850_PIN_BANK(1, 0x040, "gpm2"),
+ EXYNOS850_PIN_BANK(1, 0x060, "gpm3"),
+ EXYNOS850_PIN_BANK(1, 0x080, "gpm4"),
+ EXYNOS850_PIN_BANK(1, 0x0a0, "gpm5"),
+ EXYNOS850_PIN_BANK(1, 0x0c0, "gpm6"),
+ EXYNOS850_PIN_BANK(1, 0x0e0, "gpm7"),
+};
+
+/* pin banks of exynos850 pin-controller 2 (AUD) */
+static const struct samsung_pin_bank_data exynos850_pin_banks2[] = {
+ EXYNOS850_PIN_BANK(5, 0x000, "gpb0"),
+ EXYNOS850_PIN_BANK(5, 0x020, "gpb1"),
+};
+
+/* pin banks of exynos850 pin-controller 3 (HSI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks3[] = {
+ EXYNOS850_PIN_BANK(6, 0x000, "gpf2"),
+};
+
+/* pin banks of exynos850 pin-controller 4 (CORE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks4[] = {
+ EXYNOS850_PIN_BANK(4, 0x000, "gpf0"),
+ EXYNOS850_PIN_BANK(8, 0x020, "gpf1"),
+};
+
+/* pin banks of exynos850 pin-controller 5 (PERI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks5[] = {
+ EXYNOS850_PIN_BANK(2, 0x000, "gpg0"),
+ EXYNOS850_PIN_BANK(6, 0x020, "gpp0"),
+ EXYNOS850_PIN_BANK(4, 0x040, "gpp1"),
+ EXYNOS850_PIN_BANK(4, 0x060, "gpp2"),
+ EXYNOS850_PIN_BANK(8, 0x080, "gpg1"),
+ EXYNOS850_PIN_BANK(8
[PATCH 08/13] clk: exynos: Add Exynos850 clock driver
Heavily influenced by its Linux kernel counterpart. It's implemented on
top of recently added Samsung CCF clock framework API. For now only UART
leaf clocks are implemented, along with all preceding clocks in CMU_TOP
and CMU_PERI. The UART baud clock is required in the serial driver, to
get its rate for the consequent baud rate calculation.
Signed-off-by: Sam Protsenko
---
drivers/clk/exynos/Kconfig | 7 ++
drivers/clk/exynos/Makefile| 1 +
drivers/clk/exynos/clk-exynos850.c | 189 +
3 files changed, 197 insertions(+)
create mode 100644 drivers/clk/exynos/clk-exynos850.c
diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
index eb0efa97d15c..85ce9d6e2418 100644
--- a/drivers/clk/exynos/Kconfig
+++ b/drivers/clk/exynos/Kconfig
@@ -15,4 +15,11 @@ config CLK_EXYNOS7420
This enables common clock driver support for platforms based
on Samsung Exynos7420 SoC.
+config CLK_EXYNOS850
+ bool "Clock driver for Samsung's Exynos850 SoC"
+ select CLK_CCF
+ help
+ This enables common clock driver support for platforms based
+ on Samsung Exynos850 SoC.
+
endmenu
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index 04c5b9a39e16..734100e2bff3 100644
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -9,3 +9,4 @@
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
+obj-$(CONFIG_CLK_EXYNOS850)+= clk-exynos850.o
diff --git a/drivers/clk/exynos/clk-exynos850.c
b/drivers/clk/exynos/clk-exynos850.c
new file mode 100644
index ..cf94a3e1b646
--- /dev/null
+++ b/drivers/clk/exynos/clk-exynos850.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung Exynos850 clock driver.
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko
+ */
+
+#include
+#include
+#include
+#include "clk.h"
+
+/* CMU_TOP -
*/
+
+/* Register Offset definitions for CMU_TOP (0x120e) */
+#define PLL_CON0_PLL_MMC 0x0100
+#define PLL_CON3_PLL_MMC 0x010c
+#define PLL_CON0_PLL_SHARED0 0x0140
+#define PLL_CON3_PLL_SHARED0 0x014c
+#define PLL_CON0_PLL_SHARED1 0x0180
+#define PLL_CON3_PLL_SHARED1 0x018c
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
+#define CLK_CON_DIV_CLKCMU_PERI_BUS0x187c
+#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
+#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
+
+static const struct samsung_pll_clock top_pure_pll_clks[] = {
+ PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED0),
+ PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED1),
+ PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
+ PLL_CON3_PLL_MMC),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP */
+PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" };
+PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" };
+PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
+PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
+PNAME(mout_peri_uart_p)= { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
+PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
+
+static const struct samsung_mux_clock top_pure_mux_clks[] = {
+ MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
+ PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
+ PLL_CON0_PLL_SHARED1, 4, 1),
+ MUX(CLK_MOUT_M
[PATCH 07/13] clk: exynos: Add Samsung clock framework
Heavily based on Linux kernel Samsung clock framework, with some changes
to accommodate the differences in U-Boot CCF implementation. It's also
quite minimal as compared to the Linux version.
Signed-off-by: Sam Protsenko
---
drivers/clk/exynos/Makefile | 9 +-
drivers/clk/exynos/clk-pll.c | 167 +
drivers/clk/exynos/clk-pll.h | 23
drivers/clk/exynos/clk.c | 121 +++
drivers/clk/exynos/clk.h | 228 +++
5 files changed, 546 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/exynos/clk-pll.c
create mode 100644 drivers/clk/exynos/clk-pll.h
create mode 100644 drivers/clk/exynos/clk.c
create mode 100644 drivers/clk/exynos/clk.h
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index 7faf238571ef..04c5b9a39e16 100644
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -1,6 +1,11 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2016 Samsung Electronics
-# Thomas Abraham
+# Copyright (C) 2023 Linaro Ltd.
+#
+# Authors:
+# Thomas Abraham
+# Sam Protsenko
-obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
new file mode 100644
index ..9e496ff83aaf
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Copyright (C) 2023 Linaro Ltd.
+ *
+ * Authors:
+ * Thomas Abraham
+ * Sam Protsenko
+ *
+ * This file contains the utility functions to register the pll clocks.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define UBOOT_DM_CLK_SAMSUNG_PLL0822X "samsung_clk_pll0822x"
+#define UBOOT_DM_CLK_SAMSUNG_PLL0831X "samsung_clk_pll0831x"
+
+struct samsung_clk_pll {
+ struct clk clk;
+ void __iomem*con_reg;
+ enum samsung_pll_type type;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct samsung_clk_pll, clk)
+
+/*
+ * PLL0822x Clock Type
+ */
+
+#define PLL0822X_MDIV_MASK 0x3ff
+#define PLL0822X_PDIV_MASK 0x3f
+#define PLL0822X_SDIV_MASK 0x7
+#define PLL0822X_MDIV_SHIFT16
+#define PLL0822X_PDIV_SHIFT8
+#define PLL0822X_SDIV_SHIFT0
+
+static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(clk);
+ u32 mdiv, pdiv, sdiv, pll_con3;
+ u64 fvco = clk_get_parent_rate(clk);
+
+ pll_con3 = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
+ pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
+ sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll0822x_clk_min_ops = {
+ .get_rate = samsung_pll0822x_recalc_rate,
+};
+
+/*
+ * PLL0831x Clock Type
+ */
+
+#define PLL0831X_KDIV_MASK 0x
+#define PLL0831X_MDIV_MASK 0x1ff
+#define PLL0831X_PDIV_MASK 0x3f
+#define PLL0831X_SDIV_MASK 0x7
+#define PLL0831X_MDIV_SHIFT16
+#define PLL0831X_PDIV_SHIFT8
+#define PLL0831X_SDIV_SHIFT0
+#define PLL0831X_KDIV_SHIFT0
+
+static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(clk);
+ u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
+ s16 kdiv;
+ u64 fvco = clk_get_parent_rate(clk);
+
+ pll_con3 = readl_relaxed(pll->con_reg);
+ pll_con5 = readl_relaxed(pll->con_reg + 8);
+ mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
+ pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
+ sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
+ kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll0831x_clk_min_ops = {
+ .get_rate = samsung_pll0831x_recalc_rate,
+};
+
+static struct clk *_samsung_clk_register_pll(void __iomem *base,
+ const struct samsung_pll_clock *pll_clk)
+{
+ struct samsung_clk_pll *pll;
+ struct clk *clk;
+ const char *drv_name;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->con_reg =
[PATCH 06/13] clk: exynos: Move pll code into clk-exynos7420
PLL utilities code is only used by clk-exynos7420 driver at the moment.
Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
clocks implementation, which is coming in the next patches.
Signed-off-by: Sam Protsenko
---
drivers/clk/exynos/Makefile | 1 -
drivers/clk/exynos/clk-exynos7420.c | 25 +-
drivers/clk/exynos/clk-pll.c| 32 -
drivers/clk/exynos/clk-pll.h| 13
4 files changed, 24 insertions(+), 47 deletions(-)
delete mode 100644 drivers/clk/exynos/clk-pll.c
delete mode 100644 drivers/clk/exynos/clk-pll.h
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index c9f29c873e9b..7faf238571ef 100644
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -3,5 +3,4 @@
# Copyright (C) 2016 Samsung Electronics
# Thomas Abraham
-obj-y += clk-pll.o
obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
diff --git a/drivers/clk/exynos/clk-exynos7420.c
b/drivers/clk/exynos/clk-exynos7420.c
index 7d869eb02b8e..9caa932e12fb 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -10,8 +10,15 @@
#include
#include
#include
+#include
#include
-#include "clk-pll.h"
+
+#define PLL145X_MDIV_SHIFT 16
+#define PLL145X_MDIV_MASK 0x3ff
+#define PLL145X_PDIV_SHIFT 8
+#define PLL145X_PDIV_MASK 0x3f
+#define PLL145X_SDIV_SHIFT 0
+#define PLL145X_SDIV_MASK 0x7
#define DIVIDER(reg, shift, mask) \
(((readl(reg) >> shift) & mask) + 1)
@@ -64,6 +71,22 @@ struct exynos7420_clk_top0_priv {
unsigned long sclk_uart2;
};
+static unsigned long pll145x_get_rate(unsigned int *con1,
+ unsigned long fin_freq)
+{
+ unsigned long pll_con1 = readl(con1);
+ unsigned long mdiv, sdiv, pdiv;
+ u64 fvco = fin_freq;
+
+ mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+ pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+ sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+ return (unsigned long)fvco;
+}
+
static ulong exynos7420_topc_get_rate(struct clk *clk)
{
struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
deleted file mode 100644
index 407fc71d415b..
--- a/drivers/clk/exynos/clk-pll.c
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Exynos PLL helper functions for clock drivers.
- * Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham
- */
-
-#include
-#include
-#include
-
-#define PLL145X_MDIV_SHIFT 16
-#define PLL145X_MDIV_MASK 0x3ff
-#define PLL145X_PDIV_SHIFT 8
-#define PLL145X_PDIV_MASK 0x3f
-#define PLL145X_SDIV_SHIFT 0
-#define PLL145X_SDIV_MASK 0x7
-
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
-{
- unsigned long pll_con1 = readl(con1);
- unsigned long mdiv, sdiv, pdiv;
- uint64_t fvco = fin_freq;
-
- mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
- pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
- sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
-
- fvco *= mdiv;
- do_div(fvco, (pdiv << sdiv));
- return (unsigned long)fvco;
-}
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
deleted file mode 100644
index 7b7af5e67612..
--- a/drivers/clk/exynos/clk-pll.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Exynos PLL helper functions for clock drivers.
- * Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham
- */
-
-#ifndef __EXYNOS_CLK_PLL_H
-#define __EXYNOS_CLK_PLL_H
-
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
-
-#endif /* __EXYNOS_CLK_PLL_H */
--
2.39.2
[PATCH 03/13] dt-bindings: clock: Add Exynos850 clock controller
Add bindings documentation and the header file for Exynos850 clock controller. It was taken from Linux kernel [1,2]. [1] Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml [2] include/dt-bindings/clock/exynos850.h Signed-off-by: Sam Protsenko --- .../clock/samsung,exynos850-clock.yaml| 307 include/dt-bindings/clock/exynos850.h | 337 ++ 2 files changed, 644 insertions(+) create mode 100644 doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml create mode 100644 include/dt-bindings/clock/exynos850.h diff --git a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml new file mode 100644 index ..a0906efe1223 --- /dev/null +++ b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml @@ -0,0 +1,307 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos850 SoC clock controller + +maintainers: + - Sam Protsenko + +description: | + Exynos850 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external + clocks must be defined as fixed-rate clocks in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos850.h' header. + +properties: + compatible: +enum: + - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-aud + - samsung,exynos850-cmu-cmgp + - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d + - samsung,exynos850-cmu-hsi + - samsung,exynos850-cmu-is + - samsung,exynos850-cmu-mfcmscl + - samsung,exynos850-cmu-peri + + clocks: +minItems: 1 +maxItems: 5 + + clock-names: +minItems: 1 +maxItems: 5 + + "#clock-cells": +const: 1 + + reg: +maxItems: 1 + +allOf: + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-top + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) + +clock-names: + items: +- const: oscclk + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-apm + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: CMU_APM bus clock (from CMU_TOP) + +clock-names: + items: +- const: oscclk +- const: dout_clkcmu_apm_bus + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-aud + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: AUD clock (from CMU_TOP) + +clock-names: + items: +- const: oscclk +- const: dout_aud + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-cmgp + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: CMU_CMGP bus clock (from CMU_APM) + +clock-names: + items: +- const: oscclk +- const: gout_clkcmu_cmgp_bus + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-core + +then: + properties: +clocks: + items: +- description: External reference clock (26 MHz) +- description: CMU_CORE bus clock (from CMU_TOP) +- description: CCI clock (from CMU_TOP) +- description: eMMC clock (from CMU_TOP) +- description: SSS clock (from CMU_TOP) + +clock-names: + items: +- const: oscclk +- const: dout_core_bus +- const: dout_core_cci +- const: dout_core_mmc_embd +- const: dout_core_sss + + - if: + properties: +compatible: + contains: +const: samsung,exynos850-cmu-dpu + +then: +
[PATCH 04/13] soc: samsung: Add Exynos USI driver
USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x1382 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Driver's code was copied over from Linux kernel [1] and adapted correspondingly for U-Boot API. UCLASS_MISC is used, and although no misc operations are implemented, it makes it easier to probe the driver this way (as compared to UCLASS_NOP) and keep the code compact. [1] drivers/soc/samsung/exynos-usi.c Signed-off-by: Sam Protsenko --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/samsung/Kconfig | 23 drivers/soc/samsung/Makefile | 3 + drivers/soc/samsung/exynos-usi.c | 218 +++ 5 files changed, 246 insertions(+) create mode 100644 drivers/soc/samsung/Kconfig create mode 100644 drivers/soc/samsung/Makefile create mode 100644 drivers/soc/samsung/exynos-usi.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 85dac9de78a4..03433bc0e6d2 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -40,6 +40,7 @@ config SOC_XILINX_VERSAL_NET This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +source "drivers/soc/samsung/Kconfig" source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 84385650d46d..610bf816d40a 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig new file mode 100644 index ..ffb87fe79316 --- /dev/null +++ b/drivers/soc/samsung/Kconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0+ + +menuconfig SOC_SAMSUNG + bool "Samsung SoC drivers support" + +if SOC_SAMSUNG + +config EXYNOS_USI + bool "Exynos USI (Universal Serial Interface) driver" + depends on ARCH_EXYNOS + select MISC + select REGMAP + select SYSCON + help + Enable support for USI block. USI (Universal Serial Interface) is an + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and + ExynosAutoV9. USI block can be configured to provide one of the + following serial protocols: UART, SPI or High Speed I2C. + + This driver allows one to configure USI for desired protocol, which + is usually done in USI node in Device Tree. + +endif diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile new file mode 100644 index ..833ac073fbfa --- /dev/null +++ b/drivers/soc/samsung/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c new file mode 100644 index ..23255177e6e3 --- /dev/null +++ b/drivers/soc/samsung/exynos-usi.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko + * + * Samsung Exynos USI driver (Universal Serial Interface). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* USIv2: System Register: SW_CONF register bits */ +#define USI_V2_SW_CONF_NONE0x0 +#define USI_V2_SW_CONF_UARTBIT(0) +#define USI_V2_SW_CONF_SPI BIT(1) +#define USI_V2_SW_CONF_I2C BIT(2
[PATCH 05/13] soc: samsung: Add Exynos PMU driver
Add basic Power Management Unit (PMU) driver for Exynos SoCs. For now
it's only capable of changing UART path in PMU, which is needed for
E850-96 board. The driver's structure resembles the exynos-pmu driver
from Linux kernel, and although it's very basic and slim at the moment,
it can be easily extended in future if the need arises.
UCLASS_NOP is used, as there are no benefits in using more elaborate
classes like UCLASS_MISC in this case. The DM_FLAG_PROBE_AFTER_BIND flag
is added in bind function, as the probe function must be always called
for this driver.
Signed-off-by: Sam Protsenko
---
drivers/soc/samsung/Kconfig | 10 +++
drivers/soc/samsung/Makefile | 1 +
drivers/soc/samsung/exynos-pmu.c | 102 +++
3 files changed, 113 insertions(+)
create mode 100644 drivers/soc/samsung/exynos-pmu.c
diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
index ffb87fe79316..737b7ca8cd19 100644
--- a/drivers/soc/samsung/Kconfig
+++ b/drivers/soc/samsung/Kconfig
@@ -5,6 +5,16 @@ menuconfig SOC_SAMSUNG
if SOC_SAMSUNG
+config EXYNOS_PMU
+ bool "Exynos PMU controller driver"
+ depends on ARCH_EXYNOS
+ select REGMAP
+ select SYSCON
+ help
+ Enable support for system controller configuration driver. It allows
+ one to configure system controller registers (e.g. some register in
+ PMU syscon) by providing register's offset, mask and value.
+
config EXYNOS_USI
bool "Exynos USI (Universal Serial Interface) driver"
depends on ARCH_EXYNOS
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
index 833ac073fbfa..0eb3ed8353b0 100644
--- a/drivers/soc/samsung/Makefile
+++ b/drivers/soc/samsung/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
new file mode 100644
index ..233ad4a908f5
--- /dev/null
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko
+ *
+ * Exynos PMU (Power Management Unit) driver.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define EXYNOS850_UART_IO_SHARE_CTRL 0x0760
+#define SEL_RXD_AP_UART_SHIFT 16
+#define SEL_RXD_AP_UART_MASK GENMASK(17, 16)
+#define SEL_TXD_GPIO_1_SHIFT 20
+#define SEL_TXD_GPIO_1_MASKGENMASK(21, 20)
+#define RXD_GPIO_1 0x3
+#define TXD_AP_UART0x0
+
+struct exynos_pmu {
+ struct udevice *dev;
+ const struct exynos_pmu_data *pmu_data;
+ struct regmap *regmap;
+};
+
+struct exynos_pmu_data {
+ int (*pmu_init)(struct exynos_pmu *priv);
+};
+
+static int exynos850_pmu_init(struct exynos_pmu *priv)
+{
+ ofnode node;
+ bool uart_debug_1;
+ unsigned int offset, mask, value;
+
+ node = dev_ofnode(priv->dev);
+ uart_debug_1 = ofnode_read_bool(node, "samsung,uart-debug-1");
+ if (!uart_debug_1)
+ return 0;
+
+ /*
+* If uart1_pins are used for serial, AP UART lines have to be muxed
+* in PMU block to UART_DEBUG_1 path (GPIO_1). By default (reset value)
+* UART_DEBUG_0 path (uart0_pins) is connected to AP UART lines.
+*/
+ offset = EXYNOS850_UART_IO_SHARE_CTRL;
+ mask = SEL_RXD_AP_UART_MASK | SEL_TXD_GPIO_1_MASK;
+ value = RXD_GPIO_1 << SEL_RXD_AP_UART_SHIFT |
+ TXD_AP_UART << SEL_TXD_GPIO_1_SHIFT;
+ return regmap_update_bits(priv->regmap, offset, mask, value);
+}
+
+static const struct exynos_pmu_data exynos850_pmu_data = {
+ .pmu_init = exynos850_pmu_init,
+};
+
+static int exynos_pmu_bind(struct udevice *dev)
+{
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+ return 0;
+}
+
+static int exynos_pmu_probe(struct udevice *dev)
+{
+ ofnode node;
+ struct exynos_pmu *priv;
+
+ priv = dev_get_priv(dev);
+ priv->dev = dev;
+
+ node = dev_ofnode(dev);
+ priv->regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->pmu_data = (struct exynos_pmu_data *)dev_get_driver_data(dev);
+ if (priv->pmu_data && priv->pmu_data->pmu_init)
+ return priv->pmu_data->pmu_init(priv);
+
+ return 0;
+}
+
+static const struct udevice_id exynos_pmu_ids[] = {
+ {
+ .compatible = "samsung,exynos850-pmu",
+ .data = (ulong)_pmu_data
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(exynos_pmu) = {
+ .name = "exynos-pmu",
+ .id = UCLASS_NOP,
+ .of_match
[PATCH 02/13] dt-bindings: soc: samsung: Add Exynos PMU
Add bindings documentation for Exynos PMU hardware block. It was taken
from Linux kernel [1], but minimized and modified to reflect features
that will be actually supported in U-Boot soon. For example,
the "samsung,uart-debug-1" property is not available in Linux kernel
bindings and only present in U-Boot.
[1] Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
Signed-off-by: Sam Protsenko
---
.../soc/samsung/exynos-pmu.yaml | 85 +++
1 file changed, 85 insertions(+)
create mode 100644 doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
new file mode 100644
index ..c3e95c33b01d
--- /dev/null
+++ b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC series Power Management Unit (PMU)
+
+maintainers:
+ - Sam Protsenko
+
+description: |+
+ PMU block controls the power and operation states of Exynos SoC. It contains
+ registers for changing the state of next features::
+
+ - Local power control. Exynos SoCs have various power domains, and it's
+possible to turn them on and off independently, using corresponding
+registers in PMU block
+ - System-level power control. That allows putting the system into power-down
+modes (sleep) by turning off the power for most of the domains
+ - Miscellaneous PMU related features
+
+# Custom select to avoid matching all nodes with 'syscon'
+select:
+ properties:
+compatible:
+ contains:
+enum:
+ - samsung,exynos850-pmu
+ required:
+- compatible
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - enum:
+ - samsung,exynos850-pmu
+ - const: syscon
+
+ reg:
+maxItems: 1
+
+ samsung,uart-debug-1:
+type: boolean
+description:
+ Enable this property if AP UART lines (Application Processor UART) must
be
+ connected to UART_DEBUG_1 path in PMU block. That's usually needed when
+ the serial console is provided by uart1_pins. If this property is not
+ specified, the default behavior will be used (AP UART lines connected to
+ UART_DEBUG_0 path, which usually means uart0_pins are used for the serial
+ console).
+
+ syscon-poweroff:
+$ref: /schemas/power/reset/syscon-poweroff.yaml#
+type: object
+description:
+ Node for power off method
+
+ syscon-reboot:
+$ref: /schemas/power/reset/syscon-reboot.yaml#
+type: object
+description:
+ Node for reboot method
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+pmu_system_controller: system-controller@1186 {
+compatible = "samsung,exynos850-pmu", "syscon";
+reg = <0x1186 0x1>;
+
+reboot: syscon-reboot {
+compatible = "syscon-reboot";
+regmap = <_system_controller>;
+offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
+mask = <0x2>; /* SWRESET_SYSTEM */
+value = <0x2>; /* reset value */
+};
+};
--
2.39.2
[PATCH 01/13] dt-bindings: soc: samsung: Add Exynos USI
Add USI bindings documentation and header file. Those are taken from
Linux kernel [1,2], but the documentation was reworked a bit to only
describe the compatibles that will be supported in U-Boot soon.
[1] Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
[2] include/dt-bindings/soc/samsung,exynos-usi.h
Signed-off-by: Sam Protsenko
---
.../soc/samsung/exynos-usi.yaml | 162 ++
include/dt-bindings/soc/samsung,exynos-usi.h | 17 ++
2 files changed, 179 insertions(+)
create mode 100644 doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
create mode 100644 include/dt-bindings/soc/samsung,exynos-usi.h
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
new file mode 100644
index ..8e6423f11568
--- /dev/null
+++ b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung's Exynos USI (Universal Serial Interface)
+
+maintainers:
+ - Sam Protsenko
+
+description: |
+ USI IP-core provides selectable serial protocol (UART, SPI or High-Speed
I2C).
+ USI shares almost all internal circuits within each protocol, so only one
+ protocol can be chosen at a time. USI is modeled as a node with zero or more
+ child nodes, each representing a serial sub-node device. The mode setting
+ selects which particular function will be used.
+
+properties:
+ $nodename:
+pattern: "^usi@[0-9a-f]+$"
+
+ compatible:
+enum:
+ - samsung,exynos850-usi
+
+ reg: true
+
+ clocks: true
+
+ clock-names: true
+
+ ranges: true
+
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 1
+
+ samsung,sysreg:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+items:
+ - items:
+ - description: phandle to System Register syscon node
+ - description: offset of SW_CONF register for this USI controller
+description:
+ Should be phandle/offset pair. The phandle to System Register syscon node
+ (for the same domain where this USI controller resides) and the offset
+ of SW_CONF register for this USI controller.
+
+ samsung,mode:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ Selects USI function (which serial protocol to use). Refer to
+ for valid USI mode values.
+
+ samsung,clkreq-on:
+type: boolean
+description:
+ Enable this property if underlying protocol requires the clock to be
+ continuously provided without automatic gating. As suggested by SoC
+ manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
+ multi-master mode. Usually this property is needed if USI mode is set
+ to "UART".
+
+ This property is optional.
+
+patternProperties:
+ "^i2c@[0-9a-f]+$":
+$ref: /schemas/i2c/i2c-exynos5.yaml
+description: Child node describing underlying I2C
+
+ "^serial@[0-9a-f]+$":
+$ref: /schemas/serial/samsung_uart.yaml
+description: Child node describing underlying UART/serial
+
+ "^spi@[0-9a-f]+$":
+$ref: /schemas/spi/samsung,spi.yaml
+description: Child node describing underlying SPI
+
+required:
+ - compatible
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+ - samsung,sysreg
+ - samsung,mode
+
+if:
+ properties:
+compatible:
+ contains:
+enum:
+ - samsung,exynos850-usi
+
+then:
+ properties:
+reg:
+ maxItems: 1
+
+clocks:
+ items:
+- description: Bus (APB) clock
+- description: Operating clock for UART/SPI/I2C protocol
+
+clock-names:
+ items:
+- const: pclk
+- const: ipclk
+
+ required:
+- reg
+- clocks
+- clock-names
+
+else:
+ properties:
+reg: false
+clocks: false
+clock-names: false
+samsung,clkreq-on: false
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+usi0: usi@138200c0 {
+compatible = "samsung,exynos850-usi";
+reg = <0x138200c0 0x20>;
+samsung,sysreg = <_peri 0x1010>;
+samsung,mode = ;
+samsung,clkreq-on; /* needed for UART mode */
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+clocks = <_peri 32>, <_peri 31>;
+clock-names = "pclk", "ipclk";
+
+serial_0: serial@1382 {
+compatible = "samsung,exynos850-uart";
+reg = <0x1382 0xc0>;
+interrupts = ;
+clocks = <_peri 32>, <_peri 31>;
+clock-names = "uart", "clk_uart_baud0";
+status = "disabled";
+
[PATCH 00/13] arm: exynos: Add E850-96 board
NOTE: This patch series depends on "pinctrl: exynos: Prepare for other
SoCs support" series [1]. It should be applied first.
Add Exynos850 SoC and WinLink's E850-96 board support. A short overview
of series additions and modifications:
* USI driver: configures UART block
* PMU driver: connects AP UART lines to uart1 pins)
* Exynos850 clock driver: generates UART clocks
* Exynos850 pinctrl driver: mux UART pins
* serial_s5p: UART driver
* Exynos850 SoC: dtsi files and MMU maps
* E850-96 board: dts files, defconfig, board file and doc
Most of the code was borrowed from mainline Linux kernel (where this
board is already enabled) and adapted for U-Boot. Preliminary
preparation for this series includes next patches / series (already
merged):
* commit 585a2aaac2ac ("arm: exynos: Include missing CPU header in
soc.c")
* commit c9ab9f30c8e4 ("arm: exynos: Include missing CPU header in
gpio.h")
* commit 11bd2787deff ("watchdog: s5p_wdt: Include missing CPU
header")
* commit 08cfa971a717 ("exynos: Avoid duplicate reset_cpu with
SYSRESET enabled")
* commit f655090901dc ("clk: exynos: Add header guard for clk-pll.h")
* commit 2227f4c0afed ("serial: s5p: Fix clk_get_by_index() error code
check")
* commit a0615ffc99a5 ("serial: s5p: Remove common.h inclusion")
* commit 5ad21de6bae0 ("serial: s5p: Use livetree API to get "id"
property")
* commit e79f630dbf67 ("serial: s5p: Use named constants for register
values")
* commit a627f2802a71 ("serial: s5p: Improve coding style")
* commit 33e7ca5a9b6a ("serial: s5p: Use dev_read_addr_ptr() to get
base address")
* commit 6219b47c4d91 ("board: samsung: Fix SYS_CONFIG_NAME configs in
axy17lte Kconfig")
* commit 470682ace1e0 ("configs: Remove unneeded SYS_CONFIG_NAME from
a*y17lte defconfigs")
and series [1] (dependency) is still pending.
For more detailed description please see the board documentation (added
in PATCH #12) and corresponding commit messages.
[1] https://lists.denx.de/pipermail/u-boot/2023-November/539033.html
Sam Protsenko (13):
dt-bindings: soc: samsung: Add Exynos USI
dt-bindings: soc: samsung: Add Exynos PMU
dt-bindings: clock: Add Exynos850 clock controller
soc: samsung: Add Exynos USI driver
soc: samsung: Add Exynos PMU driver
clk: exynos: Move pll code into clk-exynos7420
clk: exynos: Add Samsung clock framework
clk: exynos: Add Exynos850 clock driver
pinctrl: exynos: Add pinctrl support for Exynos850
serial: s5p: Add Exynos850 compatible
arm: exynos: Add Exynos850 SoC support
board: samsung: Add support for E850-96 board
MAINTAINERS: Add new Samsung subsystems
MAINTAINERS | 25 +
arch/arm/dts/Makefile |1 +
arch/arm/dts/exynos-pinctrl.h | 79 +
arch/arm/dts/exynos850-e850-96-u-boot.dtsi| 37 +
arch/arm/dts/exynos850-e850-96.dts| 273
arch/arm/dts/exynos850-pinctrl.dtsi | 663 +
arch/arm/dts/exynos850.dtsi | 809 +++
arch/arm/mach-exynos/Kconfig | 28 +-
arch/arm/mach-exynos/mmu-arm64.c | 34 +
board/samsung/e850-96/Kconfig | 16 +
board/samsung/e850-96/MAINTAINERS |9 +
board/samsung/e850-96/Makefile|6 +
board/samsung/e850-96/e850-96.c | 22 +
configs/e850-96_defconfig | 21 +
doc/board/samsung/e850-96.rst | 87 ++
.../img/exynos850-boot-architecture.svg | 1283 +
doc/board/samsung/index.rst |1 +
.../clock/samsung,exynos850-clock.yaml| 307
.../soc/samsung/exynos-pmu.yaml | 85 ++
.../soc/samsung/exynos-usi.yaml | 162 +++
drivers/clk/exynos/Kconfig|7 +
drivers/clk/exynos/Makefile | 11 +-
drivers/clk/exynos/clk-exynos7420.c | 25 +-
drivers/clk/exynos/clk-exynos850.c| 189 +++
drivers/clk/exynos/clk-pll.c | 167 ++-
drivers/clk/exynos/clk-pll.h | 16 +-
drivers/clk/exynos/clk.c | 121 ++
drivers/clk/exynos/clk.h | 228 +++
drivers/pinctrl/exynos/Kconfig|8 +
drivers/pinctrl/exynos/Makefile |1 +
drivers/pinctrl/exynos/pinctrl-exynos850.c| 125 ++
drivers/serial/serial_s5p.c |1 +
drivers/soc/Kconfig |1 +
drivers/soc/Makefile |
Re: [PATCH 0/7] pinctrl: exynos: Prepare for other SoCs support
On Thu, Nov 30, 2023 at 2:13 PM Sam Protsenko wrote: > > Some Exynos SoCs (not supported by pinctrl-exynos driver yet) have > different offsets and widths of pin bank registers (i.e. PIN_CON, > PIN_PUD and PIN_DRV registers). Rework pinctrl-exynos driver so it > allows for different offsets and widths of those registers by adding > the corresponding API. That makes it possible to add the support for > new Exynos SoCs in pinctrl-exynos driver. > > The main patch in this series is: > > pinctrl: exynos: Support different register types in pin banks > > Other patches are just related cleanups and refactoring commits, > required for the clean implementation of the main patch. > > Sam Protsenko (7): > pinctrl: exynos: Improve coding style > pinctrl: exynos: Extract pin parsing code into a separate function > pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name > pinctrl: exynos: Support different register types in pin banks > pinctrl: exynos: Refactor handling the pin related dt properties > pinctrl: exynos: Reduce variables scope > pinctrl: exynos: Convert to use livetree API for fdt access > > drivers/pinctrl/exynos/pinctrl-exynos.c | 125 > drivers/pinctrl/exynos/pinctrl-exynos.h | 36 +- > drivers/pinctrl/exynos/pinctrl-exynos7420.c | 2 + > 3 files changed, 108 insertions(+), 55 deletions(-) > > -- Hi Minkyu, If there are no objections to this series, can you please apply it? Thanks! > 2.39.2 >
[PATCH 7/7] pinctrl: exynos: Convert to use livetree API for fdt access
Use counterpart dev_read_* functions instead of fdt* ones. It fixes
checkpatch warnings like this:
WARNING: Use the livetree API (dev_read_...)
#54: FILE: drivers/pinctrl/exynos/pinctrl-exynos.c:137:
pinvals[idx] = fdtdec_get_int(fdt, node,
and also makes it possible to avoid using the global data pointer in the
driver.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index b6af3befbf9b..8a045cdf7aa8 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -9,12 +9,9 @@
#include
#include
#include
-#include
#include
#include "pinctrl-exynos.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* CON, DAT, PUD, DRV */
const struct samsung_pin_bank_type bank_type_alive = {
.fld_width = { 4, 1, 2, 2, },
@@ -118,8 +115,6 @@ static void exynos_pinctrl_set_pincfg(unsigned long
reg_base, u32 pin_num,
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(config);
unsigned int count, idx;
unsigned int pinvals[PINCFG_TYPE_NUM];
@@ -127,13 +122,13 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
* refer to the following document for the pinctrl bindings
* linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
*/
- count = fdt_stringlist_count(fdt, node, "samsung,pins");
+ count = dev_read_string_count(config, "samsung,pins");
if (count <= 0)
return -EINVAL;
for (idx = 0; idx < PINCFG_TYPE_NUM; ++idx) {
- pinvals[idx] = fdtdec_get_int(fdt, node,
- exynos_pinctrl_props[idx], -1);
+ pinvals[idx] = dev_read_u32_default(config,
+ exynos_pinctrl_props[idx], -1);
}
pinvals[PINCFG_TYPE_DAT] = -1; /* ignore GPIO data register */
@@ -142,12 +137,13 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
unsigned int pin_num;
char bank_name[10];
unsigned long reg;
- const char *name;
- int pincfg;
+ const char *name = NULL;
+ int pincfg, err;
- name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
- if (!name)
+ err = dev_read_string_index(config, "samsung,pins", idx, );
+ if (err || !name)
continue;
+
parse_pin(name, _num, bank_name);
bank = get_bank(dev, bank_name);
reg = priv->base + bank->offset;
--
2.39.2
[PATCH 6/7] pinctrl: exynos: Reduce variables scope
Pull some variables declared in exynos_pinctrl_set_state() into its
loop, to reduce their scope. Style commit, no functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index e79ce5113d84..b6af3befbf9b 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -120,10 +120,8 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(config);
- unsigned int count, idx, pin_num;
+ unsigned int count, idx;
unsigned int pinvals[PINCFG_TYPE_NUM];
- unsigned long reg;
- const char *name;
/*
* refer to the following document for the pinctrl bindings
@@ -141,7 +139,10 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
for (idx = 0; idx < count; idx++) {
const struct samsung_pin_bank_data *bank;
+ unsigned int pin_num;
char bank_name[10];
+ unsigned long reg;
+ const char *name;
int pincfg;
name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
--
2.39.2
[PATCH 5/7] pinctrl: exynos: Refactor handling the pin related dt properties
All pin related dt properties (pin-function, pin-pud and pin-drv) are
handled in a very similar way. Get rid of that code duplication by
extracting the corresponding data knowledge into an actual data
structure (array), and then just iterating over it.
No functional change, it's a refactoring commit.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 35 ++---
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 9a51653be864..e79ce5113d84 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -21,6 +21,13 @@ const struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
+static const char * const exynos_pinctrl_props[PINCFG_TYPE_NUM] = {
+ [PINCFG_TYPE_FUNC] = "samsung,pin-function",
+ [PINCFG_TYPE_DAT] = "samsung,pin-val",
+ [PINCFG_TYPE_PUD] = "samsung,pin-pud",
+ [PINCFG_TYPE_DRV] = "samsung,pin-drv",
+};
+
/**
* exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
* conf: soc specific pin configuration data array
@@ -114,7 +121,7 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
- unsigned int pinfunc, pinpud, pindrv;
+ unsigned int pinvals[PINCFG_TYPE_NUM];
unsigned long reg;
const char *name;
@@ -126,13 +133,16 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
if (count <= 0)
return -EINVAL;
- pinfunc = fdtdec_get_int(fdt, node, "samsung,pin-function", -1);
- pinpud = fdtdec_get_int(fdt, node, "samsung,pin-pud", -1);
- pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
+ for (idx = 0; idx < PINCFG_TYPE_NUM; ++idx) {
+ pinvals[idx] = fdtdec_get_int(fdt, node,
+ exynos_pinctrl_props[idx], -1);
+ }
+ pinvals[PINCFG_TYPE_DAT] = -1; /* ignore GPIO data register */
for (idx = 0; idx < count; idx++) {
const struct samsung_pin_bank_data *bank;
char bank_name[10];
+ int pincfg;
name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
if (!name)
@@ -141,19 +151,12 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
bank = get_bank(dev, bank_name);
reg = priv->base + bank->offset;
- if (pinfunc != -1) {
- exynos_pinctrl_set_pincfg(reg, pin_num, pinfunc,
- PINCFG_TYPE_FUNC, bank->type);
- }
-
- if (pinpud != -1) {
- exynos_pinctrl_set_pincfg(reg, pin_num, pinpud,
- PINCFG_TYPE_PUD, bank->type);
- }
+ for (pincfg = 0; pincfg < PINCFG_TYPE_NUM; ++pincfg) {
+ unsigned int val = pinvals[pincfg];
- if (pindrv != -1) {
- exynos_pinctrl_set_pincfg(reg, pin_num, pindrv,
- PINCFG_TYPE_DRV, bank->type);
+ if (val != -1)
+ exynos_pinctrl_set_pincfg(reg, pin_num, val,
+ pincfg, bank->type);
}
}
--
2.39.2
[PATCH 4/7] pinctrl: exynos: Support different register types in pin banks
Get rid of hard-coded register offsets and widths. Instead provide a way
for pinctrl drivers to specify different pin bank register offsets and
widths. This in turn makes it possible to add support for new SoCs that
have registers with offset/width values different than generic ones
already available in pinctrl-exynos driver.
Offset constants (now unused in pinctrl-exynos.c) are moved to
pinctrl-exynos7420 driver, which is the single user of those constants.
The design of this patch follows Linux kernel pinctrl-exynos driver
design, in terms of added data structures and types. This patch doesn't
add support for any new SoCs and shouldn't introduce any functional
changes.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 42 ++---
drivers/pinctrl/exynos/pinctrl-exynos.h | 34 +++--
drivers/pinctrl/exynos/pinctrl-exynos7420.c | 2 +
3 files changed, 61 insertions(+), 17 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index d908927135b6..9a51653be864 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -15,6 +15,12 @@
DECLARE_GLOBAL_DATA_PTR;
+/* CON, DAT, PUD, DRV */
+const struct samsung_pin_bank_type bank_type_alive = {
+ .fld_width = { 4, 1, 2, 2, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
/**
* exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
* conf: soc specific pin configuration data array
@@ -81,6 +87,22 @@ static const struct samsung_pin_bank_data *get_bank(struct
udevice *dev,
return NULL;
}
+static void exynos_pinctrl_set_pincfg(unsigned long reg_base, u32 pin_num,
+ u32 val, enum pincfg_type pincfg,
+ const struct samsung_pin_bank_type *type)
+{
+ u32 width = type->fld_width[pincfg];
+ u32 reg_offset = type->reg_offset[pincfg];
+ u32 mask = (1 << width) - 1;
+ u32 shift = pin_num * width;
+ u32 data;
+
+ data = readl(reg_base + reg_offset);
+ data &= ~(mask << shift);
+ data |= val << shift;
+ writel(data, reg_base + reg_offset);
+}
+
/**
* exynos_pinctrl_set_state: configure a pin state.
* dev: the pinctrl device to be configured.
@@ -93,7 +115,7 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
unsigned int pinfunc, pinpud, pindrv;
- unsigned long reg, value;
+ unsigned long reg;
const char *name;
/*
@@ -120,24 +142,18 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
reg = priv->base + bank->offset;
if (pinfunc != -1) {
- value = readl(reg + PIN_CON);
- value &= ~(0xf << (pin_num << 2));
- value |= (pinfunc << (pin_num << 2));
- writel(value, reg + PIN_CON);
+ exynos_pinctrl_set_pincfg(reg, pin_num, pinfunc,
+ PINCFG_TYPE_FUNC, bank->type);
}
if (pinpud != -1) {
- value = readl(reg + PIN_PUD);
- value &= ~(0x3 << (pin_num << 1));
- value |= (pinpud << (pin_num << 1));
- writel(value, reg + PIN_PUD);
+ exynos_pinctrl_set_pincfg(reg, pin_num, pinpud,
+ PINCFG_TYPE_PUD, bank->type);
}
if (pindrv != -1) {
- value = readl(reg + PIN_DRV);
- value &= ~(0x3 << (pin_num << 1));
- value |= (pindrv << (pin_num << 1));
- writel(value, reg + PIN_DRV);
+ exynos_pinctrl_set_pincfg(reg, pin_num, pindrv,
+ PINCFG_TYPE_DRV, bank->type);
}
}
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h
b/drivers/pinctrl/exynos/pinctrl-exynos.h
index 6b19f196bc3a..743bb5573091 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.h
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -8,25 +8,51 @@
#ifndef __PINCTRL_EXYNOS_H_
#define __PINCTRL_EXYNOS_H_
-#define PIN_CON0x00/* Offset of pin function register */
-#define PIN_DAT0x04/* Offset of pin data register */
-#define PIN_PUD0x08/* Offset of pin pull up/down config
register */
-#define PIN_DRV0x0C/* Offset of pin drive strength
register */
+/**
+ * enum pincfg_type - possible pin configuration types supported.
+ * @PINCFG_TYP
[PATCH 3/7] pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name
Rework pin_to_bank_base() function to obtain bank data structure by bank
name instead of getting bank base address by pin name, and rename it to
get_bank() to reflect this change. This in turn leads to the extraction
of parse_pin(), so the caller has to use it before calling get_bank().
No functional change. This is a refactoring commit which prepares
pinctrl driver code for handling different sizes of register fields,
which will be added next.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 27 +
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 2d194ba0a4b5..d908927135b6 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -50,17 +50,14 @@ static void parse_pin(const char *pin_name, u32 *pin, char
*bank_name)
*pin = pin_name[++idx] - '0';
}
-/* given a pin-name, return the address of pin config registers */
-static unsigned long pin_to_bank_base(struct udevice *dev, const char
*pin_name,
- u32 *pin)
+/* given a bank name, find out the pin bank structure */
+static const struct samsung_pin_bank_data *get_bank(struct udevice *dev,
+ const char *bank_name)
{
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
const struct samsung_pin_ctrl *pin_ctrl_array = priv->pin_ctrl;
const struct samsung_pin_bank_data *bank_data;
- u32 nr_banks, pin_ctrl_idx = 0, idx = 0, bank_base;
- char bank[10];
-
- parse_pin(pin_name, pin, bank);
+ u32 nr_banks, pin_ctrl_idx = 0, idx = 0;
/* lookup the pin bank data using the pin bank name */
while (true) {
@@ -75,15 +72,13 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
for (idx = 0; idx < nr_banks; idx++) {
debug("pinctrl[%d] bank_data[%d] name is: %s\n",
pin_ctrl_idx, idx, bank_data[idx].name);
- if (!strcmp(bank, bank_data[idx].name)) {
- bank_base = priv->base + bank_data[idx].offset;
- break;
- }
+ if (!strcmp(bank_name, bank_data[idx].name))
+ return _data[idx];
}
pin_ctrl_idx++;
}
- return bank_base;
+ return NULL;
}
/**
@@ -93,6 +88,7 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
*/
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
+ struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
@@ -113,10 +109,15 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
for (idx = 0; idx < count; idx++) {
+ const struct samsung_pin_bank_data *bank;
+ char bank_name[10];
+
name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
if (!name)
continue;
- reg = pin_to_bank_base(dev, name, _num);
+ parse_pin(name, _num, bank_name);
+ bank = get_bank(dev, bank_name);
+ reg = priv->base + bank->offset;
if (pinfunc != -1) {
value = readl(reg + PIN_CON);
--
2.39.2
[PATCH 2/7] pinctrl: exynos: Extract pin parsing code into a separate function
Next commits are going to re-design the pin_to_bank_base() function and
its usage in a way that the pin parsing code will be called separately.
Extract it into a separate function first, as a refactoring commit.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 27 -
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 995a3a0ee5fd..2d194ba0a4b5 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -34,6 +34,22 @@ void exynos_pinctrl_setup_peri(struct
exynos_pinctrl_config_data *conf,
}
}
+static void parse_pin(const char *pin_name, u32 *pin, char *bank_name)
+{
+ u32 idx = 0;
+
+ /*
+* The format of the pin name is -.
+* Example: gpa0-4 (gpa0 is the bank_name name and 4 is the pin number.
+*/
+ while (pin_name[idx] != '-') {
+ bank_name[idx] = pin_name[idx];
+ idx++;
+ }
+ bank_name[idx] = '\0';
+ *pin = pin_name[++idx] - '0';
+}
+
/* given a pin-name, return the address of pin config registers */
static unsigned long pin_to_bank_base(struct udevice *dev, const char
*pin_name,
u32 *pin)
@@ -44,16 +60,7 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
u32 nr_banks, pin_ctrl_idx = 0, idx = 0, bank_base;
char bank[10];
- /*
-* The format of the pin name is -.
-* Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number.
-*/
- while (pin_name[idx] != '-') {
- bank[idx] = pin_name[idx];
- idx++;
- }
- bank[idx] = '\0';
- *pin = pin_name[++idx] - '0';
+ parse_pin(pin_name, pin, bank);
/* lookup the pin bank data using the pin bank name */
while (true) {
--
2.39.2
[PATCH 1/7] pinctrl: exynos: Improve coding style
Style commit, no functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 3 ++-
drivers/pinctrl/exynos/pinctrl-exynos.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/pinctrl-exynos.c
index 898185479ba3..995a3a0ee5fd 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -57,7 +57,8 @@ static unsigned long pin_to_bank_base(struct udevice *dev,
const char *pin_name,
/* lookup the pin bank data using the pin bank name */
while (true) {
- const struct samsung_pin_ctrl *pin_ctrl =
_ctrl_array[pin_ctrl_idx];
+ const struct samsung_pin_ctrl *pin_ctrl =
+ _ctrl_array[pin_ctrl_idx];
nr_banks = pin_ctrl->nr_banks;
if (!nr_banks)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h
b/drivers/pinctrl/exynos/pinctrl-exynos.h
index cbc5174b48cb..6b19f196bc3a 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.h
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -27,7 +27,7 @@ struct samsung_pin_bank_data {
#define EXYNOS_PIN_BANK(pins, reg, id) \
{ \
- .offset = reg, \
+ .offset = reg, \
.nr_pins= pins, \
.name = id\
}
--
2.39.2
[PATCH 0/7] pinctrl: exynos: Prepare for other SoCs support
Some Exynos SoCs (not supported by pinctrl-exynos driver yet) have different offsets and widths of pin bank registers (i.e. PIN_CON, PIN_PUD and PIN_DRV registers). Rework pinctrl-exynos driver so it allows for different offsets and widths of those registers by adding the corresponding API. That makes it possible to add the support for new Exynos SoCs in pinctrl-exynos driver. The main patch in this series is: pinctrl: exynos: Support different register types in pin banks Other patches are just related cleanups and refactoring commits, required for the clean implementation of the main patch. Sam Protsenko (7): pinctrl: exynos: Improve coding style pinctrl: exynos: Extract pin parsing code into a separate function pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name pinctrl: exynos: Support different register types in pin banks pinctrl: exynos: Refactor handling the pin related dt properties pinctrl: exynos: Reduce variables scope pinctrl: exynos: Convert to use livetree API for fdt access drivers/pinctrl/exynos/pinctrl-exynos.c | 125 drivers/pinctrl/exynos/pinctrl-exynos.h | 36 +- drivers/pinctrl/exynos/pinctrl-exynos7420.c | 2 + 3 files changed, 108 insertions(+), 55 deletions(-) -- 2.39.2
Re: [PATCH 0/4] serial: s5p: Cleanups
On Tue, Nov 7, 2023 at 1:06 PM Sam Protsenko wrote: > > A small collection of cleanup patches for serial_s5p.c driver. Should > induce no functional changes. > > Sam Protsenko (4): > serial: s5p: Remove common.h inclusion > serial: s5p: Use livetree API to get "id" property > serial: s5p: Use named constants for register values > serial: s5p: Improve coding style > > drivers/serial/serial_s5p.c | 71 + > 1 file changed, 40 insertions(+), 31 deletions(-) > > -- + Minkyu Just a kind reminder to review this series. Thanks! > 2.39.2 >
Re: [PATCH v2 1/2] board: samsung: Fix SYS_CONFIG_NAME configs in axy17lte Kconfig
Hi Tom, Minkyu,
On Thu, Nov 9, 2023 at 2:13 PM Sam Protsenko wrote:
>
> There is a couple of issues related to SYS_CONFIG_NAME config in
> axy17lte Kconfig.
>
> 1. The global SYS_CONFIG_NAME in axy17lte Kconfig overrides
>SYS_CONFIG_NAME for all boards specified after this line in
>arch/arm/mach-exynos/Kconfig:
>
>source "board/samsung/axy17lte/Kconfig"
>
>Right now it's the last 'source' line there, so the issue is not
>reproducible. But once some board is moved or added after this line
>the next build error will happen:
>
>GEN include/autoconf.mk.dep
> In file included from ./include/common.h:16:
> include/config.h:3:10: fatal error: configs/exynos78x0-common.h.h:
> No such file or directory
> 3 | #include
>| ^~~
> compilation terminated.
>
>That's happening because axy17lte Kconfig defines SYS_CONFIG_NAME
>option in global namespace (not guarded with any "if TARGET_..."), so
>it basically rewrites the correct SYS_CONFIG_NAME defined in the
>hypothetical boards which might appear after axy17lte in mach-exynos
>Kconfig.
>
> 2. Another side of the issue is that SYS_CONFIG_NAME is defined
>incorrectly in axy17lte Kconfig:
>
>config SYS_CONFIG_NAME
>default "exynos78x0-common.h"
>
>The .h extension should not have been specified there. It's leading
>to a build error, as the generated include file has a double '.h'
>extension.
>
> 3. Each target in axy17lte/Kconfig defines its own SYS_CONFIG_NAME. But
>all of those in fact incorrect, as corresponding
>include/configs/.h header files don't exist.
>
> 4. The global SYS_CONFIG_NAME pretty much repeats the help description
>from arch/Kconfig and doc/README.kconfig.
>
> Corresponding defconfig files (a*y17lte_defconfig) fix above issues by
> overriding SYS_CONFIG_NAME and correctly setting it to
> "exynos78x0-common".
>
> Fix all mentioned issues by removing the incorrect global
> SYS_CONFIG_NAME and instead specifying it (correctly) in SYS_CONFIG_NAME
> options for each target instead.
>
> Signed-off-by: Sam Protsenko
> Fixes: 3e2095e960b4 ("board: samsung: add support for Galaxy A series of 2017
> (a5y17lte)")
> ---
If this series (v2) looks good to you, can you please apply it? It's
needed for the new Exynos dev board port I'm working on right now, and
expect to submit the patches soon.
Thanks!
> Changes in v2:
> - Don't just remove global SYS_CONFIG_NAME, also fix SYS_CONFIG_NAME
> for each target in Kconfig
>
> board/samsung/axy17lte/Kconfig | 14 +++---
> 1 file changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig
> index a018547ff5d4..64a4ffa7e673 100644
> --- a/board/samsung/axy17lte/Kconfig
> +++ b/board/samsung/axy17lte/Kconfig
> @@ -1,11 +1,3 @@
> -config SYS_CONFIG_NAME
> - string "Board configuration name"
> - default "exynos78x0-common.h"
> - help
> - This option contains information about board configuration name.
> - Based on this option include/configs/.h
> header
> - will be used for board configuration.
> -
> if TARGET_A5Y17LTE
> config SYS_BOARD
> default "axy17lte"
> @@ -16,7 +8,7 @@ config SYS_VENDOR
> default "samsung"
>
> config SYS_CONFIG_NAME
> - default "a5y17lte"
> + default "exynos78x0-common"
>
> config EXYNOS7880
> bool "Exynos 7880 SOC support"
> @@ -33,7 +25,7 @@ config SYS_VENDOR
> default "samsung"
>
> config SYS_CONFIG_NAME
> - default "a5y17lte"
> + default "exynos78x0-common"
>
> config EXYNOS7880
> bool "Exynos 7880 SOC support"
> @@ -50,7 +42,7 @@ config SYS_VENDOR
> default "samsung"
>
> config SYS_CONFIG_NAME
> - default "a3y17lte"
> + default "exynos78x0-common"
>
> config EXYNOS7870
> bool "Exynos 7870 SOC support"
> --
> 2.39.2
>
Re: [PATCH 2/4] serial: s5p: Use livetree API to get "id" property
On Mon, Nov 13, 2023 at 12:01 PM Simon Glass wrote:
> >
> > The 'port_id' seems to be needed for ARCH_EXYNOS4 boards. Because
> > Exynos4 doesn't have proper DM clocks, it uses 'id' property to get
> > corresponding UART clock frequency from its mach code.
> >
> > Here is what's happening in the serial driver in case of Exynos4:
> >
> > 1. get_uart_clk(port_id) is called
> > 2. which in turn calls exynos4_get_uart_clk(port_id)
> > 3. which uses "port_id" value to read corresponding bits of of
> > CLK_SRC_PERIL0 register
> > 4. those bits are used to get corresponding PLL clock's frequency
> > 5. which is in turn used to calculate UART clock rate
> > 6. calculated rate is returned by get_uart_clk() to serial driver
> >
> > So I don't see any *easy* way we can get rid of that id property.
> >
> > The proper way of doing that would require converting Exynos4 clock
> > code to CCF (enabling CONFIG_CLK_EXYNOS). Which of course also means
> > implementing clocks in dts, akin to kernel's exynos4.dtsi. Then it'll
> > be possible to get rid of 'id' property.
>
> That sounds good!
>
> >
> > Maybe I'm missing something, please let me know.
>
> An easy way in the meantime would be to look at the compatible / reg
> property, e.g. here is a sketch:
>
> static int get_id(ofnode node)
> {
> ulong addr = (ulong)plat->reg;
> if (ofnode_device_is_compatible(node, "samsung,exynos4210-uart")) {
> return (addr >> 16) & 0xf;
> ...
>
> reg = <0x1380 0x3c>;
> id = <0>;
> };
>
> serail_1: serial@1381 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x1381 0x3c>;
> id = <1>;
> };
>
> serial_2: serial@1382 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x1382 0x3c>;
> id = <2>;
> };
>
> serial_3: serial@1383 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x1383 0x3c>;
> id = <3>;
> };
>
> serial_4: serial@1384 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x1384 0x3c>;
> id = <4>;
>
To be honest, I'm a bit of busy right now working on U-Boot port for a
new Exynos dev board, which I want to finalize and upstream ASAP. Do
you think it's possible to take this one as is for now? At least it
fixes one issue (fdtdec API and global data pointer).
Thanks!
> Regards,
> Simon
Re: [PATCH 2/4] serial: s5p: Use livetree API to get "id" property
Hi Simon,
On Tue, Nov 7, 2023 at 10:26 PM Simon Glass wrote:
>
> Hi Sam,
>
> On Tue, 7 Nov 2023 at 12:06, Sam Protsenko wrote:
> >
> > Use dev_read_u8_default() instead of fdtdec_get_int() to read the "id"
> > property from device tree, as suggested in [1]. dev_* API is already
> > used in this driver, so there is no reason to stick to fdtdec_* API.
> > This also fixes checkpatch warning:
> >
> > WARNING: Use the livetree API (dev_read_...)
> >
> > [1] doc/develop/driver-model/livetree.rst
> >
> > Signed-off-by: Sam Protsenko
> > ---
> > drivers/serial/serial_s5p.c | 5 +
> > 1 file changed, 1 insertion(+), 4 deletions(-)
> >
> > diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
> > index 177215535676..c57bdd059ea6 100644
> > --- a/drivers/serial/serial_s5p.c
> > +++ b/drivers/serial/serial_s5p.c
> > @@ -20,8 +20,6 @@
> > #include
> > #include
> >
> > -DECLARE_GLOBAL_DATA_PTR;
> > -
> > enum {
> > PORT_S5P = 0,
> > PORT_S5L
> > @@ -220,8 +218,7 @@ static int s5p_serial_of_to_plat(struct udevice *dev)
> >
> > plat->reg = (struct s5p_uart *)addr;
> > plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
> > - plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
> > - "id", dev_seq(dev));
> > + plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev));
> >
> > if (port_type == PORT_S5L) {
> > plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
> > --
> > 2.39.2
> >
>
> Really this property should not be needed anymore. Can you figure out
> how to drop it?
>
The 'port_id' seems to be needed for ARCH_EXYNOS4 boards. Because
Exynos4 doesn't have proper DM clocks, it uses 'id' property to get
corresponding UART clock frequency from its mach code.
Here is what's happening in the serial driver in case of Exynos4:
1. get_uart_clk(port_id) is called
2. which in turn calls exynos4_get_uart_clk(port_id)
3. which uses "port_id" value to read corresponding bits of of
CLK_SRC_PERIL0 register
4. those bits are used to get corresponding PLL clock's frequency
5. which is in turn used to calculate UART clock rate
6. calculated rate is returned by get_uart_clk() to serial driver
So I don't see any *easy* way we can get rid of that id property.
The proper way of doing that would require converting Exynos4 clock
code to CCF (enabling CONFIG_CLK_EXYNOS). Which of course also means
implementing clocks in dts, akin to kernel's exynos4.dtsi. Then it'll
be possible to get rid of 'id' property.
Maybe I'm missing something, please let me know.
Thanks!
> Regards,
> Simon
Re: [PATCH v1 2/2] poplar: provide more space for kernel image
On Thu, Nov 9, 2023 at 4:34 PM Igor Opaniuk wrote: > > Adjust mem layout, providing more space for linux kernel image. > > This fixes the problem: > ERROR: FDT image overlaps OS image (OS=0x3000..0x3258) > > Signed-off-by: Igor Opaniuk > --- Reviewed-by: Sam Protsenko > > include/configs/poplar.h | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/include/configs/poplar.h b/include/configs/poplar.h > index 6e8adf9187..629b335f5d 100644 > --- a/include/configs/poplar.h > +++ b/include/configs/poplar.h > @@ -37,11 +37,11 @@ > "env_mmc_blknum=0xf80\0"\ > "env_mmc_nblks=0x80\0" \ > "kernel_addr_r=0x3000\0"\ > - "pxefile_addr_r=0x3200\0" \ > - "scriptaddr=0x3200\0" \ > - "fdt_addr_r=0x3220\0" \ > + "pxefile_addr_r=0x3300\0" \ > + "scriptaddr=0x3300\0" \ > + "fdt_addr_r=0x3320\0" \ > "fdtfile=hisilicon/hi3798cv200-poplar.dtb\0"\ > - "ramdisk_addr_r=0x3240\0" \ > + "ramdisk_addr_r=0x3340\0" \ > BOOTENV > > #endif /* _POPLAR_H_ */ > -- > 2.34.1 >
Re: [PATCH v1 1/2] poplar: use random mac address
On Thu, Nov 9, 2023 at 4:34 PM Igor Opaniuk wrote: > > Set CONFIG_NET_RANDOM_ETHADDR=y, which sets random eth address in > case there is no configuration provided neither in CONFIG_ETHADDR > nor in "ethaddr" env variable. > > This fixes the problem: > poplar# dhcp > Error: ethernet@9841000 address not set. > > Signed-off-by: Igor Opaniuk > --- Reviewed-by: Sam Protsenko > > configs/poplar_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig > index f0ab2319a4..b6e0c3166c 100644 > --- a/configs/poplar_defconfig > +++ b/configs/poplar_defconfig > @@ -22,6 +22,7 @@ CONFIG_CMD_USB=y > # CONFIG_ISO_PARTITION is not set > CONFIG_ENV_IS_IN_MMC=y > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_USB_FUNCTION_FASTBOOT=y > CONFIG_FASTBOOT_BUF_ADDR=0x2000 > CONFIG_FASTBOOT_BUF_SIZE=0x1000 > -- > 2.34.1 >
Re: [PATCH] board: samsung: Remove incorrect SYS_CONFIG_NAME in axy17lte Kconfig
On Thu, Nov 9, 2023 at 6:53 AM Tom Rini wrote: > > On Fri, Oct 20, 2023 at 01:42:53PM -0500, Sam Protsenko wrote: > > > The global SYS_CONFIG_NAME in axy17lte Kconfig overrides SYS_CONFIG_NAME > > for all boards specified after this line in > > arch/arm/mach-exynos/Kconfig: > > > > source "board/samsung/axy17lte/Kconfig" > > > > Right now it's the last 'source' line there, so the issue is not > > reproducible. But once some board is moved or added after this line the > > next build error will happen: > > Good spotting on this one. > > [snip] > > diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig > > index a018547ff5d4..209394a8a5a8 100644 > > --- a/board/samsung/axy17lte/Kconfig > > +++ b/board/samsung/axy17lte/Kconfig > > @@ -1,11 +1,3 @@ > > -config SYS_CONFIG_NAME > > - string "Board configuration name" > > - default "exynos78x0-common.h" > > - help > > - This option contains information about board configuration name. > > - Based on this option include/configs/.h > > header > > - will be used for board configuration. > > - > > if TARGET_A5Y17LTE > > config SYS_BOARD > > default "axy17lte" > > But this isn't right as Minkyu points out because SYS_CONFIG_NAME isn't > set for these platforms now. The fix is to do as > board/freescale/lx2160a/Kconfig does for example and have > SYS_CONFIG_NAME under each if TARGET_... stanza, even if we're repeating > the value. It may or may not look cleaner to do: > config SYS_CONFIG_NAME > default "exynos78x0-common.h" if TARGET_A5Y17LTE || \ > TARGET_A7Y17LTE || TARGET_A3Y17LTE > > In the file directly, instead. > Thanks for the review! I just sent v2 [1], hopefully addressing your and Minkyu's comments. And also threw in [PATCH v2 2/2] this time, reworking defconfigs accordingly. [1] https://lists.denx.de/pipermail/u-boot/2023-November/536981.html > -- > Tom
[PATCH v2 2/2] configs: Remove unneeded SYS_CONFIG_NAME from a*y17lte defconfigs
As correct default SYS_CONFIG_NAME value is now set in board/samsung/axy17lte/Kconfig (in commit "board: samsung: Fix SYS_CONFIG_NAME configs in axy17lte Kconfig"), the SYS_CONFIG_NAME option can be safely removed from all a*y17lte defconfigs. That removal doesn't change resulting .config files. Signed-off-by: Sam Protsenko --- Changes in v2: - None. This patch wasn't present in v1 configs/a3y17lte_defconfig | 1 - configs/a5y17lte_defconfig | 1 - configs/a7y17lte_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig index 42fcd2a3d317..043f3a04db88 100644 --- a/configs/a3y17lte_defconfig +++ b/configs/a3y17lte_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="exynos78x0-common" CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2600 CONFIG_ARCH_EXYNOS=y diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig index 3b80536c12c8..14590f65e9c0 100644 --- a/configs/a5y17lte_defconfig +++ b/configs/a5y17lte_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="exynos78x0-common" CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2600 CONFIG_ARCH_EXYNOS=y diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig index 9390e35057eb..ccb0bf2e8059 100644 --- a/configs/a7y17lte_defconfig +++ b/configs/a7y17lte_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="exynos78x0-common" CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2600 CONFIG_ARCH_EXYNOS=y -- 2.39.2
[PATCH v2 1/2] board: samsung: Fix SYS_CONFIG_NAME configs in axy17lte Kconfig
There is a couple of issues related to SYS_CONFIG_NAME config in
axy17lte Kconfig.
1. The global SYS_CONFIG_NAME in axy17lte Kconfig overrides
SYS_CONFIG_NAME for all boards specified after this line in
arch/arm/mach-exynos/Kconfig:
source "board/samsung/axy17lte/Kconfig"
Right now it's the last 'source' line there, so the issue is not
reproducible. But once some board is moved or added after this line
the next build error will happen:
GEN include/autoconf.mk.dep
In file included from ./include/common.h:16:
include/config.h:3:10: fatal error: configs/exynos78x0-common.h.h:
No such file or directory
3 | #include
| ^~~
compilation terminated.
That's happening because axy17lte Kconfig defines SYS_CONFIG_NAME
option in global namespace (not guarded with any "if TARGET_..."), so
it basically rewrites the correct SYS_CONFIG_NAME defined in the
hypothetical boards which might appear after axy17lte in mach-exynos
Kconfig.
2. Another side of the issue is that SYS_CONFIG_NAME is defined
incorrectly in axy17lte Kconfig:
config SYS_CONFIG_NAME
default "exynos78x0-common.h"
The .h extension should not have been specified there. It's leading
to a build error, as the generated include file has a double '.h'
extension.
3. Each target in axy17lte/Kconfig defines its own SYS_CONFIG_NAME. But
all of those in fact incorrect, as corresponding
include/configs/.h header files don't exist.
4. The global SYS_CONFIG_NAME pretty much repeats the help description
from arch/Kconfig and doc/README.kconfig.
Corresponding defconfig files (a*y17lte_defconfig) fix above issues by
overriding SYS_CONFIG_NAME and correctly setting it to
"exynos78x0-common".
Fix all mentioned issues by removing the incorrect global
SYS_CONFIG_NAME and instead specifying it (correctly) in SYS_CONFIG_NAME
options for each target instead.
Signed-off-by: Sam Protsenko
Fixes: 3e2095e960b4 ("board: samsung: add support for Galaxy A series of 2017
(a5y17lte)")
---
Changes in v2:
- Don't just remove global SYS_CONFIG_NAME, also fix SYS_CONFIG_NAME
for each target in Kconfig
board/samsung/axy17lte/Kconfig | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig
index a018547ff5d4..64a4ffa7e673 100644
--- a/board/samsung/axy17lte/Kconfig
+++ b/board/samsung/axy17lte/Kconfig
@@ -1,11 +1,3 @@
-config SYS_CONFIG_NAME
- string "Board configuration name"
- default "exynos78x0-common.h"
- help
- This option contains information about board configuration name.
- Based on this option include/configs/.h header
- will be used for board configuration.
-
if TARGET_A5Y17LTE
config SYS_BOARD
default "axy17lte"
@@ -16,7 +8,7 @@ config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
- default "a5y17lte"
+ default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@@ -33,7 +25,7 @@ config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
- default "a5y17lte"
+ default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@@ -50,7 +42,7 @@ config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
- default "a3y17lte"
+ default "exynos78x0-common"
config EXYNOS7870
bool "Exynos 7870 SOC support"
--
2.39.2
[PATCH] clk: exynos: Add header guard for clk-pll.h
The clk-pll.h is going to be included in multiple files soon. Add
missing header guard to prevent possible build errors in future.
Signed-off-by: Sam Protsenko
Fixes: 166097e87753 ("clk: exynos: add clock driver for Exynos7420 Soc")
---
drivers/clk/exynos/clk-pll.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
index c79aac44258b..7b7af5e67612 100644
--- a/drivers/clk/exynos/clk-pll.h
+++ b/drivers/clk/exynos/clk-pll.h
@@ -5,4 +5,9 @@
* Thomas Abraham
*/
+#ifndef __EXYNOS_CLK_PLL_H
+#define __EXYNOS_CLK_PLL_H
+
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
+
+#endif /* __EXYNOS_CLK_PLL_H */
--
2.39.2
[PATCH] MAINTAINERS: Fix Sam Protsenko mail
Sam works for Linaro again. Use his work e-mail address for ANDROID AB subsystem. Signed-off-by: Sam Protsenko --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index cde778bc4d3d..d21f66b0b67b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -58,7 +58,7 @@ F:lib/acpi/ ANDROID AB M: Igor Opaniuk -R: Sam Protsenko +R: Sam Protsenko S: Maintained F: cmd/ab_select.c F: common/android_ab.c -- 2.39.2
[PATCH] serial: s5p: Use dev_read_addr_ptr() to get base address
As the address read from device tree is being cast to a pointer, it's
better to use dev_read_addr_ptr() API for getting that address. The more
detailed explanation can be found in commit a12a73b66476 ("drivers: use
dev_read_addr_ptr when cast to pointer").
Signed-off-by: Sam Protsenko
---
drivers/serial/serial_s5p.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index c24d9bca84c9..7d04dcff54fc 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -221,13 +221,11 @@ static int s5p_serial_of_to_plat(struct udevice *dev)
{
struct s5p_serial_plat *plat = dev_get_plat(dev);
const ulong port_type = dev_get_driver_data(dev);
- fdt_addr_t addr;
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
+ plat->reg = dev_read_addr_ptr(dev);
+ if (!plat->reg)
return -EINVAL;
- plat->reg = (struct s5p_uart *)addr;
plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev));
--
2.39.2
[PATCH 4/4] serial: s5p: Improve coding style
Just some minor style fixes. No functional change.
Signed-off-by: Sam Protsenko
---
drivers/serial/serial_s5p.c | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 6d316ccaf31d..c24d9bca84c9 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -50,9 +50,9 @@ enum {
/* Information about a serial port */
struct s5p_serial_plat {
- struct s5p_uart *reg; /* address of registers in physical memory */
- u8 reg_width; /* register width */
- u8 port_id; /* uart port number */
+ struct s5p_uart *reg; /* address of registers in physical memory */
+ u8 reg_width; /* register width */
+ u8 port_id; /* uart port number */
u8 rx_fifo_count_shift;
u8 tx_fifo_count_shift;
u32 rx_fifo_count_mask;
@@ -65,7 +65,7 @@ struct s5p_serial_plat {
* The coefficient, used to calculate the baudrate on S5P UARTs is
* calculated as
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
+ * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
*/
static const int udivslot[] = {
@@ -251,10 +251,10 @@ static int s5p_serial_of_to_plat(struct udevice *dev)
}
static const struct dm_serial_ops s5p_serial_ops = {
- .putc = s5p_serial_putc,
- .pending = s5p_serial_pending,
- .getc = s5p_serial_getc,
- .setbrg = s5p_serial_setbrg,
+ .putc = s5p_serial_putc,
+ .pending= s5p_serial_pending,
+ .getc = s5p_serial_getc,
+ .setbrg = s5p_serial_setbrg,
};
static const struct udevice_id s5p_serial_ids[] = {
@@ -264,13 +264,13 @@ static const struct udevice_id s5p_serial_ids[] = {
};
U_BOOT_DRIVER(serial_s5p) = {
- .name = "serial_s5p",
- .id = UCLASS_SERIAL,
- .of_match = s5p_serial_ids,
- .of_to_plat = s5p_serial_of_to_plat,
+ .name = "serial_s5p",
+ .id = UCLASS_SERIAL,
+ .of_match = s5p_serial_ids,
+ .of_to_plat = s5p_serial_of_to_plat,
.plat_auto = sizeof(struct s5p_serial_plat),
- .probe = s5p_serial_probe,
- .ops= _serial_ops,
+ .probe = s5p_serial_probe,
+ .ops= _serial_ops,
};
#endif
@@ -298,10 +298,12 @@ static inline void _debug_uart_putc(int ch)
struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
#if IS_ENABLED(CONFIG_ARCH_APPLE)
- while (readl(>ufstat) & S5L_TX_FIFO_FULL);
+ while (readl(>ufstat) & S5L_TX_FIFO_FULL)
+ ;
writel(ch, >utxh);
#else
- while (readl(>ufstat) & S5P_TX_FIFO_FULL);
+ while (readl(>ufstat) & S5P_TX_FIFO_FULL)
+ ;
writeb(ch, >utxh);
#endif
}
--
2.39.2
[PATCH 3/4] serial: s5p: Use named constants for register values
Get rid of magic numbers in s5p_serial_init() when writing to UART
registers. While at it, use BIT() macro for existing constants when
appropriate.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/serial/serial_s5p.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index c57bdd059ea6..6d316ccaf31d 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -25,19 +25,28 @@ enum {
PORT_S5L
};
+#define UFCON_FIFO_EN BIT(0)
+#define UFCON_RX_FIFO_RESETBIT(1)
+#define UMCON_RESET_VAL0x0
+#define ULCON_WORD_8_BIT 0x3
+#define UCON_RX_IRQ_OR_POLLING BIT(0)
+#define UCON_TX_IRQ_OR_POLLING BIT(2)
+#define UCON_RX_ERR_IRQ_EN BIT(6)
+#define UCON_TX_IRQ_LEVEL BIT(9)
+
#define S5L_RX_FIFO_COUNT_SHIFT0
#define S5L_RX_FIFO_COUNT_MASK (0xf << S5L_RX_FIFO_COUNT_SHIFT)
-#define S5L_RX_FIFO_FULL (1 << 8)
+#define S5L_RX_FIFO_FULL BIT(8)
#define S5L_TX_FIFO_COUNT_SHIFT4
#define S5L_TX_FIFO_COUNT_MASK (0xf << S5L_TX_FIFO_COUNT_SHIFT)
-#define S5L_TX_FIFO_FULL (1 << 9)
+#define S5L_TX_FIFO_FULL BIT(9)
#define S5P_RX_FIFO_COUNT_SHIFT0
#define S5P_RX_FIFO_COUNT_MASK (0xff << S5P_RX_FIFO_COUNT_SHIFT)
-#define S5P_RX_FIFO_FULL (1 << 8)
+#define S5P_RX_FIFO_FULL BIT(8)
#define S5P_TX_FIFO_COUNT_SHIFT16
#define S5P_TX_FIFO_COUNT_MASK (0xff << S5P_TX_FIFO_COUNT_SHIFT)
-#define S5P_TX_FIFO_FULL (1 << 24)
+#define S5P_TX_FIFO_FULL BIT(24)
/* Information about a serial port */
struct s5p_serial_plat {
@@ -80,13 +89,15 @@ static const int udivslot[] = {
static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
{
- /* enable FIFOs, auto clear Rx FIFO */
- writel(0x3, >ufcon);
- writel(0, >umcon);
- /* 8N1 */
- writel(0x3, >ulcon);
+ /* Enable FIFOs, auto clear Rx FIFO */
+ writel(UFCON_FIFO_EN | UFCON_RX_FIFO_RESET, >ufcon);
+ /* No auto flow control, disable nRTS signal */
+ writel(UMCON_RESET_VAL, >umcon);
+ /* 8N1, no parity bit */
+ writel(ULCON_WORD_8_BIT, >ulcon);
/* No interrupts, no DMA, pure polling */
- writel(0x245, >ucon);
+ writel(UCON_RX_IRQ_OR_POLLING | UCON_TX_IRQ_OR_POLLING |
+ UCON_RX_ERR_IRQ_EN | UCON_TX_IRQ_LEVEL, >ucon);
}
static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width,
--
2.39.2
[PATCH 2/4] serial: s5p: Use livetree API to get "id" property
Use dev_read_u8_default() instead of fdtdec_get_int() to read the "id"
property from device tree, as suggested in [1]. dev_* API is already
used in this driver, so there is no reason to stick to fdtdec_* API.
This also fixes checkpatch warning:
WARNING: Use the livetree API (dev_read_...)
[1] doc/develop/driver-model/livetree.rst
Signed-off-by: Sam Protsenko
---
drivers/serial/serial_s5p.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 177215535676..c57bdd059ea6 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -20,8 +20,6 @@
#include
#include
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
PORT_S5P = 0,
PORT_S5L
@@ -220,8 +218,7 @@ static int s5p_serial_of_to_plat(struct udevice *dev)
plat->reg = (struct s5p_uart *)addr;
plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
- plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "id", dev_seq(dev));
+ plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev));
if (port_type == PORT_S5L) {
plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
--
2.39.2
[PATCH 1/4] serial: s5p: Remove common.h inclusion
It's not really needed here anymore. Remove it, as common.h is going away at some point. Signed-off-by: Sam Protsenko --- drivers/serial/serial_s5p.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index fe52580d64de..177215535676 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -7,7 +7,6 @@ * based on drivers/serial/s3c64xx.c */ -#include #include #include #include -- 2.39.2
[PATCH 0/4] serial: s5p: Cleanups
A small collection of cleanup patches for serial_s5p.c driver. Should induce no functional changes. Sam Protsenko (4): serial: s5p: Remove common.h inclusion serial: s5p: Use livetree API to get "id" property serial: s5p: Use named constants for register values serial: s5p: Improve coding style drivers/serial/serial_s5p.c | 71 + 1 file changed, 40 insertions(+), 31 deletions(-) -- 2.39.2
[PATCH] serial: s5p: Fix clk_get_by_index() error code check
clk_get_by_index() returns negative number on error. Assigning it to
unsigned int makes the subsequent "ret < 0" check always false, leading
in turn to possible unhandled errors. Change 'ret' variable type to
signed int so the code checks and handles clk_get_by_index() return code
properly.
Signed-off-by: Sam Protsenko
Fixes: cf75cdf96ef2 ("serial: s5p: use clock api to get clock rate")
---
drivers/serial/serial_s5p.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 7aeb8c0f8cb7..fe52580d64de 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -118,7 +118,7 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
#if IS_ENABLED(CONFIG_CLK_EXYNOS) || IS_ENABLED(CONFIG_ARCH_APPLE)
struct clk clk;
- u32 ret;
+ int ret;
ret = clk_get_by_index(dev, 1, );
if (ret < 0)
--
2.39.2
[PATCH] exynos: Avoid duplicate reset_cpu with SYSRESET enabled
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the exynos soc code. Fix the build with
SYSRESET enabled by omitting the function from the soc code in that
case. The code still needs to be kept around for use in SPL.
This commit was inspired by commit 6e19dc84c14b ("sunxi: Avoid duplicate
reset_cpu with SYSRESET enabled").
Signed-off-by: Sam Protsenko
---
arch/arm/mach-exynos/soc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 6fe61cf9288d..aff2b5e1b6e8 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -21,12 +21,14 @@ extern void _main(void);
void *secondary_boot_addr = (void *)_main;
#endif /* CONFIG_TARGET_ESPRESSO7420 */
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
#ifdef CONFIG_CPU_V7A
writel(0x1, samsung_get_base_swreset());
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
--
2.39.2
[PATCH] tools: gitignore: Fix tools/generated path
'git status' shows 'tools/generated/' after running the build, which is
wrong. The corresponding .gitignore rule was already added in commit
c623642d29be ("Adjust gitignore for tools/generated/"), but because of
superfluous 'tools/' part it wasn't in effect. Remove incorrect 'tools/'
part to fix it.
While at it, remove tools/ path incorrectly added to the top-level
.gitignore in commit 801c482207c7 (".gitignore: ignore misc include,
simple-bin, and tools/generated build artifacts"), as it's required in
the comment on the top of .gitignore:
# NOTE! Don't add files that are generated in specific
# subdirectories here. Add them in the ".gitignore" file
# in that subdirectory instead.
Signed-off-by: Sam Protsenko
Fixes: c623642d29be ("Adjust gitignore for tools/generated/")
Fixes: 801c482207c7 (".gitignore: ignore misc include, simple-bin, and
tools/generated build artifacts")
---
.gitignore | 1 -
tools/.gitignore | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/.gitignore b/.gitignore
index a1a79e92feef..330148119264 100644
--- a/.gitignore
+++ b/.gitignore
@@ -61,7 +61,6 @@ fit-dtb.blob*
# Generated files
#
/spl/
-/tools/generated/
/tpl/
/defconfig
diff --git a/tools/.gitignore b/tools/.gitignore
index 941d38de212d..0108c567309b 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -34,7 +34,7 @@
/relocate-rela
/spl_size_limit
/sunxi-spl-image-builder
-/tools/generated/**/*.c
+/generated/**/*.c
/update_octeon_header
/version.h
/xway-swap-bytes
--
2.39.2
[PATCH 2/3] arm: exynos: Include missing CPU header in gpio.h
arch/arm/include/asm/arch/gpio.h relies on definitions from cpu.h.
Include it explicitly in gpio.h. Otherwise next build error may occur:
In file included from ./arch/arm/include/asm/gpio.h:7,
from include/cros_ec.h:14,
from board/samsung/common/board.c:8:
./arch/arm/include/asm/arch/gpio.h:1357:4:
error: 'EXYNOS4_GPIO_PART1_BASE' undeclared here
(not in a function); did you mean 'EXYNOS4_GPIO_MAX_PORT'?
1357 | { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
|^~~
Signed-off-by: Sam Protsenko
---
arch/arm/mach-exynos/include/mach/gpio.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
b/arch/arm/mach-exynos/include/mach/gpio.h
index f9975d7919f2..9eeeb7699963 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -8,6 +8,9 @@
#define __ASM_ARCH_GPIO_H
#ifndef __ASSEMBLY__
+
+#include
+
struct s5p_gpio_bank {
unsigned intcon;
unsigned intdat;
--
2.39.2
[PATCH 1/3] arm: exynos: Include missing CPU header in soc.c
samsung_get_base_swreset() is called in soc.c, but corresponding header with its prototype is not included. Fix this to avoid possible build errors. Signed-off-by: Sam Protsenko --- arch/arm/mach-exynos/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index a07c87a2c8e2..6fe61cf9288d 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -9,6 +9,7 @@ #include #include #include +#include #ifdef CONFIG_TARGET_ESPRESSO7420 /* -- 2.39.2
[PATCH 3/3] watchdog: s5p_wdt: Include missing CPU header
s5p watchdog driver calls samsung_get_base_watchdog() function, but its prototype is not included. That might lead to build warnings like this: drivers/watchdog/s5p_wdt.c: In function 'wdt_stop': drivers/watchdog/s5p_wdt.c:16:26: warning: implicit declaration of function 'samsung_get_base_watchdog' [-Wimplicit-function-declaration] 16 | (struct s5p_watchdog *)samsung_get_base_watchdog(); | ^ Include asm/arch/cpu.h to fix that issue. Signed-off-by: Sam Protsenko --- drivers/watchdog/s5p_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/s5p_wdt.c b/drivers/watchdog/s5p_wdt.c index 5ad7d2609f04..80524a00101b 100644 --- a/drivers/watchdog/s5p_wdt.c +++ b/drivers/watchdog/s5p_wdt.c @@ -6,6 +6,7 @@ #include #include +#include #include #define PRESCALER_VAL 255 -- 2.39.2
[PATCH 0/3] exynos: Include missing CPU headers
During porting a new Exynos-based board to U-Boot I faced a couple of similar build errors due to missing inclusion. This series make sure it's fixed in all places I found. Sam Protsenko (3): arm: exynos: Include missing CPU header in soc.c arm: exynos: Include missing CPU header in gpio.h watchdog: s5p_wdt: Include missing CPU header arch/arm/mach-exynos/include/mach/gpio.h | 3 +++ arch/arm/mach-exynos/soc.c | 1 + drivers/watchdog/s5p_wdt.c | 1 + 3 files changed, 5 insertions(+) -- 2.39.2
[PATCH] board: samsung: Remove incorrect SYS_CONFIG_NAME in axy17lte Kconfig
The global SYS_CONFIG_NAME in axy17lte Kconfig overrides SYS_CONFIG_NAME
for all boards specified after this line in
arch/arm/mach-exynos/Kconfig:
source "board/samsung/axy17lte/Kconfig"
Right now it's the last 'source' line there, so the issue is not
reproducible. But once some board is moved or added after this line the
next build error will happen:
GEN include/autoconf.mk.dep
In file included from ./include/common.h:16:
include/config.h:3:10: fatal error: configs/exynos78x0-common.h.h:
No such file or directory
3 | #include
| ^~~
compilation terminated.
That's happening because axy17lte Kconfig defines SYS_CONFIG_NAME option
in global namespace (not guarded with any "if TARGET_..."), so it
basically rewrites the correct SYS_CONFIG_NAME defined in the
hypothetical boards which might appear after axy17lte in mach-exynos
Kconfig.
Another side of the issue is that SYS_CONFIG_NAME is defined
incorrectly in axy17lte Kconfig:
config SYS_CONFIG_NAME
default "exynos78x0-common.h"
The .h extension should not have been specified there. It's leading to
the build error, as the generated include file has double '.h' extension.
Fix the issue by simply removing the SYS_CONFIG_NAME definition in
axy17lte Kconfig, as all related defconfigs already declare internal
values for SYS_CONFIG_NAME:
- a5y17lte_defconfig
- a7y17lte_defconfig
- a3y17lte_defconfig
Signed-off-by: Sam Protsenko
Fixes: 3e2095e960b4 ("board: samsung: add support for Galaxy A series of 2017
(a5y17lte)")
---
board/samsung/axy17lte/Kconfig | 8
1 file changed, 8 deletions(-)
diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig
index a018547ff5d4..209394a8a5a8 100644
--- a/board/samsung/axy17lte/Kconfig
+++ b/board/samsung/axy17lte/Kconfig
@@ -1,11 +1,3 @@
-config SYS_CONFIG_NAME
- string "Board configuration name"
- default "exynos78x0-common.h"
- help
- This option contains information about board configuration name.
- Based on this option include/configs/.h header
- will be used for board configuration.
-
if TARGET_A5Y17LTE
config SYS_BOARD
default "axy17lte"
--
2.39.2
Re: [PATCH v2] fastboot: getvar: fix partition-size return value
Hi Gary,
On Thu, 27 Aug 2020 at 11:51, Gary Bisson
wrote:
>
> The size returned by 'getvar partition-size' should be in bytes, not in
> blocks as fastboot uses that value to generate empty partition when
> running format [1].
>
> Note that the function was already returning the proper size in bytes
> for NAND devices (see struct part_info details).
>
> [1]
> https://android.googlesource.com/platform/system/core/+/refs/heads/android10-release/fastboot/fastboot.cpp#1500
>
> Signed-off-by: Gary Bisson
> ---
Thank you for the patch, all look good! As I understand from the
changelog, v2 fixes sunxi build error found by Lukasz? Other than
that:
Reviewed-by: Sam Protsenko
> Changelog v1->v2:
> - removed change for FASTBOOT_FLASH_NAND as not necessary (and therefore
> not building)
> ---
> drivers/fastboot/fb_getvar.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
> index 52da34b1e37..d43f2cfee66 100644
> --- a/drivers/fastboot/fb_getvar.c
> +++ b/drivers/fastboot/fb_getvar.c
> @@ -95,7 +95,7 @@ static const struct {
> *
> * @param[in] part_name Info for which partition name to look for
> * @param[in,out] response Pointer to fastboot response buffer
> - * @param[out] size If not NULL, will contain partition size (in blocks)
> + * @param[out] size If not NULL, will contain partition size
> * @return Partition number or negative value on error
> */
> static int getvar_get_part_info(const char *part_name, char *response,
> @@ -109,7 +109,7 @@ static int getvar_get_part_info(const char *part_name,
> char *response,
> r = fastboot_mmc_get_part_info(part_name, _desc, _info,
>response);
> if (r >= 0 && size)
> - *size = part_info.size;
> + *size = part_info.size * part_info.blksz;
> # elif CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
> struct part_info *part_info;
>
> --
> 2.28.0
>
[PATCH] configs: am335x_evm: Enable Fastboot
This config option was present in am335x_boneblack_defconfig, but we
have to use generic am335x_evm_defconfig now, as BBB defconfig was
removed in commit 8fa7f65dd02c ("configs: Remove
am335x_boneblack_defconfig"). So this patch merely brings that option
back.
Tested on BeagleBone Black:
=> fastboot 0
$ fastboot flash rootfs rootfs.img
Fixes: 8fa7f65dd02c ("configs: Remove am335x_boneblack_defconfig")
Signed-off-by: Sam Protsenko
---
configs/am335x_evm_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index b5579f6686..2fe9f86f1a 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -44,6 +44,9 @@ CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
--
2.24.1
[PATCH] configs: am335x_evm: Enable DFU over TFTP support
DFU over TFTP flashing method might be helpful in order to speed-up the
flashing process of big images (as DFU works over USB EP0, which is
quite slow). Also, it's a good backup option in the case when USB got
broken (either in software or hardware), to avoid resorting to SD card
boot.
This config option was present in am335x_boneblack_defconfig, but we
have to use generic am335x_evm_defconfig now, as BBB defconfig was
removed in commit 8fa7f65dd02c ("configs: Remove
am335x_boneblack_defconfig"). So this patch merely brings that option
back.
Tested on BeagleBone Black:
=> setenv dfu_alt_info $dfu_alt_info_emmc
=> setenv ipaddr 192.168.0.100
=> setenv serverip 192.168.0.1
=> setenv updatefile update_uboot.itb
=> dfu tftp mmc 1
Where 'update_uboot.its' file looks like this:
/dts-v1/;
/ {
description = "Automatic U-Boot update";
#address-cells = <1>;
images {
u-boot.img.raw-1 {
description = "U-Boot binary";
data = /incbin/("u-boot.img");
compression = "none";
type = "firmware";
load = <0x6>;
hash-1 {
algo = "sha1";
};
};
};
};
And 'update_uboot.itb' is generated as follows:
$ mkimage -f update_uboot.its update_uboot.itb
Newly flashed U-Boot works fine.
Fixes: 8fa7f65dd02c ("configs: Remove am335x_boneblack_defconfig")
Signed-off-by: Sam Protsenko
---
configs/am335x_evm_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 8fd90a6f37..2fe9f86f1a 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK=y
CONFIG_CLK_CDCE9XX=y
+CONFIG_DFU_TFTP=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
--
2.24.1
