On 16/12/2021 15:57, Sean Anderson wrote:
On 12/16/21 8:17 AM, Tero Kristo wrote:
On 15/12/2021 18:47, Sean Anderson wrote:
This adds an entry in MAINTAINERS for the cdce9xx driver, since it
was not
added when the driver was submitted. This will help future submitters
figure out who to CC
ted by them.
-Tero
(no changes since v1)
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6db5354322..44f4b846e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -658,6 +658,12 @@ M: Simon Glass
S:Maintained
F:tools/buildman/
+CDCE9XX
On 15/12/2021 18:47, Sean Anderson wrote:
This xlate function just performs some checking. We can do this in
request() instead and use the default xlate.
Signed-off-by: Sean Anderson
Looks good to me now.
Reviewed-by: Tero Kristo
---
Changes in v2:
- Fix build error caused by mismatched
On 01/12/2021 22:10, Sean Anderson wrote:
On 12/1/21 3:08 PM, Tom Rini wrote:
On Wed, Dec 01, 2021 at 02:44:02PM -0500, Sean Anderson wrote:
This xlate function just performs some checking. We can do this in
request() instead and use the default xlate.
Signed-off-by: Sean Anderson
Hi
On 13/06/2021 19:49, Tom Rini wrote:
On Fri, Jun 11, 2021 at 09:40:14PM +0530, Lokesh Vutla wrote:
Hi Tom,
Please find the PR for master branch targeted for v2021.10-next branch
with checkpatch warnings fixed. Details about the PR are updated in the tag
message.
Gitlab CI report:
On 11/06/2021 14:08, Lokesh Vutla wrote:
Hi Tero,
On 11/06/21 2:15 pm, Tero Kristo wrote:
Hello,
One more post, this time with the #ifdef hackery converted to use the
IS_ENABLED / CONFIG_IS_ENABLED macros, and also removed the "common.h"
include from k3-clk.h header. This ve
From: Tero Kristo
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
configs
From: Tero Kristo
Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
board/ti/j721e/README | 9 ++---
1 file changed, 6
caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.
Signed-off-by: Tero Kristo
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
2 files changed, 2 insertions(+), 2
From: Dave Gerlach
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
configs
From: Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/Makefile | 2
configuration.
Signed-off-by: Dave Gerlach
Reported-by: Keerthy
Tested-by: Keerthy
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/j721e_init.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 76a04a9035
From: Tero Kristo
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch
From: Dave Gerlach
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 7 ---
1 file changed, 4 insertions
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 2 ++
1 file
From: Tero Kristo
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 84 +
arch/arm/mach-k3
From: Tero Kristo
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register
From: Tero Kristo
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/config.mk | 4
From: Tero Kristo
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Kconfig | 12 ++
drivers
From: Tero Kristo
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
Reviewed-by: Jaehoon Chung
From: Tero Kristo
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
From: Tero Kristo
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.
Signed-off-by: Tero
From: Tero Kristo
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post
From: Tero Kristo
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-sci.c | 6 --
1 file changed, 4 insertions(+), 2
From: Tero Kristo
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.
Acked-by: Lukasz Majewski
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/
From: Tero Kristo
Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:
dev_get_uclass_priv: null device
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 2 ++
1 file changed, 2
From: Tero Kristo
Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.
Reviewed-by: Peng Fan
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers
From: Tero Kristo
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.
Signed-off-by: Tero Kristo
Signed-off
From: Lokesh Vutla
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
Signed-off-by: Tero Kristo
From: Tero Kristo
With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device
From: Tero Kristo
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support
From: Tero Kristo
Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.
This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect r
Hello,
One more post, this time with the #ifdef hackery converted to use the
IS_ENABLED / CONFIG_IS_ENABLED macros, and also removed the "common.h"
include from k3-clk.h header. This version also contains fixes to any
build issues reported by Lokesh, and these are squashed in to relevant
patches.
On 10/06/2021 18:33, Lokesh Vutla wrote:
+Tero,
On 10/06/21 8:55 pm, Tom Rini wrote:
On Thu, Jun 10, 2021 at 12:16:50PM +0530, Lokesh Vutla wrote:
Hi Tom,
Please find the PR for master branch targeted for v2021.10-next branch.
Details about the PR are updated in the tag message.
**p_image,
+ size_t *p_size)
{
if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
if (socfpga_vendor_authentication(p_image, p_size))
--
-Tero
On 03/06/2021 09:32, Tero Kristo wrote:
From: Lokesh Vutla
board_fit_image_post_process() passes
On 08/06/2021 09:32, Lokesh Vutla wrote:
On 08/06/21 11:57 am, Tero Kristo wrote:
On 07/06/2021 14:22, Lokesh Vutla wrote:
On 03/06/21 12:02 pm, Tero Kristo wrote:
Hi,
As requested, this is just a rebase to the latest u-boot tip.
Boot tested on j721e to make sure nothing got broken
On 07/06/2021 14:22, Lokesh Vutla wrote:
On 03/06/21 12:02 pm, Tero Kristo wrote:
Hi,
As requested, this is just a rebase to the latest u-boot tip.
Boot tested on j721e to make sure nothing got broken.
There are some build errors. Can you take a look?
https://source.denx.de/u-boot
From: Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/Makefile | 2
From: Tero Kristo
Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
board/ti/j721e/README | 9 ++---
1 file changed, 6
caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.
Signed-off-by: Tero Kristo
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
2 files changed, 2 insertions(+), 2
From: Dave Gerlach
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
configs
configuration.
Signed-off-by: Dave Gerlach
Reported-by: Keerthy
Tested-by: Keerthy
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/j721e_init.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 76a04a9035
From: Tero Kristo
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
configs
From: Tero Kristo
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 2 ++
1 file
From: Dave Gerlach
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 7 ---
1 file changed, 4 insertions
From: Tero Kristo
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 80 +
arch/arm/mach-k3
From: Tero Kristo
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/config.mk | 4
From: Tero Kristo
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register
From: Tero Kristo
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Kconfig | 12 ++
drivers
From: Tero Kristo
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
Reviewed-by: Jaehoon Chung
From: Tero Kristo
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
From: Tero Kristo
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.
Signed-off-by: Tero
From: Tero Kristo
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post
From: Tero Kristo
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-sci.c | 6 --
1 file changed, 4 insertions(+), 2
From: Tero Kristo
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.
Acked-by: Lukasz Majewski
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/
From: Tero Kristo
Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:
dev_get_uclass_priv: null device
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 2 ++
1 file changed, 2
From: Tero Kristo
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.
Signed-off-by: Tero Kristo
Signed-off
From: Tero Kristo
Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.
Reviewed-by: Peng Fan
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers
From: Lokesh Vutla
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
Signed-off-by: Tero Kristo
From: Tero Kristo
With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device
From: Tero Kristo
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support
From: Tero Kristo
Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.
This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect r
Hi,
As requested, this is just a rebase to the latest u-boot tip.
Boot tested on j721e to make sure nothing got broken.
-Tero
.
Signed-off-by: Tero Kristo
---
v2: convert to proper Kconfig and add defaults for TI platforms
net/Kconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/net/Kconfig b/net/Kconfig
index c4b4dae064..ba0ca813ce 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -74,6 +74,17 @@ config
might get confused by that.
Just keep it in mind for future improvements.
For the whole series (did a quick test run with the latest v4 HSM rearch
series also):
Reviewed-by: Tero Kristo
Tested-by: Tero Kristo
Dave Gerlach (14):
dt-bindings: memory-controller: Add K3 AM64 DDRSS compatible
On 11/05/2021 15:07, Tom Rini wrote:
On Tue, May 11, 2021 at 10:40:15AM +0300, Tero Kristo wrote:
This fits the TFTP progress bar on single line based on the size of the
file being downloaded, reducing unnecessary spam and also making it
easier to track the download progress.
Signed-off
From: Dave Gerlach
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
configs
caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.
Signed-off-by: Tero Kristo
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
2 files changed, 2 insertions(+), 2
From: Tero Kristo
Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
board/ti/j721e/README | 9 ++---
1 file changed, 6
configuration.
Signed-off-by: Dave Gerlach
Reported-by: Keerthy
Tested-by: Keerthy
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/j721e_init.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 1a4f796e5e
From: Tero Kristo
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch
From: Tero Kristo
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
configs
From: Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/Makefile | 2
From: Dave Gerlach
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 7 ---
1 file changed, 4 insertions
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 2 ++
1 file
From: Tero Kristo
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/config.mk | 4
From: Tero Kristo
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 80 +
arch/arm/mach-k3
From: Tero Kristo
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Kconfig | 12 ++
drivers
From: Tero Kristo
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register
From: Tero Kristo
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/power/domain/Kconfig
From: Tero Kristo
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
From: Tero Kristo
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.
Signed-off-by: Tero
From: Tero Kristo
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-sci.c | 6 --
1 file changed, 4 insertions(+), 2
From: Tero Kristo
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post
From: Tero Kristo
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.
Acked-by: Lukasz Majewski
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/
From: Tero Kristo
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.
Signed-off-by: Tero Kristo
Signed-off
From: Tero Kristo
Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:
dev_get_uclass_priv: null device
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 2 ++
1 file changed, 2
From: Lokesh Vutla
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
Signed-off-by: Tero Kristo
From: Tero Kristo
Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.
Reviewed-by: Peng Fan
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers
From: Tero Kristo
With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device
From: Tero Kristo
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support
Hello,
Couple of small changes in v4:
- re-worked patch #14 to include review comments from Jaehoon Chung
* changed code to use iopoll version instead of hand crafted loops
for timeout handling
* other mostly cosmetic changes
- patch #19/#21 changed to allow RM init to happen based on
From: Tero Kristo
Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.
This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect r
This fits the TFTP progress bar on single line based on the size of the
file being downloaded, reducing unnecessary spam and also making it
easier to track the download progress.
Signed-off-by: Tero Kristo
---
include/configs/ti_armv7_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 09/05/2021 08:54, Vignesh Raghavendra wrote:
On 5/5/21 11:25 PM, Tero Kristo wrote:
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two
On 07/05/2021 03:03, Jaehoon Chung wrote:
Hi Tero,
On 5/6/21 2:55 AM, Tero Kristo wrote:
From: Tero Kristo
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting
Uhm,
Sorry for CC:ing a stale email address with the patches, t-kri...@ti.com
is no longer functional. Please drop that from any of the replies if you
don't fancy spam replies from server.
-Tero
On 05/05/2021 20:55, Tero Kristo wrote:
Hello,
Resurrecting this series; v2 [1] was sort
caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.
Signed-off-by: Tero Kristo
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +-
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +-
2 files changed, 2 insertions(+), 2
From: Tero Kristo
Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
board/ti/j721e/README | 9 ++---
1 file changed, 6
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