Re: [U-Boot] [PATCH] spi: cadence_qspi: Add quad write support
On 26/02/19 1:59 PM, Ley Foon Tan wrote:
> Use quad write if SPI_TX_QUAD flag is set.
>
How was the patch tested? Could you add that info to commit msg?
> Signed-off-by: Ley Foon Tan
> ---
> drivers/spi/cadence_qspi.c | 2 +-
> drivers/spi/cadence_qspi.h | 2 +-
> drivers/spi/cadence_qspi_apb.c | 7 ++-
> 3 files changed, 8 insertions(+), 3 deletions(-)
> mode change 100644 => 100755 drivers/spi/cadence_qspi.c
> mode change 100644 => 100755 drivers/spi/cadence_qspi.h
> mode change 100644 => 100755 drivers/spi/cadence_qspi_apb.c
>
Why are the permissions being changed? Please keep it as is
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> old mode 100644
> new mode 100755
> index 11fce9c4fe..efdb178450
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -256,7 +256,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned
> int bitlen,
> break;
> case CQSPI_INDIRECT_WRITE:
> err = cadence_qspi_apb_indirect_write_setup
> - (plat, priv->cmd_len, cmd_buf);
> + (plat, priv->cmd_len, dm_plat->mode, cmd_buf);
> if (!err) {
> err = cadence_qspi_apb_indirect_write_execute
> (plat, data_bytes, dout);
> diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
> old mode 100644
> new mode 100755
> index 055900def0..b491407130
> --- a/drivers/spi/cadence_qspi.h
> +++ b/drivers/spi/cadence_qspi.h
> @@ -60,7 +60,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
> cadence_spi_platdata *plat,
> int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
> unsigned int rxlen, u8 *rxbuf);
> int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
> - unsigned int cmdlen, const u8 *cmdbuf);
> + unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
> int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata
> *plat,
> unsigned int txlen, const u8 *txbuf);
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> old mode 100644
> new mode 100755
> index a8af352030..55a7501913
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -77,6 +77,7 @@
>
> #define CQSPI_REG_WR_INSTR 0x08
> #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
> +#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB16
>
> #define CQSPI_REG_DELAY 0x0C
> #define CQSPI_REG_DELAY_TSLCH_LSB 0
> @@ -686,7 +687,7 @@ failrd:
>
> /* Opcode + Address (3/4 bytes) */
> int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
> - unsigned int cmdlen, const u8 *cmdbuf)
> + unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf)
> {
> unsigned int reg;
> unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
> @@ -702,6 +703,10 @@ int cadence_qspi_apb_indirect_write_setup(struct
> cadence_spi_platdata *plat,
>
> /* Configure the opcode */
> reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
> +
> + if (tx_width & SPI_TX_QUAD)
> + reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
> +
> writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
>
> /* Setup write address. */
>
--
Regards
Vignesh
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Re: [U-Boot] [PATCH] usb: udc-uclass: Fixed problem when no alias is defined in DT
Hi Lukasz,
On 24/01/19 8:14 PM, Jean-Jacques Hiblot wrote:
> commit 801f1fa442 "dm: usb: udc: Use SEQ_ALIAS to index the USB gadget
> ports" changed the way the udevice if found. It uses the alias to find
> a udevice for a given USB port number. In the commit log it was stated
> that if no alias is provided, the bind order will be used instead. However
> it doesn't work. Fixing this by adding a call to uclass_get_device() if
> uclass_get_device_by_seq() fails.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
This fixes DFU gadget failing to find USB device on DRA7xx/AM57xx
platforms. Since, this patch fixes a regression, could this be picked up
for next -rc?
Tested-by: Vignesh R
> drivers/usb/gadget/udc/udc-uclass.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/gadget/udc/udc-uclass.c
> b/drivers/usb/gadget/udc/udc-uclass.c
> index 8d7864797a..3053ccf7d9 100644
> --- a/drivers/usb/gadget/udc/udc-uclass.c
> +++ b/drivers/usb/gadget/udc/udc-uclass.c
> @@ -23,8 +23,11 @@ int usb_gadget_initialize(int index)
> return 0;
> ret = uclass_get_device_by_seq(UCLASS_USB_GADGET_GENERIC, index, );
> if (!dev || ret) {
> - pr_err("No USB device found\n");
> - return -ENODEV;
> + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, index, );
> + if (!dev || ret) {
> + pr_err("No USB device found\n");
> + return -ENODEV;
> + }
> }
> dev_array[index] = dev;
> return 0;
>
--
Regards
Vignesh
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[U-Boot] [PATCH] am57xx_evm_defconfig: Enable configs to support QSPI boot
AM57xx IDK EVMs can boot out of QSPI. Enable configs to support QSPI boot. Also enable configs for updating QSPI boot images over DFU. Tested on AM572x IDK EVM. Signed-off-by: Vignesh R --- configs/am57xx_evm_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 748682036e17..3f73f259751c 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -40,9 +40,13 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_DWC_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x8200 CONFIG_FASTBOOT_BUF_SIZE=0x2F00 -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] configs: am57xx_evm: define CONFIG_SPL_LOAD_FIT_ADDRESS for SPL-DFU
Hi Bin, On 08/02/19 10:31 PM, Bin Liu wrote: > Define CONFIG_SPL_LOAD_FIT_ADDRESS to enable SPL-DFU for am57x platform. > > Signed-off-by: Bin Liu > --- With this patch DFU args are no longer available at U-Boot prompt > include/configs/am57xx_evm.h | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h > index d61fdf9f7a36..70aa4250605b 100644 > --- a/include/configs/am57xx_evm.h > +++ b/include/configs/am57xx_evm.h > @@ -35,11 +35,22 @@ > > #define CONFIG_SYS_OMAP_ABE_SYSCK > > +#ifdef CONFIG_SPL_DFU This should be CONFIG_IS_ENABLED(DFU) so that DFUARGS defined when CONFIG_DFU=y in U-Boot. > +#ifndef CONFIG_SPL_BUILD > #define DFUARGS \ > "dfu_bufsiz=0x1\0" \ > DFU_ALT_INFO_MMC \ > DFU_ALT_INFO_EMMC \ > DFU_ALT_INFO_RAM \ > + DFU_ALT_INFO_QSPI > +#else > +#undef CONFIG_CMD_BOOTD > +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x8020 > +#define DFUARGS \ > + "dfu_bufsiz=0x1\0" \ > + DFU_ALT_INFO_RAM > +#endif > +#endif > > #include > > -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 00/25] MTD defconfigs/Kconfigs/Makefiles heavy cleanup
Hi Jagan, On 09/12/18 11:37 PM, Miquel Raynal wrote: > Hello, > > During my last project about SPI-NAND support in U-Boot, I discovered > when modifying Makefiles a confusing organization where: > * Sub-directories/files are compiled from the root Makefile > * Commands are at the root of everything > > I sent a fist series a few weeks ago to move Makefile entries in their > respective directories (which needed to be reworked). Since then, I > have been working on clarifying all this for the MTD subsystem and > here are the main points of such re-organization: > * Rename CONFIG_MTD into CONFIG_DM_MTD to reserve CONFIG_MTD to what > is called today CONFIG_MTD_DEVICE. > * Fix build dependencies in defconfigs, like: "UBI and NAND depend on MTD". > * Fix the Kconfig files to reflect these dependencies (as defconfigs > have been updated, nothing should break). > * Simplify the Makefiles: compiling the drivers/mtd/nand/raw/ > sub-directory should just depend on MTD being compiled and the NAND > core as well, there is absolutely no logic to make it depend on > CMD_NAND. > > New green Travis CI build for the third version of this series: > https://travis-ci.org/miquelraynal/u-boot/builds/463486099 > There are three Sandbox tests that are failing, they have not been > break by this series. The following Travis test has been done on the > commit on which has been based the series and shows the same errors: > https://travis-ci.org/miquelraynal/u-boot/builds/463593006 > I would like to revive this series. With some rebasing, this series should still apply as is. Jagan, did you get a chance to look into this series? Any comments? > Thanks, > Miquèl > > Note: as the number of Cc:'ed people reached 184 with > get_maintainers.pl I decided to trim the list to: > * People interested by the MTD subsystem. > * A few maintainers: I had to tweak some defconfigs after more digging > than with other boards (k2g, bcm11130, M54418TWR). Maintainers of > these platforms are Cc:'ed. > > Changes since v3: > = > * As suggested by Vignesh, SPI_FLASH_MTD depends on MTD. Enforce this > in Kconfig with a new patch. There is no defconfig to fix, all > defconfigs with SPI_FLASH_MTD already use MTD. > * s/coherent Makefile/appropriate Makefile/ in commit title of patch 1. > * s/Kconfig/Makefile in commit message of "mtd: nand: remove > dependency on commands in Kconfig" and "mtd: ubi: remove dependency > on command in Kconfig". > * Add Boris R-b tags. > * Correct typos pointed by Boris. > * Remove the if/endif in cmd/Kconfig about mtdparts, let the "depends > on" that was already present. > * Use an if/endif block to compile legacy-mtd-utils.c (to avoid > failures when both 'sf' and 'nand' commands are compiled-in). > * Merge all Makefile changes in one consistent commit as suggested by > Boris. > > Changes since v2: > = > * Cleanup also applied to the SPL in an additional patch. > * NOR dependency on MTD extracted from the patch adding MTD > dependencies on commands only to do it in a separate change. > * Typo s/copile/compile/ in "rename CONFIG_MTD_DEVICE..." commit log. > * No more MTD depencency on SPI_FLASH, only kept on SPI_FLASH_MTD. > * Same applies to the sf command. > * Avoid compiling the NAND core while it is not needed (not speaking > about the raw NAND core, really what is in drivers/mtd/nand:). > * Last patch dropping CONFIG_MTD_PARTITIONS forgotten. We need them in > order to reduce the final binary size. > * Additional fixes in cmd/Kconfig. > > Changes since v1: > = > * Squashed both patches from the first series and included them in > "mtd: simplify Makefiles". > * Added all other patches. > * Renamed CONFIG_NAND into CONFIG_MTD_RAW_NAND as suggested. > > > Miquel Raynal (25): > mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND > mtd: rename CONFIG_MTD -> CONFIG_DM_MTD > mtd: rename CONFIG_MTD_DEVICE -> CONFIG_MTD > mtd: ensure MTD is compiled when there is a NOR flash > mtd: ensure MTD/the raw NAND core are compiled when there is a NAND > flash > mtd: ensure MTD is compiled when there is a SPI NOR flash using MTD > mtd: ensure UBI is compiled when using fastmap > mtd: ensure MTD is compiled when UBI is used > mtd: ensure UBI is compiled when CMD_UBI is selected > mtd: ensure UBI is compiled when ENV_IS_IN_UBI is selected > mtd: ensure MTD_RAW_NAND is compiled when ENV_IS_IN_NAND is selected > mtd: ensure MTD and NOR drivers are compiled with ENV_IS_IN_FLASH > mtd: ensure CMD_NAND is compiled when its options are selected > mtd: ensure MTD is compiled when CMD_MTDPARTS is selected > configs: move CONFIG_MTD in defconfigs when set in arch includes > configs: remove raw NAND core from k2g defconfigs > configs: remove MTD support from bcm11130 and M54418TWR defconfigs > mtd: nand: add includes in NAND core to avoid warnings > dfu: add dependency on the raw NAND core > mtd: nor: NOR flashes
Re: [U-Boot] [PATCH] treewide: Replace CONFIG_DM_SPI_FLASH with CONFIG_IS_ENABLED(DM_SPI_FLASH)
On 19/02/19 10:37 AM, Marek Vasut wrote:
> Perform the replacement to allow platforms use non-DM SPI flash access
> in SPL/TPL. This is thus far needed on platforms with size constraints.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Vignesh R
> ---
I have a similar patch, but you beat me to it :)
Reviewed-by: Vignesh R
Regards
Vignesh
> cmd/sf.c | 4 ++--
> drivers/mtd/spi/sf_probe.c | 2 +-
> drivers/net/fm/fm.c| 4 ++--
> env/sf.c | 2 +-
> include/spi_flash.h| 2 +-
> 5 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/cmd/sf.c b/cmd/sf.c
> index 738ef0e46d..7e92a43b2c 100644
> --- a/cmd/sf.c
> +++ b/cmd/sf.c
> @@ -84,7 +84,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
> unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
> unsigned int mode = CONFIG_SF_DEFAULT_MODE;
> char *endp;
> -#ifdef CONFIG_DM_SPI_FLASH
> +#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
> struct udevice *new, *bus_dev;
> int ret;
> /* In DM mode defaults will be taken from DT */
> @@ -119,7 +119,7 @@ static int do_spi_flash_probe(int argc, char * const
> argv[])
> return -1;
> }
>
> -#ifdef CONFIG_DM_SPI_FLASH
> +#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
> /* Remove the old device, otherwise probe will just be a nop */
> ret = spi_find_bus_and_cs(bus, cs, _dev, );
> if (!ret) {
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index 7f1378f494..4282d48f26 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -53,7 +53,7 @@ err_read_id:
> return ret;
> }
>
> -#ifndef CONFIG_DM_SPI_FLASH
> +#if !CONFIG_IS_ENABLED(DM_SPI_FLASH)
> struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
> unsigned int max_hz, unsigned int spi_mode)
> {
> diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
> index e19ddc..6a5c9bbc9d 100644
> --- a/drivers/net/fm/fm.c
> +++ b/drivers/net/fm/fm.c
> @@ -377,7 +377,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
> addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
> int ret = 0;
>
> -#ifdef CONFIG_DM_SPI_FLASH
> +#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
> struct udevice *new;
>
> /* speed and mode will be read from DT */
> @@ -464,7 +464,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
> void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
> int ret = 0;
>
> -#ifdef CONFIG_DM_SPI_FLASH
> +#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
> struct udevice *new;
>
> /* speed and mode will be read from DT */
> diff --git a/env/sf.c b/env/sf.c
> index b3dec82c35..ee639b90fc 100644
> --- a/env/sf.c
> +++ b/env/sf.c
> @@ -52,7 +52,7 @@ static struct spi_flash *env_flash;
>
> static int setup_flash_device(void)
> {
> -#ifdef CONFIG_DM_SPI_FLASH
> +#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
> struct udevice *new;
> int ret;
>
> diff --git a/include/spi_flash.h b/include/spi_flash.h
> index 7f691e8559..09f3896fb9 100644
> --- a/include/spi_flash.h
> +++ b/include/spi_flash.h
> @@ -51,7 +51,7 @@ struct dm_spi_flash_ops {
> /* Access the serial operations for a device */
> #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
>
> -#ifdef CONFIG_DM_SPI_FLASH
> +#if CONFIG_IS_ENABLED(DM_SPI_FLASH)
> /**
> * spi_flash_read_dm() - Read data from SPI flash
> *
>
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Re: [U-Boot] [PATCH v2 1/1] mtd: added missing GigaDevice chips
Hi,
On 18/02/19 3:30 PM, Jiri Kastner wrote:
> Vocore2 (mt7688 based device) has g25q128 chip
> from GigaDevice, which i've found in kernel tree.
> added chips are gd25q128 and gd25q256.
>
> Cc: Jagan Teki
> Cc: Vignesh R
> ---
> drivers/mtd/spi/spi-nor-ids.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 3215e2431d..c1f84df64f 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -106,6 +106,16 @@ const struct flash_info spi_nor_ids[] = {
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> },
> + {
> + INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> + },
> + {
> + INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> + },
Have you tested Quad mode on this device? I see gd25q256 uses
macronix_quad_enable() and kernel handles this by .quad_enable()
callback which isnt supported in U-Boot yet. Could you explain how Quad
mode would work in U-Boot with this flash?
--
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Vignesh
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Re: [U-Boot] [PATCH] sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters array
On 14/02/19 10:39 PM, Jagan Teki wrote:
> + Vignesh
>
> On Mon, Jan 7, 2019 at 11:05 AM Ye Li wrote:
>>
>> On i.MX7ULP EVK board, we use MX25R6435F NOR flash, add its parameters
>> and IDs to flash parameter array. Otherwise, the flash probe will fails.
>>
>> Signed-off-by: Ye Li
>> ---
>> drivers/mtd/spi/spi_flash_ids.c | 1 +
This file no longer exists after recent SPI NOR migration. Could you
rebase on the latest? The capabilities flags are now same as kernel.
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mtd/spi/spi_flash_ids.c
>> b/drivers/mtd/spi/spi_flash_ids.c
>> index ad0a0c8..17f9893 100644
>> --- a/drivers/mtd/spi/spi_flash_ids.c
>> +++ b/drivers/mtd/spi/spi_flash_ids.c
>> @@ -94,6 +94,7 @@ const struct spi_flash_info spi_flash_ids[] = {
>> {"mx25u25635f",INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL |
>> WR_QPP) },
>> {"mx66u51235f",INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL |
>> WR_QPP) },
>> {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL |
>> WR_QPP) },
>> + {"mx25r6435f", INFO(0xc22817, 0x0, 64 * 1024, 128, RD_FULL |
>> SECT_4K) },
>
> Look like this would also support WR_QPP, how about updating the same?
>
--
Regards
Vignesh
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Re: [U-Boot] [PATCH v4 14/20] mtd: spi: Switch to new SPI NOR framework
On 13/02/19 1:54 AM, Adam Ford wrote: > On Tue, Feb 12, 2019 at 1:20 PM Adam Ford wrote: >> >> On Sun, Feb 10, 2019 at 10:37 PM Vignesh R wrote: >>> >>> >>> >>> On 11/02/19 9:01 AM, Adam Ford wrote: >>>> On Tue, Feb 5, 2019 at 12:00 AM Vignesh R wrote: >>>>> >>>>> Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD >>>>> layer. Fix up sf_dataflash to work in legacy way. And update sandbox to >>>>> use new interfaces/definitions >>>>> >>>>> Signed-off-by: Vignesh R >>>>> Tested-by: Simon Goldschmidt >>>>> Tested-by: Stefan Roese >>>>> Tested-by: Horatiu Vultur >>>>> Reviewed-by: Jagan Teki >>>>> Tested-by: Jagan Teki #zynq-microzed >>>> >>>> This patch appears to break the da850_evm board which boots from SPI >>>> Flash and initializes the davinci driver with platdata since the >>>> device tree stuff does not quite work right in SPL. >>> >>> Oops, I did test on K2G EVM that has davinci SPI controller with micron >>> n25q flash but that was with DT. Not sure whats missing with platdata. >>> >>>> >>>> U-Boot SPL 2019.01-02923-gc4e8862308-dirty (Feb 10 2019 - 21:24:38 -0600) >>>> Trying to boot from SPI >>>> SPI probe failed. >>>> SPL: failed to boot from all boot devices >>>> ### ERROR ### Please RESET the board ### >>> >>> Could you enable debug prints at spi-mem level in drivers/spi/spi-mem.c >>> (especially debug prints at the end of spi_mem_exec_op()) and post the >>> logs here? >>> >>>> >>>> Any suggestions on how to fix the SPI initialization without needing >>>> the device tree? I have tried to port the device tree stuff to SPL, >>>> but I haven't yet been successful so I have had to leave the platdata >>>> initialization in place. >>>> >>> >>> I haven't changed any driver names so, platdata to driver bindings >>> should still be the same. Could you verify if spi_nor_scan() is being >>> called in drivers/mtd/spi/spi-nor-tiny.c for SPL? >> >> I globally turned on DEBUG and I have two logs for you: >> >> Not working: >> >> U-Boot SPL 2019.01-02923-gc4e8862308-dirty (Feb 12 2019 - 13:04:19 -0600) >> Trying to boot from SPI >> uclass_find_device_by_seq: 0 -1 >> uclass_find_device_by_seq: 0 0 >>- -1 -1 'davinci_spi' >>- not found >> spi_get_bus_and_cs: Binding new device 'spi_flash', busnum=0, cs=0, >> driver=spi_flash_std >> spi_get_bus_and_cs: Error path, created=1, device 'spi_flash' >> SPI probe failed. >> SPL: failed to boot from all boot devices >> ### ERROR ### Please RESET the board ### >> >> As a point of reference , I thought I'd show >> WORKING version (before this patch): >> >> U-Boot SPL 2019.01-02922-g2ee6705be0-dirty (Feb 12 2019 - 12:59:49 -0600) >> Trying to boot from SPI >> uclass_find_device_by_seq: 0 -1 >> uclass_find_device_by_seq: 0 0 >>- -1 -1 'davinci_spi' >>- not found >> spi_get_bus_and_cs: Binding new device 'spi_flash', busnum=0, cs=0, >> driver=spi_flash_std >> uclass_find_device_by_seq: 0 -1 >> uclass_find_device_by_seq: 0 0 >>- -1 -1 'spi_flash' >>- not found >> spi_flash_std_probe: slave=8001fd60, cs=0 >> davinci_spi_set_speed speed 3000 >> davinci_spi_set_mode mode 3 >> davinci_spi_set_speed speed 3000 >> davinci_spi_set_mode mode 3 >> spi_get_bus_and_cs: bus=8001fbf4, slave=8001fd60 >> SPL: payload image: U-Boot 2019.01-02922-g2ee6705be0 load addr: >> 0xc107ffc0 size: 405306 >> Jumping to U-Boot >> loaded - jumping to U-Boot... >> image entry point: 0xc108 >> ... >> >> During this process, I learned a few things. >> 1. I am not really using the device tree during SPL like i originally >> thought and the OF_PLATDATA >> 2. Getting SPL to support device tree with or without PLATDATA isn't >> as straightforward as I hoped >> 3. With the knowledge I learned from item 1, I tried to disabled >> OF_CONTROL during SPL, but this patch also fails to build since it >> assumes OF_CONTROL is always enabled. >> >> If there are any suggestions you might have, I am willing to try them. >> > > I beleive I have narrowed it down a bit to a chunk of code (int > device_probe(struct udevice *dev)) located
Re: [U-Boot] [PATCH v1 1/2] configs: k2g_evm: Enable CONFIG_BLK
On 08/02/19 3:25 PM, Jean-Jacques Hiblot wrote: > CONFIG_BLK can be safely enabled as DM_MMC and DM_USB are already enabled. > > Signed-off-by: Jean-Jacques Hiblot > --- > Thanks for the patch! Tested-by: Vignesh R Tom, This fix is required for booting kernel from MMC/SD on K2G boards. Could you please consider the patch for next -rc? > configs/k2g_evm_defconfig | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig > index c518b707a5..838b6f14b6 100644 > --- a/configs/k2g_evm_defconfig > +++ b/configs/k2g_evm_defconfig > @@ -34,7 +34,6 @@ CONFIG_DTB_RESELECT=y > CONFIG_MULTI_DTB_FIT=y > CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > CONFIG_DM=y > -# CONFIG_BLK is not set > CONFIG_DFU_MMC=y > CONFIG_SYS_I2C_DAVINCI=y > CONFIG_MISC=y > -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] spi: Kconfig: Mark CONFIG_SPI as Legacy spi support
On 09/02/19 5:45 PM, Jagan Teki wrote: > CONFIG_SPI is mandatory for SPI support even if the given board > has dm or non-dm versions, so mark CONFIG_SPI as non-dm config > option and move the respective non-dm drivers below to that. > > This eventually reduce the explicit CONFIG_SPI enablement for > dm version spi drivers. > > Cc: Vignesh R > Signed-off-by: Jagan Teki Acked-by: Vignesh R > --- > drivers/spi/Kconfig | 17 - > 1 file changed, 12 insertions(+), 5 deletions(-) > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 2fb4862c4a..bed279cbc4 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -1,7 +1,4 @@ > -menuconfig SPI > - bool "SPI Support" > - > -if SPI > +menu "SPI Support" > > config DM_SPI > bool "Enable Driver Model for SPI drivers" > @@ -294,6 +291,14 @@ config ZYNQMP_GQSPI > > endif # if DM_SPI > > +config SPI > + bool "Legacy SPI support" > + help > + Enable the legacy SPI support. This will include legacy SPI > + interface code for non-dm SPI drivers. > + > +if SPI > + > config SOFT_SPI > bool "Soft SPI driver" > help > @@ -387,4 +392,6 @@ config OMAP3_SPI > (McSPI). This driver be used to access SPI chips on platforms > embedding this OMAP3 McSPI IP core. > > -endif # menu "SPI Support" > +endif # if SPI > + > +endmenu # menu "SPI Support" > -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] mtd: spi: Kconfig: Update CONFIG_SPI_FLASH
Hi, On 09/02/19 5:45 PM, Jagan Teki wrote: > 1) CONFIG_SPI_FLASH is not just a legacy code, but it has common >core code which handle both dm and non-dm spi flash code. So >fix the info text to make it clear globally. > > 2) Since it's flash core it shouldn't depends on legacy SPI, >so remove the 'depends on SPI' > > Cc: Vignesh R > Signed-off-by: Jagan Teki > --- > drivers/mtd/spi/Kconfig | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig > index e3b40fc157..605f60c713 100644 > --- a/drivers/mtd/spi/Kconfig > +++ b/drivers/mtd/spi/Kconfig > @@ -26,11 +26,10 @@ config SPI_FLASH_SANDBOX > stored in a file on the host filesystem. > > config SPI_FLASH > - bool "Legacy SPI Flash Interface support" > - depends on SPI > + bool "SPI Flash Core Interface support" Nit, since we have SPI NAND flash as well, should description be updated to say SPI NOR Flash instead of SPI Flash? > select SPI_MEM > help > - Enable the legacy SPI flash support. This will include basic > + Enable the SPI flash Core support. This will include basic > standard support for things like probing, read / write, and > erasing through cmd_sf interface. > > -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mtd: spi: Kconfig: Select SPI_FLASH if DM_SPI_FLASH
On 09/02/19 5:45 PM, Jagan Teki wrote: > DM_SPI_FLASH should require spi flash interface code for dm > version, so select SPI_FLASH core by default if any board > enabled DM_SPI_FLASH. > > This overcome the explicit enablement of CONFIG_SPI_FLASH on > respective boards when DM_SPI_FLASH being used. > > Cc: Vignesh R > Signed-off-by: Jagan Teki > --- > drivers/mtd/spi/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig > index 605f60c713..43f597ec29 100644 > --- a/drivers/mtd/spi/Kconfig > +++ b/drivers/mtd/spi/Kconfig > @@ -3,6 +3,7 @@ menu "SPI Flash Support" > config DM_SPI_FLASH > bool "Enable Driver Model for SPI flash" > depends on DM && DM_SPI > + select SPI_FLASH How about imply instead of select since there is no compile time dependency? > help > Enable driver model for SPI flash. This SPI flash interface > (spi_flash_probe(), spi_flash_write(), etc.) is then > -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] spi: ti_qspi: Drop non DM code
Now that all boards using TI QSPI have moved to DM and DT, drop non DM
code completely.
Signed-off-by: Vignesh R
---
drivers/spi/Kconfig| 12 +-
drivers/spi/Makefile | 2 +-
drivers/spi/ti_qspi.c | 231 ++---
include/configs/am43xx_evm.h | 2 -
include/configs/am57xx_evm.h | 2 -
include/configs/cl-som-am57x.h | 1 -
include/configs/cm_t43.h | 1 -
include/configs/dra7xx_evm.h | 2 -
scripts/config_whitelist.txt | 2 -
9 files changed, 45 insertions(+), 210 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ac7fbab84199..92cd02be4150 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -258,6 +258,12 @@ config TEGRA210_QSPI
be used to access SPI chips on platforms embedding this
NVIDIA Tegra210 IP core.
+config TI_QSPI
+ bool "TI QSPI driver"
+ help
+ Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
+ This driver support spi flash single, quad and memory reads.
+
config XILINX_SPI
bool "Xilinx SPI driver"
help
@@ -345,12 +351,6 @@ config SH_QSPI
Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs.
-config TI_QSPI
- bool "TI QSPI driver"
- help
- Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
- This driver support spi flash single, quad and memory reads.
-
config KIRKWOOD_SPI
bool "Marvell Kirkwood SPI Driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 39026712931b..cf3be7bc2ce2 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -9,6 +9,7 @@ obj-y += spi-uclass.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
+obj-$(CONFIG_TI_QSPI) += ti_qspi.o
else
obj-y += spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
@@ -56,7 +57,6 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
-obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 2dcce66de048..731fb23022d2 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -52,9 +52,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define MM_SWITCH 0x01
#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xf8ff
-#define MMAP_START_ADDR_DRA0x5c00
-#define MMAP_START_ADDR_AM43x 0x3000
-#define CORE_CTRL_IO0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
#define QSPI_CMD_READ_DUAL (0x6b << 0)
@@ -98,13 +95,9 @@ struct ti_qspi_regs {
/* ti qspi priv */
struct ti_qspi_priv {
-#ifndef CONFIG_DM_SPI
- struct spi_slave slave;
-#else
void *memory_map;
uint max_hz;
u32 num_cs;
-#endif
struct ti_qspi_regs *base;
void *ctrl_mod_mmap;
ulong fclk;
@@ -113,8 +106,9 @@ struct ti_qspi_priv {
u32 dc;
};
-static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
+static int ti_qspi_set_speed(struct udevice *bus, uint hz)
{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
uint clk_div;
if (!hz)
@@ -133,6 +127,8 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv,
uint hz)
>base->clk_ctrl);
/* enable SCLK and program the clk divider */
writel(QSPI_CLK_EN | clk_div, >base->clk_ctrl);
+
+ return 0;
}
static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
@@ -142,38 +138,6 @@ static void ti_qspi_cs_deactivate(struct ti_qspi_priv
*priv)
readl(>base->cmd);
}
-static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
-{
- priv->dc = 0;
- if (mode & SPI_CPHA)
- priv->dc |= QSPI_CKPHA(0);
- if (mode & SPI_CPOL)
- priv->dc |= QSPI_CKPOL(0);
- if (mode & SPI_CS_HIGH)
- priv->dc |= QSPI_CSPOL(0);
-
- return 0;
-}
-
-static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
-{
- writel(priv->dc, >base->dc);
- writel(0, >base->cmd);
- writel(0, >base->data);
-
- priv->dc <<= cs * 8;
- writel(priv->dc, >base->dc);
-
- return 0;
-}
-
-static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
-{
- writel(0, >base->dc);
- writel(0, >base->cmd);
- writel(0, >base->data);
-}
-
static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
u32
[U-Boot] [PATCH 2/2] spi: ti_qspi: Convert to spi-mem ops
Convert driver to use spi-mem ops in order to support accelerated MMIO
flash interface in generic way and for better performance.
Signed-off-by: Vignesh R
---
drivers/spi/ti_qspi.c | 132 ++
1 file changed, 68 insertions(+), 64 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 731fb23022d2..77fa17ee8ab1 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -40,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_INVAL (4 << 16)
#define QSPI_RD_QUAD(7 << 16)
/* device control */
-#define QSPI_DD(m, n) (m << (3 + n*8))
#define QSPI_CKPHA(n) (1 << (2 + n*8))
#define QSPI_CSPOL(n) (1 << (1 + n*8))
#define QSPI_CKPOL(n) (1 << (n*8))
@@ -53,18 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xf8ff
-#define QSPI_CMD_READ (0x3 << 0)
-#define QSPI_CMD_READ_DUAL (0x6b << 0)
-#define QSPI_CMD_READ_QUAD (0x6c << 0)
-#define QSPI_CMD_READ_FAST (0x0b << 0)
-#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
-#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
-#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
-#define QSPI_CMD_WRITE (0x12 << 16)
-#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
+#define QSPI_SETUP0_ADDR_SHIFT (8)
+#define QSPI_SETUP0_DBITS_SHIFT(10)
/* ti qspi register set */
struct ti_qspi_regs {
@@ -96,6 +89,7 @@ struct ti_qspi_regs {
/* ti qspi priv */
struct ti_qspi_priv {
void *memory_map;
+ size_t mmap_size;
uint max_hz;
u32 num_cs;
struct ti_qspi_regs *base;
@@ -171,19 +165,6 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int
bitlen,
return -EINVAL;
}
- /* Setup mmap flags */
- if (flags & SPI_XFER_MMAP) {
- writel(MM_SWITCH, >base->memswitch);
- if (priv->ctrl_mod_mmap)
- ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
- return 0;
- } else if (flags & SPI_XFER_MMAP_END) {
- writel(~MM_SWITCH, >base->memswitch);
- if (priv->ctrl_mod_mmap)
- ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
- return 0;
- }
-
if (bitlen == 0)
return -1;
@@ -269,9 +250,9 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int
bitlen,
}
/* TODO: control from sf layer to here through dm-spi */
-#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
-void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
{
+#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
unsigned intaddr = (unsigned int) (data);
unsigned intedma_slot_num = 1;
@@ -286,44 +267,34 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t
len)
/* disable edma3 clocks */
disable_edma3_clocks();
+#else
+ memcpy_fromio(data, offset, len);
+#endif
*((unsigned int *)offset) += len;
}
-#endif
-static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
- struct spi_slave *slave,
- bool enable)
+static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
+ u8 data_nbits, u8 addr_width,
+ u8 dummy_bytes)
{
- u32 memval;
- u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
+ u32 memval = opcode;
- if (!enable) {
- writel(0, >base->setup0);
- return;
- }
-
- memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
-
- switch (mode) {
- case SPI_RX_QUAD:
- memval |= QSPI_CMD_READ_QUAD;
- memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ switch (data_nbits) {
+ case 4:
memval |= QSPI_SETUP0_READ_QUAD;
- slave->mode |= SPI_RX_QUAD;
break;
- case SPI_RX_DUAL:
- memval |= QSPI_CMD_READ_DUAL;
- memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ case 2:
memval |= QSPI_SETUP0_READ_DUAL;
break;
def
[U-Boot] [PATCH 0/2] ti_qspi: Move to spi-mem framework
Now that SPI NOR Supports MMIO SPI controllers via spi-mem framework, move TI QSPI to SPI MEM framework for better performance and avoid repeating SPI NOR generic code in the driver. While at that get rid of non DM code, as all boards are expected to support DM and DT by now. Note: This *breaks cl-som-am57x_defconfig*, as defconfig does not enable even basic CONFIG_DM and would surely be dropped in next merge window. Tested on AM43xx, dra7xx EVMs Vignesh R (2): spi: ti_qspi: Drop non DM code spi: ti_qspi: Convert to spi-mem ops drivers/spi/Kconfig| 12 +- drivers/spi/Makefile | 2 +- drivers/spi/ti_qspi.c | 351 ++--- include/configs/am43xx_evm.h | 2 - include/configs/am57xx_evm.h | 2 - include/configs/cl-som-am57x.h | 1 - include/configs/cm_t43.h | 1 - include/configs/dra7xx_evm.h | 2 - scripts/config_whitelist.txt | 2 - 9 files changed, 107 insertions(+), 268 deletions(-) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] cl-som-am57x_defconfig will be dropped
Hi Uri, I see following warnings when building configs/cl-som-am57x_defconfig[1] which means board has not be moved to U-Boot Driver Model and Device Tree. Do you have plans to move configs/cl-som-am57x_defconfig to DM and enable CONFIG_DM and other DM framework? This is coming in the way of dropping all non DM code from drivers and this config will be dropped in 2019.04. [1]: = WARNING == This board does not use CONFIG_DM_MMC. Please update the board to use CONFIG_DM_MMC before the v2019.04 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mtd: add spi flash id s25fl064l
On 08/02/19 3:33 PM, Heiko Schocher wrote:
> Add support for SPANSION s25fl064l
>
> Signed-off-by: Heiko Schocher
> ---
>
> Changes in v2:
> - s/s25f064l/s25fl064l
> as Vignesh R suggested
>
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 3215e2431d..ef18a0568e 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -187,6 +187,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
> { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K |
> SPI_NOR_DUAL_READ) },
> + { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> #endif
> #ifdef CONFIG_SPI_FLASH_SST /* SST */
>
Acked-by: Vignesh R
--
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Vignesh
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Re: [U-Boot] [PATCH] mtd: qspi: support read the flag status in fspi driver
Hi, On 09/02/19 10:59 PM, Jagan Teki wrote: > On Mon, Jan 7, 2019 at 2:24 PM Ye Li wrote: >> >> From: Han Xu >> >> Support to read the flag status in driver to avoid the spi-nor framework >> wait_for_ready hang issue. >> >> Signed-off-by: Han Xu >> --- >> drivers/spi/fsl_qspi.c | 47 +++ >> 1 file changed, 47 insertions(+) >> >> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c >> index 1987a72..ed0e649 100644 >> --- a/drivers/spi/fsl_qspi.c >> +++ b/drivers/spi/fsl_qspi.c >> @@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; >> #endif >> #define SEQID_WRAR 13 >> #define SEQID_RDAR 14 >> +#define SEQID_RDFSR15 >> >> /* QSPI CMD */ >> #define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */ >> @@ -57,6 +58,7 @@ DECLARE_GLOBAL_DATA_PTR; >> #define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */ >> #define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */ >> #define QSPI_CMD_RDID 0x9f/* Read JEDEC ID */ >> +#define QSPI_CMD_FLAG_SR 0x70/* Read FLAG STATUS*/ > > NAK, need to handle this from flash side. better keep working on that front. > U-Boot now supports spi-mem abstraction just like kernel. Could you move fsl_qspi to use spi-mem APIs to get rid of using opcodes directly within the driver? -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 14/20] mtd: spi: Switch to new SPI NOR framework
On 11/02/19 9:01 AM, Adam Ford wrote: > On Tue, Feb 5, 2019 at 12:00 AM Vignesh R wrote: >> >> Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD >> layer. Fix up sf_dataflash to work in legacy way. And update sandbox to >> use new interfaces/definitions >> >> Signed-off-by: Vignesh R >> Tested-by: Simon Goldschmidt >> Tested-by: Stefan Roese >> Tested-by: Horatiu Vultur >> Reviewed-by: Jagan Teki >> Tested-by: Jagan Teki #zynq-microzed > > This patch appears to break the da850_evm board which boots from SPI > Flash and initializes the davinci driver with platdata since the > device tree stuff does not quite work right in SPL. Oops, I did test on K2G EVM that has davinci SPI controller with micron n25q flash but that was with DT. Not sure whats missing with platdata. > > U-Boot SPL 2019.01-02923-gc4e8862308-dirty (Feb 10 2019 - 21:24:38 -0600) > Trying to boot from SPI > SPI probe failed. > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ### Could you enable debug prints at spi-mem level in drivers/spi/spi-mem.c (especially debug prints at the end of spi_mem_exec_op()) and post the logs here? > > Any suggestions on how to fix the SPI initialization without needing > the device tree? I have tried to port the device tree stuff to SPL, > but I haven't yet been successful so I have had to leave the platdata > initialization in place. > I haven't changed any driver names so, platdata to driver bindings should still be the same. Could you verify if spi_nor_scan() is being called in drivers/mtd/spi/spi-nor-tiny.c for SPL? Sorry for the trouble. Regards Vignesh -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 00/20] SF: Migrate to Linux SPI NOR framework
On 07/02/19 6:13 PM, Jagan Teki wrote: > On Tue, Feb 5, 2019 at 11:29 AM Vignesh R wrote: [...] >> >> Vignesh R (20): >> configs: Move CONFIG_SPI_FLASH into defconfigs >> bitops: Fix GENMASK definition for Sandbox >> spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes >> spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size >> spi: spi-mem: Claim SPI bus before spi mem access >> spi: Add non DM version of SPI_MEM >> sh: bitops: add hweight*() macros >> mtd: spi: Port SPI NOR framework from Linux >> mtd: spi: spi-nor-core: Add SPI MEM support >> mtd: spi: spi-nor-core: Add 4 Byte addressing support >> mtd: spi: spi-nor-core: Add SFDP support >> mtd: spi: spi-nor-core: Add back U-Boot specific features >> mtd: spi: sf_probe: Add "jedec,spi-nor" compatible string >> mtd: spi: Switch to new SPI NOR framework >> mtd: spi: Remove unused files >> mtd: spi: Add lightweight SPI flash stack for SPL >> spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL >> configs: Remove SF_DUAL_FLASH >> configs: Don't use SPI_FLASH_BAR as default >> MAINTAINERS: Add an entry for SPI NOR > > Update trivial change on this patch. > > Applied to u-boot-spi/master, thanks for the big changes and welcome aboard! > Thanks Jagan! Thanks all for testing out this series -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd: add spi flash id s25f064l
Hi,
On 08/02/19 1:34 PM, Heiko Schocher wrote:
> Add support for SPANSION s25f064l
>
s/s25f064l/s25fl064l
as per: https://www.cypress.com/file/316661/download
> Signed-off-by: Heiko Schocher
> ---
>
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 3215e2431d..662c009764 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -187,6 +187,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
> { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K |
> SPI_NOR_DUAL_READ) },
> + { INFO("s25f064l", 0x016017, 0, 64 * 1024, 128, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
Here too.
> { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> #endif
> #ifdef CONFIG_SPI_FLASH_SST /* SST */
>
--
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Vignesh
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Re: [U-Boot] [PATCH v4 00/20] SF: Migrate to Linux SPI NOR framework
On 06-Feb-19 1:43 PM, Simon Goldschmidt wrote: > On Tue, Feb 5, 2019 at 6:58 AM Vignesh R wrote: >> >> Here is the v4 of SPI NOR migration(github branch at [1]) with minor >> cleanups > > I've just sanity-checked this again on socfpga_socrates: Everything > still works and SPL is ~1.8 KiB smaller than without this patch. > Thanks again for testing! Jagan, This is based on top of latest u-boot/master. Could this series be queued now? Thanks! Regards Vignesh >> >> Travis ci report: >> https://travis-ci.org/r-vignesh/u-boot/builds/488868207 >> >> Change log: >> Since v3: >> Rebase on to the latest u-boot/master >> Drop MODULE_LICENSE, EXPORT_SYMBOL_GPL macros >> Make SPI_FLASH_BAR default for ZYNQ_QSPI as suggested by Jagan. >> >> Since v2: >> Split sync up patches into smaller versions so that its easier for review. >> Address comments by Jagan and Simon Goldschmidt on v2. >> Make SPI_FLASH_TINY(read only SF stack) as default for SPL build to >> offset against size increase due to new code. >> >> Since v1: >> Remove #ifindef __UBOOT__ >> Add back BAR support, but dont enable as default for all platform (see >> 10/11 for more details) >> Enable SPI_FLASH_TINY on boards where there is SPL size constraint as >> seen on travis ci builds. >> Drop sf_mtd changes for now as it seems to cause issues. >> v1: https://patchwork.ozlabs.org/cover/1012146/ >> >> Since RFC v2: >> Fix issues reported by Simon Goldschmidt wrt 4 use of byte addressing opcode >> Fix issues in compiling SFDP code >> Re organize file names and Makefile to simply spi-nor-tiny inclusion >> Remove SPI_FLASH_BAR and SF_DUAL_FLASH as these are no longer used >> RFC v2: https://patchwork.ozlabs.org/cover/1007589/ >> >> Since RFC v1: >> Add lightweight SPI flash stack for boards with SPL size constraints >> Provide non DM version of spi-mem >> Fix build issues on different platforms as reported by travis-ci on v1 >> >> RFC v1: https://patchwork.ozlabs.org/cover/1004689/ >> >> Background: >> >> U-Boot SPI NOR support (sf layer) is quite outdated as it does not >> support 4 byte addressing opcodes, SFDP table parsing and different types of >> quad mode enable sequences. Many newer flashes no longer support BANK >> registers used by sf layer to a access >16MB space. >> Also, many SPI controllers have special MMIO interfaces which provide >> accelerated read/write access but require knowledge of flash parameters >> to make use of it. Recent spi-mem layer provides a way to support such >> flashes but sf layer isn't using that. >> This patch series syncs SPI NOR framework from Linux v4.19. It also adds >> spi-mem support on top. >> So, we gain 4byte addressing support and SFDP support. This makes >> migrating to U-Boot MTD framework easier. >> >> Tested with few Spansion, micron and macronix flashes with TI's dra7xx, >> k2g, am43xx EVMs. I dont have access to flashes from other vendors. So, >> I would greatly appreciate testing on other platforms. Complete series >> with dependencies here[1] >> >> [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v4 >> >> Vignesh R (20): >> configs: Move CONFIG_SPI_FLASH into defconfigs >> bitops: Fix GENMASK definition for Sandbox >> spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes >> spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size >> spi: spi-mem: Claim SPI bus before spi mem access >> spi: Add non DM version of SPI_MEM >> sh: bitops: add hweight*() macros >> mtd: spi: Port SPI NOR framework from Linux >> mtd: spi: spi-nor-core: Add SPI MEM support >> mtd: spi: spi-nor-core: Add 4 Byte addressing support >> mtd: spi: spi-nor-core: Add SFDP support >> mtd: spi: spi-nor-core: Add back U-Boot specific features >> mtd: spi: sf_probe: Add "jedec,spi-nor" compatible string >> mtd: spi: Switch to new SPI NOR framework >> mtd: spi: Remove unused files >> mtd: spi: Add lightweight SPI flash stack for SPL >> spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL >> configs: Remove SF_DUAL_FLASH >> configs: Don't use SPI_FLASH_BAR as default >> MAINTAINERS: Add an entry for SPI NOR >> >> MAINTAINERS |9 + >> arch/arm/mach-omap2/am33xx/Kconfig|1 - >> arch/sh/include/asm/bitops.h |4 + >> common/spl/Kconfig| 23 +- >> configs/alt_defconfig
[U-Boot] [PATCH v4 7/7] configs: am65x_evm_a53: Enable DMA related configs
From: Grygorii Strashko Enable TI K3 AM65x PSI-L, Ring Accelerator and UDMA drivers Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh R Reviewed-by: Tom Rini --- configs/am65x_evm_a53_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 8f6fd25531b4..c058b75e0079 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -48,10 +48,11 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y -CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_K3_ARASAN=y @@ -67,5 +68,6 @@ CONFIG_REMOTEPROC_K3=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 5/7] soc: keystone: Merge into ti specific directory
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
arch/arm/mach-keystone/Kconfig | 8
drivers/soc/Makefile | 1 -
drivers/soc/keystone/Makefile | 3 ---
drivers/soc/ti/Kconfig | 6 ++
drivers/soc/ti/Makefile| 5 ++---
drivers/soc/{keystone => ti}/keystone_serdes.c | 0
include/configs/ti_armv7_keystone2.h | 3 ---
scripts/config_whitelist.txt | 1 -
8 files changed, 16 insertions(+), 11 deletions(-)
delete mode 100644 drivers/soc/keystone/Makefile
rename drivers/soc/{keystone => ti}/keystone_serdes.c (100%)
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index d24596eccb0d..e06eba5aea1f 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -9,18 +9,24 @@ config TARGET_K2HK_EVM
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
config TARGET_K2G_EVM
bool "TI Keystone 2 Galileo EVM"
@@ -29,6 +35,8 @@ config TARGET_K2G_EVM
select TI_I2C_BOARD_DETECT
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
endchoice
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 8b7ead546e1c..ce253b7aa886 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,5 +2,4 @@
#
# Makefile for the U-Boot SOC specific device drivers.
-obj-$(CONFIG_ARCH_KEYSTONE)+= keystone/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/keystone/Makefile b/drivers/soc/keystone/Makefile
deleted file mode 100644
index dfebb143e09b..
--- a/drivers/soc/keystone/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig
index 8c0f3c07b23f..e4f88344487e 100644
--- a/drivers/soc/ti/Kconfig
+++ b/drivers/soc/ti/Kconfig
@@ -16,5 +16,11 @@ config TI_K3_NAVSS_RINGACC
and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs
If unsure, say N.
+config TI_KEYSTONE_SERDES
+ bool "Keystone SerDes driver for ethernet"
+ depends on ARCH_KEYSTONE
+ help
+SerDes driver for Keystone SoC used for ethernet support on TI
+K2 platforms.
endif # SOC_TI
diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
index 63e21aaad40f..4ec04ee1257e 100644
--- a/drivers/soc/ti/Makefile
+++ b/drivers/soc/ti/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
-#
-# TI K3 SOC drivers
-#
+
obj-$(CONFIG_TI_K3_NAVSS_RINGACC) += k3-navss-ringacc.o
+obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/ti/keystone_serdes.c
similarity index 100%
rename from drivers/soc/keystone/keystone_serdes.c
rename to drivers/soc/ti/keystone_serdes.c
diff --git a/include/configs/ti_armv7_keystone2.h
b/include/configs/ti_armv7_keystone2.h
index 0c7d66486832..6d8536a815f8 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -134,9 +134,6 @@
#define CONFIG_KSNET_SERDES_SGMII2_BASEKS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMIIKS2_LANES_PER_SGMII_SERDES
-/* SerDes */
-#define CONFIG_TI_KEYSTONE_SERDES
-
#define CONFIG_AEMIF_CNTRL_BASEKS2_AEMIF_CNTRL_BASE
/* I2C Configuration */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b425cc360fe1..294d5238b414 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4419,7 +4419,6 @@ CONFIG_THOR_RESET_OFF
CONFIG_THUNDERX
CONFIG_TIMESTAMP
CONFIG_TIZEN
-CONFIG_TI_KEYSTONE_SERDES
CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
--
2.20.1
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[U-Boot] [PATCH v4 6/7] arm64: dts: ti: k3-am65: add mcu navss nodes
From: Grygorii Strashko
Add DT node for MCU NAVSS its components to get DMA working on AM654
SoC.
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 47
1 file changed, 47 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 143eb6d63092..c5d23d0203ab 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include
+#include
/ {
chosen {
@@ -63,6 +64,52 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x>;
};
+
+ navss_mcu: navss-mcu {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ti,sci-dev-id = <119>;
+
+ mcu_ringacc: ringacc@2b80 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>;
+ reg-names = "rt", "fifos",
+ "proxy_gcfg", "proxy_target";
+ ti,num-rings = <286>;
+ ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
+ ti,dma-ring-reset-quirk;
+ ti,sci = <>;
+ ti,sci-dev-id = <195>;
+ };
+
+ mcu_udmap: udmap@285c {
+ compatible = "ti,k3-navss-udmap";
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x2aa0 0x0 0x4>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ #dma-cells = <3>;
+
+ ti,ringacc = <_ringacc>;
+ ti,psil-base = <0x6000>;
+
+ ti,sci = <>;
+ ti,sci-dev-id = <194>;
+
+ ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
+ <0x2>; /* TX_CHAN */
+ ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
+ <0x4>; /* RX_CHAN */
+ ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
+ dma-coherent;
+ };
+ };
};
_wakeup {
--
2.20.1
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[U-Boot] [PATCH v4 4/7] dma: ti: add driver to K3 UDMA
The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet mode) - MEM_TO_DEV (Packet mode) Signed-off-by: Peter Ujfalusi Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh R --- drivers/dma/Kconfig |2 + drivers/dma/Makefile |2 + drivers/dma/ti/Kconfig| 14 + drivers/dma/ti/Makefile |3 + drivers/dma/ti/k3-udma-hwdef.h| 184 +++ drivers/dma/ti/k3-udma.c | 1730 + include/dt-bindings/dma/k3-udma.h | 31 + include/linux/soc/ti/ti-udma.h| 24 + 8 files changed, 1990 insertions(+) create mode 100644 drivers/dma/ti/Kconfig create mode 100644 drivers/dma/ti/Makefile create mode 100644 drivers/dma/ti/k3-udma-hwdef.h create mode 100644 drivers/dma/ti/k3-udma.c create mode 100644 include/dt-bindings/dma/k3-udma.h create mode 100644 include/linux/soc/ti/ti-udma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1820676d7a18..4f37ba7d35eb 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -57,4 +57,6 @@ config APBH_DMA_BURST8 endif +source "drivers/dma/ti/Kconfig" + endmenu # menu "DMA Support" diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index b5f9147e0a54..afab324461b9 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o + +obj-y += ti/ diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig new file mode 100644 index ..3d5498326c42 --- /dev/null +++ b/drivers/dma/ti/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ + +if ARCH_K3 + +config TI_K3_NAVSS_UDMA +bool "Texas Instruments UDMA" +depends on ARCH_K3 +select DMA +select TI_K3_NAVSS_RINGACC +select TI_K3_NAVSS_PSILCFG +default n +help + Support for UDMA used in K3 devices. +endif diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile new file mode 100644 index ..de2f9ac91a46 --- /dev/null +++ b/drivers/dma/ti/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_TI_K3_NAVSS_UDMA) += k3-udma.o diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h new file mode 100644 index ..c88399a815ea --- /dev/null +++ b/drivers/dma/ti/k3-udma-hwdef.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef K3_NAVSS_UDMA_HWDEF_H_ +#define K3_NAVSS_UDMA_HWDEF_H_ + +#define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000 + +/* Global registers */ +#define UDMA_REV_REG 0x0 +#define UDMA_PERF_CTL_REG 0x4 +#define UDMA_EMU_CTL_REG 0x8 +#define UDMA_PSIL_TO_REG 0x10 +#define UDMA_UTC_CTL_REG 0x1c +#define UDMA_CAP_REG(i)(0x20 + (i * 4)) +#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 +#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 + +/* RX Flow regs */ +#define UDMA_RFLOW_RFA_REG 0x0 +#define UDMA_RFLOW_RFB_REG 0x4 +#define UDMA_RFLOW_RFC_REG 0x8 +#define UDMA_RFLOW_RFD_REG 0xc +#define UDMA_RFLOW_RFE_REG 0x10 +#define UDMA_RFLOW_RFF_REG 0x14 +#define UDMA_RFLOW_RFG_REG 0x18 +#define UDMA_RFLOW_RFH_REG 0x1c + +#define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG) + +/* TX chan regs */ +#define UDMA_TCHAN_TCFG_REG0x0 +#define UDMA_TCHAN_TCREDIT_REG 0x4 +#define UDMA_TCHAN_TCQ_REG 0x14 +#define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4) +#define UDMA_TCHAN_TEOES_REG 0x60 +#define UDMA_TCHAN_TPRI_CTRL_REG 0x64 +#define UDMA_TCHAN_THREAD_ID_REG 0x68 +#define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70 +#define UDMA_TCHAN_TST_SCHED_REG 0x80 + +/* RX chan regs */ +#define UDMA_RCHAN_RCFG_REG0x0 +#define UDMA_RCHAN_RCQ_REG 0x14 +#define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4) +#define UDMA_RCHAN_REOES_REG 0x60 +#define UDMA_RCHAN_RPRI_CTRL_REG 0x64 +#define UDMA_RCHAN_THREAD_ID_REG 0x68 +#d
[U-Boot] [PATCH v4 1/7] firmware: ti_sci: Add support for NAVSS resource management
From: Grygorii Strashko
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.
This patch adds support for requesting and configuring such resources
from TI-SCI firmware.
Signed-off-by: Peter Ujfalusi
Signed-off-by: Grygorii Strashko
Reviewed-by: Tom Rini
Signed-off-by: Vignesh R
---
arch/arm/dts/k3-am65-wakeup.dtsi | 2 +-
drivers/firmware/ti_sci.c | 760 -
drivers/firmware/ti_sci.h | 642 +
include/linux/soc/ti/ti_sci_protocol.h | 300 ++
4 files changed, 1692 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
index 8d7b47f9dfbf..1f591ef8bb9e 100644
--- a/arch/arm/dts/k3-am65-wakeup.dtsi
+++ b/arch/arm/dts/k3-am65-wakeup.dtsi
@@ -7,7 +7,7 @@
_wakeup {
dmsc: dmsc {
- compatible = "ti,k2g-sci";
+ compatible = "ti,am654-sci";
ti,host-id = <12>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 91481260411a..ec78a520e702 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -31,16 +32,37 @@ struct ti_sci_xfer {
u8 rx_len;
};
+/**
+ * struct ti_sci_rm_type_map - Structure representing TISCI Resource
+ * management representation of dev_ids.
+ * @dev_id:TISCI device ID
+ * @type: Corresponding id as identified by TISCI RM.
+ *
+ * Note: This is used only as a work around for using RM range apis
+ * for AM654 SoC. For future SoCs dev_id will be used as type
+ * for RM range APIs. In order to maintain ABI backward compatibility
+ * type is not being changed for AM654 SoC.
+ */
+struct ti_sci_rm_type_map {
+ u32 dev_id;
+ u16 type;
+};
+
/**
* struct ti_sci_desc - Description of SoC integration
- * @host_id: Host identifier representing the compute entity
- * @max_rx_timeout_us: Timeout for communication with SoC (in Microseconds)
- * @max_msg_size: Maximum size of data per message that can be handled.
+ * @default_host_id: Host identifier representing the compute entity
+ * @max_rx_timeout_ms: Timeout for communication with SoC (in Milliseconds)
+ * @max_msgs: Maximum number of messages that can be pending
+ * simultaneously in the system
+ * @max_msg_size: Maximum size of data per message that can be handled.
+ * @rm_type_map: RM resource type mapping structure.
*/
struct ti_sci_desc {
- u8 host_id;
- int max_rx_timeout_us;
+ u8 default_host_id;
+ int max_rx_timeout_ms;
+ int max_msgs;
int max_msg_size;
+ struct ti_sci_rm_type_map *rm_type_map;
};
/**
@@ -136,7 +158,7 @@ static inline int ti_sci_get_response(struct ti_sci_info
*info,
int ret;
/* Receive the response */
- ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_us);
+ ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms);
if (ret) {
dev_err(info->dev, "%s: Message receive failed. ret = %d\n",
__func__, ret);
@@ -1441,6 +1463,147 @@ static int ti_sci_cmd_core_reboot(const struct
ti_sci_handle *handle)
return ret;
}
+static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
+ u16 *type)
+{
+ struct ti_sci_rm_type_map *rm_type_map = info->desc->rm_type_map;
+ bool found = false;
+ int i;
+
+ /* If map is not provided then assume dev_id is used as type */
+ if (!rm_type_map) {
+ *type = dev_id;
+ return 0;
+ }
+
+ for (i = 0; rm_type_map[i].dev_id; i++) {
+ if (rm_type_map[i].dev_id == dev_id) {
+ *type = rm_type_map[i].type;
+ found = true;
+ break;
+ }
+ }
+
+ if (!found)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * ti_sci_get_resource_range - Helper to get a range of resources assigned
+ *to a host. Resource is uniquely identified by
+ *type and subtype.
+ * @handle:Pointer to TISCI handle.
+ * @dev_id:TISCI device ID.
+ * @subtype: Resource assignment subtype that is being requested
+ * from the given device.
+ * @s_host:Host processor ID to which the resources are allocated
+ * @range_start: Start index of the resource range
+ * @range_num: Number of resources in the range
+ *
+ * Return
[U-Boot] [PATCH v4 2/7] soc: ti: k3: add navss ringacc driver
From: Grygorii Strashko The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh R --- drivers/Kconfig |2 + drivers/soc/Kconfig |5 + drivers/soc/Makefile|1 + drivers/soc/ti/Kconfig | 20 + drivers/soc/ti/Makefile |5 + drivers/soc/ti/k3-navss-ringacc.c | 1057 +++ include/linux/soc/ti/k3-navss-ringacc.h | 236 + 7 files changed, 1326 insertions(+) create mode 100644 drivers/soc/Kconfig create mode 100644 drivers/soc/ti/Kconfig create mode 100644 drivers/soc/ti/Makefile create mode 100644 drivers/soc/ti/k3-navss-ringacc.c create mode 100644 include/linux/soc/ti/k3-navss-ringacc.h diff --git a/drivers/Kconfig b/drivers/Kconfig index e9fbadd13d5a..1eedb3462b0a 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -96,6 +96,8 @@ source "drivers/smem/Kconfig" source "drivers/sound/Kconfig" +source "drivers/soc/Kconfig" + source "drivers/spi/Kconfig" source "drivers/spmi/Kconfig" diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig new file mode 100644 index ..7b4e4d613088 --- /dev/null +++ b/drivers/soc/Kconfig @@ -0,0 +1,5 @@ +menu "SOC (System On Chip) specific Drivers" + +source "drivers/soc/ti/Kconfig" + +endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 42037f99d587..8b7ead546e1c 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -3,3 +3,4 @@ # Makefile for the U-Boot SOC specific device drivers. obj-$(CONFIG_ARCH_KEYSTONE)+= keystone/ +obj-$(CONFIG_SOC_TI) += ti/ diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig new file mode 100644 index ..8c0f3c07b23f --- /dev/null +++ b/drivers/soc/ti/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ + +menuconfig SOC_TI + bool "TI SOC drivers support" + +if SOC_TI + +config TI_K3_NAVSS_RINGACC + bool "K3 Ring accelerator Sub System" + depends on ARCH_K3 + select MISC + help + Say y here to support the K3 AM65x Ring accelerator module. + The Ring Accelerator (RINGACC or RA) provides hardware acceleration + to enable straightforward passing of work between a producer + and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs + If unsure, say N. + + +endif # SOC_TI diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile new file mode 100644 index ..63e21aaad40f --- /dev/null +++ b/drivers/soc/ti/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# TI K3 SOC drivers +# +obj-$(CONFIG_TI_K3_NAVSS_RINGACC) += k3-navss-ringacc.o diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c new file mode 100644 index ..fcb84f7aa49b --- /dev/null +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -0,0 +1,1057 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define set
[U-Boot] [PATCH v4 3/7] soc: ti: k3: add CPPI5 description and helpers
From: Grygorii Strashko
Add TI Communications Port Programming Interface (CPPI) 5
interface description and helpers
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
include/linux/soc/ti/cppi5.h | 995 +++
1 file changed, 995 insertions(+)
create mode 100644 include/linux/soc/ti/cppi5.h
diff --git a/include/linux/soc/ti/cppi5.h b/include/linux/soc/ti/cppi5.h
new file mode 100644
index ..34038b31f702
--- /dev/null
+++ b/include/linux/soc/ti/cppi5.h
@@ -0,0 +1,995 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * CPPI5 descriptors interface
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#ifndef __TI_CPPI5_H__
+#define __TI_CPPI5_H__
+
+#include
+#include
+
+/**
+ * Descriptor header, present in all types of descriptors
+ */
+struct cppi5_desc_hdr_t {
+ u32 pkt_info0; /* Packet info word 0 (n/a in Buffer desc) */
+ u32 pkt_info1; /* Packet info word 1 (n/a in Buffer desc) */
+ u32 pkt_info2; /* Packet info word 2 Buffer reclamation info */
+ u32 src_dst_tag; /* Packet info word 3 (n/a in Buffer desc) */
+} __packed;
+
+/**
+ * Host-mode packet and buffer descriptor definition
+ */
+struct cppi5_host_desc_t {
+ struct cppi5_desc_hdr_t hdr;
+ u64 next_desc; /* w4/5: Linking word */
+ u64 buf_ptr;/* w6/7: Buffer pointer */
+ u32 buf_info1; /* w8: Buffer valid data length */
+ u32 org_buf_len; /* w9: Original buffer length */
+ u64 org_buf_ptr; /* w10/11: Original buffer pointer */
+ u32 epib[0];/* Extended Packet Info Data (optional, 4 words) */
+ /*
+* Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
+* and/or Other Software Data (0-N bytes, optional)
+*/
+} __packed;
+
+#define CPPI5_DESC_MIN_ALIGN (16U)
+
+#define CPPI5_INFO0_HDESC_EPIB_SIZE(16U)
+#define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE (128U)
+
+#define CPPI5_INFO0_HDESC_TYPE_SHIFT (30U)
+#define CPPI5_INFO0_HDESC_TYPE_MASKGENMASK(31, 30)
+#define CPPI5_INFO0_DESC_TYPE_VAL_HOST (1U)
+#define CPPI5_INFO0_DESC_TYPE_VAL_MONO (2U)
+#define CPPI5_INFO0_DESC_TYPE_VAL_TR (3U)
+#define CPPI5_INFO0_HDESC_EPIB_PRESENT BIT(29)
+/*
+ * Protocol Specific Words location:
+ * 0 - located in the descriptor,
+ * 1 = located in the SOP Buffer immediately prior to the data.
+ */
+#define CPPI5_INFO0_HDESC_PSINFO_LOCATION BIT(28)
+#define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT(22U)
+#define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
+#define CPPI5_INFO0_HDESC_PKTLEN_SHIFT (0)
+#define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
+
+#define CPPI5_INFO1_DESC_PKTERROR_SHIFT(28U)
+#define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
+#define CPPI5_INFO1_HDESC_PSFLGS_SHIFT (24U)
+#define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
+#define CPPI5_INFO1_DESC_PKTID_SHIFT (14U)
+#define CPPI5_INFO1_DESC_PKTID_MASKGENMASK(23, 14)
+#define CPPI5_INFO1_DESC_FLOWID_SHIFT (0)
+#define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
+
+#define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT(27U)
+#define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
+/* Return Policy: 0 - Entire packet 1 - Each buffer */
+#define CPPI5_INFO2_HDESC_RETPOLICYBIT(18)
+/*
+ * Early Return:
+ * 0 = desc pointers should be returned after all reads have been completed
+ * 1 = desc pointers should be returned immediately upon fetching
+ * the descriptor and beginning to transfer data.
+ */
+#define CPPI5_INFO2_HDESC_EARLYRET BIT(17)
+/*
+ * Return Push Policy:
+ * 0 = Descriptor must be returned to tail of queue
+ * 1 = Descriptor must be returned to head of queue
+ */
+#define CPPI5_INFO2_DESC_RETPUSHPOLICY BIT(16)
+#define CPPI5_INFO2_DESC_RETQ_SHIFT(0)
+#define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
+
+#define CPPI5_INFO3_DESC_SRCTAG_SHIFT (16U)
+#define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)
+#define CPPI5_INFO3_DESC_DSTTAG_SHIFT (0)
+#define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0)
+
+#define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT(0)
+#define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0)
+
+#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT(0)
+#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0)
+
+/*
+ * Host Packet Descriptor Extended Packet Info Block
+ */
+struct cppi5_desc_epib_t {
+ u32 timestamp; /* w0: application specific timestamp */
+ u32 sw_info0; /* w1: Software Info 0 */
+ u32 sw_info1; /* w2: Software Info 1 */
+ u32 sw_info2; /* w3: Software Info 2 */
+};
+
+/**
+ * Monolithic-mode packet descriptor
+ */
+struct cppi5_monolithic_desc_t {
+ struct cppi5_desc_hdr_t hdr
[U-Boot] [PATCH v4 0/7] AM65x: Add DMA support
This series adds DMA support for TI's AM654 SoC.
v4:
Convert debug prints to pr_debug()s
Collect R-bs
v3:
Minor comment/whitespace cleanups as pointed out by Tom Rini
v2:
Align DT bindings with latest proposed bindings as pointed out by Peter.
Merge drivers/soc/keystone into drivers/soc/ti
Background:
The AM65x TRM (http://www.ti.com/lit/pdf/spruid7b) describes the Data Movement
Architecture which is implmented by the k3-udma driver.
This DMA architecture is a big departure from 'traditional' architecture where
we had either EDMA or sDMA as system DMA.
Packet DMAs were used as dedicated DMAs to service only networking (K2)
or USB (am335x) while other peripherals were serviced by EDMA.
In AM65x the UDMA (Unified DMA) is used for all data movment within the SoC,
tasked to service all peripherals (UART, McSPI, McASP, networking, etc).
The NAVSS/UDMA is built around CPPI5 (Communications Port Programming Interface)
and it supports Packet mode (similar to CPPI4.1 in K2 for networking) and
TR mode (similar to EDMA descriptor).
The data movement is done within a PSI-L fabric, all peripherals (including the
UDMA-P). peripherals are not addressed by their I/O register as with traditional
DMAs but with their PSI-L thread ID.
To be able to use the DMA the following generic steps need to be taken:
- configure a DMA channel (tchan for TX, rchan for RX)
- channel mode: Packet or TR mode
- for memcpy a tchan and rchan pair is used.
- for packet mode RX we also need to configure a receive flow to configure the
packet receiption
- the source and destination threads must be paired
- at minimum one pair of rings need to be configured:
- tx: transfer ring and transfer completion ring
- rx: free descriptor ring and receive ring
When the channel setup is completed we only interract with the rings:
- TX: push a descriptor to t_ring and wait for it to be pushed to the tc_ring by
the UDMA-P
- RX: push a descriptor to the fd_ring and wait for UDMA-P to push it back to
the r_ring.
Resources Management and configuration of channel and ring is handled by
sending TI-SCI msgs to remote core.
Patches are based on kernel patches here:
https://patchwork.kernel.org/cover/10612465/
Grygorii Strashko (5):
firmware: ti_sci: Add support for NAVSS resource management
soc: ti: k3: add navss ringacc driver
soc: ti: k3: add CPPI5 description and helpers
arm64: dts: ti: k3-am65: add mcu navss nodes
configs: am65x_evm_a53: Enable DMA related configs
Vignesh R (2):
dma: ti: add driver to K3 UDMA
soc: keystone: Merge into ti specific directory
arch/arm/dts/k3-am65-wakeup.dtsi |2 +-
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 47 +
arch/arm/mach-keystone/Kconfig|8 +
configs/am65x_evm_a53_defconfig |4 +-
drivers/Kconfig |2 +
drivers/dma/Kconfig |2 +
drivers/dma/Makefile |2 +
drivers/dma/ti/Kconfig| 14 +
drivers/dma/ti/Makefile |3 +
drivers/dma/ti/k3-udma-hwdef.h| 184 ++
drivers/dma/ti/k3-udma.c | 1730 +
drivers/firmware/ti_sci.c | 760 +++-
drivers/firmware/ti_sci.h | 642 ++
drivers/soc/Kconfig |5 +
drivers/soc/Makefile |2 +-
drivers/soc/keystone/Makefile |3 -
drivers/soc/ti/Kconfig| 26 +
drivers/soc/ti/Makefile |4 +
drivers/soc/ti/k3-navss-ringacc.c | 1057 ++
.../soc/{keystone => ti}/keystone_serdes.c|0
include/configs/ti_armv7_keystone2.h |3 -
include/dt-bindings/dma/k3-udma.h | 31 +
include/linux/soc/ti/cppi5.h | 995 ++
include/linux/soc/ti/k3-navss-ringacc.h | 236 +++
include/linux/soc/ti/ti-udma.h| 24 +
include/linux/soc/ti/ti_sci_protocol.h| 300 +++
scripts/config_whitelist.txt |1 -
27 files changed, 6066 insertions(+), 21 deletions(-)
create mode 100644 drivers/dma/ti/Kconfig
create mode 100644 drivers/dma/ti/Makefile
create mode 100644 drivers/dma/ti/k3-udma-hwdef.h
create mode 100644 drivers/dma/ti/k3-udma.c
create mode 100644 drivers/soc/Kconfig
delete mode 100644 drivers/soc/keystone/Makefile
create mode 100644 drivers/soc/ti/Kconfig
create mode 100644 drivers/soc/ti/Makefile
create mode 100644 drivers/soc/ti/k3-navss-ringacc.c
rename drivers/soc/{keystone => ti}/keystone_serdes.c (100%)
create mode 100644 include/dt-bindings/dma/k3-udma.h
create mode 100644 include/linux/soc/ti/cppi5.h
create mode 100644 include/linux/soc/ti/k3-navss-ringacc.h
create mode 100644 include/linux/soc/ti/ti-udma.h
--
2.20.1
___
U-Boot mailing list
U-Boot@lists.d
Re: [U-Boot] [PULL] Please pull u-boot-rockchip:tags/for-master-20190201
On 01/02/19 10:45 PM, Philipp Tomsich wrote: > Tom, > > I am a little late this time with our changes for rc1. Hope this doesn’t > impact your workflow too much. > Things got a bit messy this time, as some of the series introduced unexpected > isses during testing > (such as the debug UART not being available). > > Travis is still running > (https://travis-ci.org/ptomsich/u-boot-rockchip/builds/487509207) on the > rebased > version, but prior to the rebase (and the final fixes), things were testing > out correctly. > > Thanks, > Philipp. > > [...] > create mode 100644 configs/kylin-rk3036_defconfig.rej > create mode 100644 configs/puma-rk3399_defconfig.rej I think you added these files by mistake. Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 14/20] mtd: spi: Switch to new SPI NOR framework
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/mtd/spi/Kconfig| 2 +
drivers/mtd/spi/Makefile | 4 +-
drivers/mtd/spi/sandbox.c | 36 +++---
drivers/mtd/spi/sf_dataflash.c | 11 +-
drivers/mtd/spi/sf_internal.h | 225 ++---
drivers/mtd/spi/sf_probe.c | 32 +++--
drivers/mtd/spi/spi-nor-core.c | 59 +
drivers/spi/stm32_qspi.c | 4 +-
include/spi_flash.h| 105 ---
9 files changed, 113 insertions(+), 365 deletions(-)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 4ba95d58b371..e3b40fc157d6 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -27,6 +27,8 @@ config SPI_FLASH_SANDBOX
config SPI_FLASH
bool "Legacy SPI Flash Interface support"
+ depends on SPI
+ select SPI_MEM
help
Enable the legacy SPI flash support. This will include basic
standard support for things like probing, read / write, and
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index b4c7e1c98bd5..70058d3df2b9 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -9,7 +9,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
-obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
+obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 7b9891cb981c..084c66e9840b 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -92,7 +92,7 @@ struct sandbox_spi_flash {
/* The current flash status (see STAT_XXX defines above) */
u16 status;
/* Data describing the flash we're emulating */
- const struct spi_flash_info *data;
+ const struct flash_info *data;
/* The file on disk to serv up data from */
int fd;
};
@@ -122,7 +122,7 @@ static int sandbox_sf_probe(struct udevice *dev)
/* spec = idcode:file */
struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
size_t len, idname_len;
- const struct spi_flash_info *data;
+ const struct flash_info *data;
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
struct sandbox_state *state = state_get_current();
struct dm_spi_slave_platdata *slave_plat;
@@ -155,7 +155,7 @@ static int sandbox_sf_probe(struct udevice *dev)
idname_len = strlen(spec);
debug("%s: device='%s'\n", __func__, spec);
- for (data = spi_flash_ids; data->name; data++) {
+ for (data = spi_nor_ids; data->name; data++) {
len = strlen(data->name);
if (idname_len != len)
continue;
@@ -243,43 +243,43 @@ static int sandbox_sf_process_cmd(struct
sandbox_spi_flash *sbsf, const u8 *rx,
sbsf->cmd = rx[0];
switch (sbsf->cmd) {
- case CMD_READ_ID:
+ case SPINOR_OP_RDID:
sbsf->state = SF_ID;
sbsf->cmd = SF_ID;
break;
- case CMD_READ_ARRAY_FAST:
+ case SPINOR_OP_READ_FAST:
sbsf->pad_addr_bytes = 1;
- case CMD_READ_ARRAY_SLOW:
- case CMD_PAGE_PROGRAM:
+ case SPINOR_OP_READ:
+ case SPINOR_OP_PP:
sbsf->state = SF_ADDR;
break;
- case CMD_WRITE_DISABLE:
+ case SPINOR_OP_WRDI:
debug(" write disabled\n");
sbsf->status &= ~STAT_WEL;
break;
- case CMD_READ_STATUS:
+ case SPINOR_OP_RDSR:
sbsf->state = SF_READ_STATUS;
break;
- case CMD_READ_STATUS1:
+ case SPINOR_OP_RDSR2:
sbsf->state = SF_READ_STATUS1;
break;
- case CMD_WRITE_ENABLE:
+ case SPINOR_OP_WREN:
debug(" write enabled\n");
sbsf->status |= STAT_WEL;
break;
- case CMD_WRITE_STATUS:
+ case SPINOR_OP_WRSR:
sbsf->state = SF_WRITE_STATUS;
break;
default: {
int flags = sbsf->data->flags;
/* we only support erase here */
- if (sbsf->cmd == CMD_ERASE_CHIP) {
+ if (sbsf->cmd == SPINOR_OP_CHIP_ERASE) {
sbsf->erase_size = sbsf->data->sector_size *
[U-Boot] [PATCH v4 15/20] mtd: spi: Remove unused files
spi_flash and spi_flash_ids are no longer needed after SPI NOR
migration. Remove them.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/mtd/spi/spi_flash.c | 1337 ---
drivers/mtd/spi/spi_flash_ids.c | 211 -
2 files changed, 1548 deletions(-)
delete mode 100644 drivers/mtd/spi/spi_flash.c
delete mode 100644 drivers/mtd/spi/spi_flash_ids.c
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
deleted file mode 100644
index 0c2392f28a43..
--- a/drivers/mtd/spi/spi_flash.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPI Flash Core
- *
- * Copyright (C) 2015 Jagan Teki
- * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
- * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
- * Copyright (C) 2008 Atmel Corporation
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "sf_internal.h"
-
-static void spi_flash_addr(u32 addr, u8 *cmd)
-{
- /* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
-}
-
-static int read_sr(struct spi_flash *flash, u8 *rs)
-{
- int ret;
- u8 cmd;
-
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, , 1, rs, 1);
- if (ret < 0) {
- debug("SF: fail to read status register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int read_fsr(struct spi_flash *flash, u8 *fsr)
-{
- int ret;
- const u8 cmd = CMD_FLAG_STATUS;
-
- ret = spi_flash_read_common(flash, , 1, fsr, 1);
- if (ret < 0) {
- debug("SF: fail to read flag status register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_sr(struct spi_flash *flash, u8 ws)
-{
- u8 cmd;
- int ret;
-
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, , 1, , 1);
- if (ret < 0) {
- debug("SF: fail to write status register\n");
- return ret;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int read_cr(struct spi_flash *flash, u8 *rc)
-{
- int ret;
- u8 cmd;
-
- cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash, , 1, rc, 1);
- if (ret < 0) {
- debug("SF: fail to read config register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_cr(struct spi_flash *flash, u8 wc)
-{
- u8 data[2];
- u8 cmd;
- int ret;
-
- ret = read_sr(flash, [0]);
- if (ret < 0)
- return ret;
-
- cmd = CMD_WRITE_STATUS;
- data[1] = wc;
- ret = spi_flash_write_common(flash, , 1, , 2);
- if (ret) {
- debug("SF: fail to write config register\n");
- return ret;
- }
-
- return 0;
-}
-#endif
-
-int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash)
-{
- u8 status;
- int ret;
-
- ret = read_sr(flash, );
- if (ret)
- return ret;
-
- return (status >> 2) & 7;
-}
-
-#ifdef CONFIG_SPI_FLASH_BAR
-/*
- * This "clean_bar" is necessary in a situation when one was accessing
- * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
- *
- * After it the BA24 bit shall be cleared to allow access to correct
- * memory region after SW reset (by calling "reset" command).
- *
- * Otherwise, the BA24 bit may be left set and then after reset, the
- * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
- */
-static int clean_bar(struct spi_flash *flash)
-{
- u8 cmd, bank_sel = 0;
-
- if (flash->bank_curr == 0)
- return 0;
- cmd = flash->bank_write_cmd;
- flash->bank_curr = 0;
-
- return spi_flash_write_common(flash, , 1, _sel, 1);
-}
-
-static int write_bar(struct spi_flash *flash, u32 offset)
-{
- u8 cmd, bank_sel;
- int ret;
-
- bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
- if (bank_sel == flash->bank_curr)
- goto bar_end;
-
- cmd = flash->bank_write_cmd;
- ret = spi_flash_write_common(flash, , 1, _sel, 1);
- if (ret < 0) {
- debug("SF: fail to write bank register\n");
- return ret;
- }
-
-bar_end:
- flash->bank_curr = bank_sel;
- return flash->bank_curr;
-}
-
-static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
-{
- u8 curr_bank = 0;
- int ret;
-
- if (flash->size <= SPI_FLASH_
[U-Boot] [PATCH v4 19/20] configs: Don't use SPI_FLASH_BAR as default
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R Tested-by: Simon Goldschmidt Tested-by: Stefan Roese Tested-by: Horatiu Vultur Reviewed-by: Jagan Teki Tested-by: Jagan Teki #zynq-microzed --- arch/arm/mach-omap2/am33xx/Kconfig | 1 - configs/alt_defconfig| 1 - configs/am57xx_evm_defconfig | 1 - configs/am57xx_hs_evm_defconfig | 1 - configs/ap121_defconfig | 1 - configs/ap143_defconfig | 1 - configs/avnet_ultra96_rev1_defconfig | 1 - configs/axs101_defconfig | 1 - configs/axs103_defconfig | 1 - configs/bg0900_defconfig | 1 - configs/blanche_defconfig| 1 - configs/cl-som-am57x_defconfig | 1 - configs/clearfog_defconfig | 1 - configs/cm_t43_defconfig | 1 - configs/db-88f6820-amc_defconfig | 1 - configs/display5_defconfig | 1 - configs/display5_factory_defconfig | 1 - configs/dra7xx_evm_defconfig | 1 - configs/dra7xx_hs_evm_defconfig | 1 - configs/ds109_defconfig | 1 - configs/ds414_defconfig | 1 - configs/evb-rv1108_defconfig | 1 - configs/gose_defconfig | 1 - configs/helios4_defconfig| 1 - configs/k2g_evm_defconfig| 1 - configs/k2g_hs_evm_defconfig | 1 - configs/koelsch_defconfig| 1 - configs/lager_defconfig | 1 - configs/maxbcm_defconfig | 1 - configs/mt7629_rfb_defconfig | 1 - configs/mx6sxsabreauto_defconfig | 1 - configs/mx6sxsabresd_defconfig | 1 - configs/mx6ul_14x14_evk_defconfig| 1 - configs/mx6ul_9x9_evk_defconfig | 1 - configs/mx6ull_14x14_evk_defconfig | 1 - configs/mx6ull_14x14_evk_plugin_defconfig| 1 - configs/mx7dsabresd_qspi_defconfig | 1 - configs/porter_defconfig | 1 - configs/r8a77970_eagle_defconfig | 1 - configs/silk_defconfig | 1 - configs/socfpga_arria5_defconfig | 1 - configs/socfpga_cyclone5_defconfig | 1 - configs/socfpga_is1_defconfig| 1 - configs/socfpga_sockit_defconfig | 1 - configs/socfpga_socrates_defconfig | 1 - configs/socfpga_sr1500_defconfig | 1 - configs/socfpga_stratix10_defconfig | 1 - configs/stout_defconfig | 1 - configs/topic_miami_defconfig| 1 - configs/topic_miamilite_defconfig| 1 - configs/topic_miamiplus_defconfig| 1 - configs/xilinx_versal_virt_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig| 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - configs/zynq_cc108_defconfig | 1 - configs/zynq_cse_qspi_defconfig | 1 - configs/zynq_dlc20_rev1_0_defconfig | 1 - configs/zynq_microzed_defconfig | 1 - configs/zynq_minized_defconfig | 1 - configs/zynq_z_turn_defconfig| 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 1 - configs/zynq_zybo_z7_defconfig
[U-Boot] [PATCH v4 16/20] mtd: spi: Add lightweight SPI flash stack for SPL
Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.
Based on prior work of reducing spi flash id table by
Simon Goldschmidt
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
common/spl/Kconfig | 11 +-
drivers/mtd/spi/Makefile | 10 +-
drivers/mtd/spi/sf_internal.h | 2 +
drivers/mtd/spi/spi-nor-core.c | 266 +--
drivers/mtd/spi/spi-nor-ids.c | 297
drivers/mtd/spi/spi-nor-tiny.c | 804 +
6 files changed, 1126 insertions(+), 264 deletions(-)
create mode 100644 drivers/mtd/spi/spi-nor-ids.c
create mode 100644 drivers/mtd/spi/spi-nor-tiny.c
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 138537b4ce9a..983acca85d9d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -739,9 +739,18 @@ config SPL_SPI_FLASH_SUPPORT
if SPL_SPI_FLASH_SUPPORT
+config SPL_SPI_FLASH_TINY
+ bool "Enable low footprint SPL SPI Flash support"
+ depends on !SPI_FLASH_BAR
+ help
+Enable lightweight SPL SPI Flash support that supports just reading
+data/images from flash. No support to write/erase flash. Enable
+this if you have SPL size limitations and don't need full
+fledged SPI flash support.
+
config SPL_SPI_FLASH_SFDP_SUPPORT
bool "SFDP table parsing support for SPI NOR flashes"
- depends on !SPI_FLASH_BAR
+ depends on !SPI_FLASH_BAR && !SPL_SPI_FLASH_TINY
help
Enable support for parsing and auto discovery of parameters for
SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 70058d3df2b9..f99f6cb16e29 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -4,12 +4,20 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+spi-nor-y := sf_probe.o spi-nor-ids.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
+ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y)
+spi-nor-y += spi-nor-tiny.o
+else
+spi-nor-y += spi-nor-core.o
+endif
+else
+spi-nor-y += spi-nor-core.o
endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
+obj-$(CONFIG_SPI_FLASH) += spi-nor.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index fd00e0d1b23b..a6bf734830a7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -16,7 +16,9 @@
#define SPI_NOR_MAX_ADDR_WIDTH 4
struct flash_info {
+#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
char*name;
+#endif
/*
* This array stores the ID bytes.
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 7590ff7716e8..b7f073387796 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -879,284 +879,26 @@ static int stm_is_locked(struct spi_nor *nor, loff_t
ofs, uint64_t len)
}
#endif /* CONFIG_SPI_FLASH_STMICRO */
-/* Used when the "_ext_id" is two bytes at most */
-#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
- .id = { \
- ((_jedec_id) >> 16) & 0xff, \
- ((_jedec_id) >> 8) & 0xff, \
- (_jedec_id) & 0xff, \
- ((_ext_id) >> 8) & 0xff,\
- (_ext_id) & 0xff, \
- }, \
- .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),
\
- .sector_size = (_sector_size), \
- .n_sectors = (_n_sectors), \
- .page_size = 256, \
- .flags = (_flags),
-
-#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
- .id = { \
- ((_jedec_id) >> 16) & 0xff, \
- ((_jedec_id) >> 8) & 0xff, \
- (_jedec_id) & 0xff, \
- ((_ext_id) >> 16) & 0xff,
[U-Boot] [PATCH v4 17/20] spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL
SPL only needs to be able to read from SPI Flash to load next stage and does not really need write/erase etc. Therefore in order to reduce SPI Flash code size in SPL, enable SPI_FLASH_TINY, that only supports reading from SPI flash, as default. Note: Since, SPI_FLASH_TINY does not support SPI_FLASH_BAR, SPI_FLASH_TINY is not enabled for boards with SPI controllers that cannot support 4 byte addressing. Signed-off-by: Vignesh R Reviewed-by: Jagan Teki Tested-by: Jagan Teki #zynq-microzed --- common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 983acca85d9d..935066d66487 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -742,6 +742,7 @@ if SPL_SPI_FLASH_SUPPORT config SPL_SPI_FLASH_TINY bool "Enable low footprint SPL SPI Flash support" depends on !SPI_FLASH_BAR + default y if SPI_FLASH help Enable lightweight SPL SPI Flash support that supports just reading data/images from flash. No support to write/erase flash. Enable -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 18/20] configs: Remove SF_DUAL_FLASH
SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above enums yield no user and therefore support seems to be incomplete. Remove these configs so as to avoid confusion. Signed-off-by: Vignesh R Reviewed-by: Jagan Teki Tested-by: Jagan Teki #zynq-microzed --- configs/topic_miamilite_defconfig | 1 - configs/topic_miamiplus_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - doc/SPI/README.dual-flash | 92 --- include/configs/socfpga_stratix10_socdk.h | 1 - 17 files changed, 108 deletions(-) delete mode 100644 doc/SPI/README.dual-flash diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index e4d52f6a915e..95fa7678d639 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -40,7 +40,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index f742838d7c1f..6d753c0326a1 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -39,7 +39,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_NETDEVICES is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 3ec435e7ffe7..911d1beed2e1 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -54,7 +54,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 9026f00649bb..1b0df0c7b9a3 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 3eed06976053..043ce80b5916 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index 8bd7c9c57842..51ed37038d40 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 9f023c2bd2bd..04c73b7d0170 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -42,7 +42,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index f2caac790a1a..dd6f50df4ee4 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -62,7 +62,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git
[U-Boot] [PATCH v4 10/20] mtd: spi: spi-nor-core: Add 4 Byte addressing support
Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/mtd/spi/spi-nor-core.c | 141 +
1 file changed, 141 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 66e94258b6c5..523e44cbba2a 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -290,6 +290,126 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info
*mtd)
return mtd->priv;
}
+static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
+{
+ size_t i;
+
+ for (i = 0; i < size; i++)
+ if (table[i][0] == opcode)
+ return table[i][1];
+
+ /* No conversion found, keep input op code. */
+ return opcode;
+}
+
+static u8 spi_nor_convert_3to4_read(u8 opcode)
+{
+ static const u8 spi_nor_3to4_read[][2] = {
+ { SPINOR_OP_READ, SPINOR_OP_READ_4B },
+ { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
+ { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
+ { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
+ { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
+ { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+
+ { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
+ { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
+ { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
+ };
+
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
+ ARRAY_SIZE(spi_nor_3to4_read));
+}
+
+static u8 spi_nor_convert_3to4_program(u8 opcode)
+{
+ static const u8 spi_nor_3to4_program[][2] = {
+ { SPINOR_OP_PP, SPINOR_OP_PP_4B },
+ { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
+ { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ };
+
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
+ ARRAY_SIZE(spi_nor_3to4_program));
+}
+
+static u8 spi_nor_convert_3to4_erase(u8 opcode)
+{
+ static const u8 spi_nor_3to4_erase[][2] = {
+ { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
+ { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
+ { SPINOR_OP_SE, SPINOR_OP_SE_4B },
+ };
+
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
+ ARRAY_SIZE(spi_nor_3to4_erase));
+}
+
+static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
+ const struct flash_info *info)
+{
+ /* Do some manufacturer fixups first */
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_SPANSION:
+ /* No small sector erase for 4-byte command set */
+ nor->erase_opcode = SPINOR_OP_SE;
+ nor->mtd.erasesize = info->sector_size;
+ break;
+
+ default:
+ break;
+ }
+
+ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
+ nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
+ nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
+}
+
+/* Enable/disable 4-byte addressing mode. */
+static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
+int enable)
+{
+ int status;
+ bool need_wren = false;
+ u8 cmd;
+
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_ST:
+ case SNOR_MFR_MICRON:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+ case SNOR_MFR_MACRONIX:
+ case SNOR_MFR_WINBOND:
+ if (need_wren)
+ write_enable(nor);
+
+ cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
+ status = nor->write_reg(nor, cmd, NULL, 0);
+ if (need_wren)
+ write_disable(nor);
+
+ if (!status && !enable &&
+ JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
+ /*
+* On Winbond W25Q256FV, leaving 4byte mode causes
+* the Extended Address Register to be set to 1, so all
+* 3-byte-address reads come from the second 16M.
+* We must clear the register to enable normal behavior.
+*/
+ write_enable(nor);
+ nor->
[U-Boot] [PATCH v4 20/20] MAINTAINERS: Add an entry for SPI NOR
Add myself as co-maintainer for U-Boot SPI NOR subsystem. Signed-off-by: Vignesh R Reviewed-by: Jagan Teki --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e3a15868bcad..e5f897b39d59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -690,6 +690,15 @@ F: drivers/mtd/spi/ F: drivers/spi/ F: include/spi* +SPI-NOR +M: Jagan Teki +M: Vignesh R +S: Maintained +F: drivers/mtd/spi/ +F: include/spi_flash.h +F: include/linux/mtd/cfi.h +F: include/linux/mtd/spi-nor.h + SPMI M: Mateusz Kulikowski S: Maintained -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 11/20] mtd: spi: spi-nor-core: Add SFDP support
Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
common/spl/Kconfig | 13 +-
drivers/mtd/spi/Kconfig| 14 +-
drivers/mtd/spi/spi-nor-core.c | 629 -
3 files changed, 649 insertions(+), 7 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 59028529c92e..138537b4ce9a 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -737,13 +737,24 @@ config SPL_SPI_FLASH_SUPPORT
lines). This enables the drivers in drivers/mtd/spi as part of an
SPL build. This normally requires SPL_SPI_SUPPORT.
+if SPL_SPI_FLASH_SUPPORT
+
+config SPL_SPI_FLASH_SFDP_SUPPORT
+ bool "SFDP table parsing support for SPI NOR flashes"
+ depends on !SPI_FLASH_BAR
+ help
+Enable support for parsing and auto discovery of parameters for
+SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
+tables as per JESD216 standard in SPL.
+
config SPL_SPI_LOAD
bool "Support loading from SPI flash"
- depends on SPL_SPI_FLASH_SUPPORT
help
Enable support for loading next stage, U-Boot or otherwise, from
SPI NOR in U-Boot SPL.
+endif # SPL_SPI_FLASH_SUPPORT
+
config SPL_SPI_SUPPORT
bool "Support SPI drivers"
help
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 76d5a1d11527..4ba95d58b371 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -34,9 +34,18 @@ config SPI_FLASH
If unsure, say N
+if SPI_FLASH
+
+config SPI_FLASH_SFDP_SUPPORT
+ bool "SFDP table parsing support for SPI NOR flashes"
+ depends on !SPI_FLASH_BAR
+ help
+Enable support for parsing and auto discovery of parameters for
+SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
+tables as per JESD216 standard.
+
config SPI_FLASH_BAR
bool "SPI flash Bank/Extended address register support"
- depends on SPI_FLASH
help
Enable the SPI flash Bank/Extended address register support.
Bank/Extended address registers are used to access the flash
@@ -44,13 +53,10 @@ config SPI_FLASH_BAR
config SF_DUAL_FLASH
bool "SPI DUAL flash memory support"
- depends on SPI_FLASH
help
Enable this option to support two flash memories connected to a single
controller. Currently Xilinx Zynq qspi supports this.
-if SPI_FLASH
-
config SPI_FLASH_ATMEL
bool "Atmel SPI flash support"
help
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 523e44cbba2a..2b39aaedead4 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -81,6 +81,7 @@ struct flash_info {
* to support memory size above 128Mib.
*/
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
+#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
int (*quad_enable)(struct spi_nor *nor);
@@ -1411,6 +1412,39 @@ static int spansion_read_cr_quad_enable(struct spi_nor
*nor)
return 0;
}
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
+/**
+ * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
+ * @nor: pointer to a 'struct spi_nor'
+ *
+ * Set the Quad Enable (QE) bit in the Configuration Register.
+ * This function should be used with QSPI memories not supporting the Read
+ * Configuration Register (35h) instruction.
+ *
+ * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
+ * memories.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
+{
+ u8 sr_cr[2];
+ int ret;
+
+ /* Keep the current value of the Status Register. */
+ ret = read_sr(nor);
+ if (ret < 0) {
+ dev_dbg(nor->dev, "error while reading status register\n");
+ return -EINVAL;
+ }
+ sr_cr[0] = ret;
+ sr_cr[1] = CR_QUAD_EN_SPAN;
+
+ return write_sr_cr(nor, sr_cr);
+}
+
+#endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
#endif /* CONFIG_SPI_FLASH_SPANSION */
struct spi_nor_read_command {
@@ -1500,6 +1534,573 @@ spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
pp->proto = proto;
}
+#if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
+/*
+ * Serial Flash Discoverable Parameters (SFDP) parsing.
+ */
+
+/**
+ * spi_nor_read_sfdp() - read Serial Flash Discoverable Paramete
[U-Boot] [PATCH v4 13/20] mtd: spi: sf_probe: Add "jedec, spi-nor" compatible string
Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible
SPI Flash device nodes. Therefore make U-Boot also to look for the same
compatible string so that we can use Linux DTS files as is.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Tested-by: Jagan Teki #zynq-microzed
---
drivers/mtd/spi/sf_probe.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 00f8558e7019..7a379914d8f1 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -161,6 +161,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
static const struct udevice_id spi_flash_std_ids[] = {
{ .compatible = "spi-flash" },
+ { .compatible = "jedec,spi-nor" },
{ }
};
--
2.20.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 12/20] mtd: spi: spi-nor-core: Add back U-Boot specific features
For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework
Signed-off-by: Vignesh R
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/mtd/spi/spi-nor-core.c | 162 -
include/linux/mtd/spi-nor.h| 9 ++
2 files changed, 168 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 2b39aaedead4..13c6236d623a 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -291,6 +291,7 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
+#ifndef CONFIG_SPI_FLASH_BAR
static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
{
size_t i;
@@ -365,6 +366,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
}
+#endif /* !CONFIG_SPI_FLASH_BAR */
/* Enable/disable 4-byte addressing mode. */
static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
@@ -499,6 +501,79 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
DEFAULT_READY_WAIT_JIFFIES);
}
+#ifdef CONFIG_SPI_FLASH_BAR
+/*
+ * This "clean_bar" is necessary in a situation when one was accessing
+ * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
+ *
+ * After it the BA24 bit shall be cleared to allow access to correct
+ * memory region after SW reset (by calling "reset" command).
+ *
+ * Otherwise, the BA24 bit may be left set and then after reset, the
+ * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
+ */
+static int clean_bar(struct spi_nor *nor)
+{
+ u8 cmd, bank_sel = 0;
+
+ if (nor->bank_curr == 0)
+ return 0;
+ cmd = nor->bank_write_cmd;
+ nor->bank_curr = 0;
+ write_enable(nor);
+
+ return nor->write_reg(nor, cmd, _sel, 1);
+}
+
+static int write_bar(struct spi_nor *nor, u32 offset)
+{
+ u8 cmd, bank_sel;
+ int ret;
+
+ bank_sel = offset / SZ_16M;
+ if (bank_sel == nor->bank_curr)
+ goto bar_end;
+
+ cmd = nor->bank_write_cmd;
+ write_enable(nor);
+ ret = nor->write_reg(nor, cmd, _sel, 1);
+ if (ret < 0) {
+ debug("SF: fail to write bank register\n");
+ return ret;
+ }
+
+bar_end:
+ nor->bank_curr = bank_sel;
+ return nor->bank_curr;
+}
+
+static int read_bar(struct spi_nor *nor, const struct flash_info *info)
+{
+ u8 curr_bank = 0;
+ int ret;
+
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_SPANSION:
+ nor->bank_read_cmd = SPINOR_OP_BRRD;
+ nor->bank_write_cmd = SPINOR_OP_BRWR;
+ break;
+ default:
+ nor->bank_read_cmd = SPINOR_OP_RDEAR;
+ nor->bank_write_cmd = SPINOR_OP_WREAR;
+ }
+
+ ret = nor->read_reg(nor, nor->bank_read_cmd,
+ _bank, 1);
+ if (ret) {
+ debug("SF: fail to read bank addr register\n");
+ return ret;
+ }
+ nor->bank_curr = curr_bank;
+
+ return 0;
+}
+#endif
+
/*
* Initiate the erasure of a single sector
*/
@@ -543,6 +618,11 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
len = instr->len;
while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = write_bar(nor, addr);
+ if (ret < 0)
+ return ret;
+#endif
write_enable(nor);
ret = spi_nor_erase_sector(nor, addr);
@@ -557,9 +637,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
goto erase_err;
}
+erase_err:
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(nor);
+#endif
write_disable(nor);
-erase_err:
return ret;
}
@@ -1144,8 +1227,23 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
from, size_t len,
while (len) {
loff_t addr = from;
+ size_t read_len = len;
- ret = nor->read(nor, addr, len, buf);
+#ifdef CONFIG_SPI_FLASH_BAR
+ u32 remain_len;
+
+ ret = write_bar(nor, addr);
+ if (ret < 0)
+ return log_ret(ret);
+ remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
+
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+#endif
+
+ ret = nor->read(nor, addr, read_len, buf);
if (
[U-Boot] [PATCH v4 08/20] mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/mtd/spi/spi-nor-core.c | 1716
include/linux/mtd/cfi.h| 32 +
include/linux/mtd/spi-nor.h| 410
3 files changed, 2158 insertions(+)
create mode 100644 drivers/mtd/spi/spi-nor-core.c
create mode 100644 include/linux/mtd/cfi.h
create mode 100644 include/linux/mtd/spi-nor.h
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
new file mode 100644
index ..54ef94d20f79
--- /dev/null
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -0,0 +1,1716 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Based on m25p80.c, by Mike Lavender (m...@steroidmicros.com), with
+ * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
+ *
+ * Copyright (C) 2005, Intec Automation Inc.
+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
+ *
+ * Synced from Linux v4.19
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/* Define max times to check status register before we give up. */
+
+/*
+ * For everything but full-chip erase; probably could be much smaller, but kept
+ * around for safety for now
+ */
+
+#define HZ CONFIG_SYS_HZ
+
+#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+
+#define SPI_NOR_MAX_ID_LEN 6
+#define SPI_NOR_MAX_ADDR_WIDTH 4
+
+struct flash_info {
+ char*name;
+
+ /*
+* This array stores the ID bytes.
+* The first three bytes are the JEDIC ID.
+* JEDEC ID zero means "no ID" (mostly older chips).
+*/
+ u8 id[SPI_NOR_MAX_ID_LEN];
+ u8 id_len;
+
+ /* The size listed here is what works with SPINOR_OP_SE, which isn't
+* necessarily called a "sector" by the vendor.
+*/
+ unsigned intsector_size;
+ u16 n_sectors;
+
+ u16 page_size;
+ u16 addr_width;
+
+ u16 flags;
+#define SECT_4KBIT(0) /* SPINOR_OP_BE_4K works
uniformly */
+#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
+#define SST_WRITE BIT(2) /* use SST byte programming */
+#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
+#define SECT_4K_PMCBIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly
*/
+#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
+#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
+#define USE_FSRBIT(7) /* use flag status register */
+#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
+#define SPI_NOR_HAS_TB BIT(9) /*
+* Flash SR has Top/Bottom (TB) protect
+* bit. Must be used with
+* SPI_NOR_HAS_LOCK.
+*/
+#defineSPI_S3ANBIT(10) /*
+* Xilinx Spartan 3AN In-System Flash
+* (MFR cannot be used for probing
+* because it has the same value as
+* ATMEL flashes)
+*/
+#define SPI_NOR_4B_OPCODES BIT(11) /*
+* Use dedicated 4byte address op codes
+* to support memory size above 128Mib.
+*/
+#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
+#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
+};
+
+#define JEDEC_MFR(info)((info)->id[0])
+
+static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
+{
+ return -EINVAL;
+}
+
+static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+ return -EINVAL;
+}
+
+static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
+u_char *buf)
+{
+ return -EINVAL;
+}
+
+static ssize_t spi_nor_write_data(struct spi_nor *
[U-Boot] [PATCH v4 09/20] mtd: spi: spi-nor-core: Add SPI MEM support
Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/mtd/spi/spi-nor-core.c | 97 --
1 file changed, 93 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 54ef94d20f79..66e94258b6c5 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -88,26 +88,115 @@ struct flash_info {
#define JEDEC_MFR(info)((info)->id[0])
+static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
+ *op, void *buf)
+{
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ op->data.buf.in = buf;
+ else
+ op->data.buf.out = buf;
+ return spi_mem_exec_op(nor->spi, op);
+}
+
static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
{
- return -EINVAL;
+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(len, NULL, 1));
+ int ret;
+
+ ret = spi_nor_read_write_reg(nor, , val);
+ if (ret < 0)
+ dev_dbg(>spimem->spi->dev, "error %d reading %x\n", ret,
+ code);
+
+ return ret;
}
static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
- return -EINVAL;
+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(len, NULL, 1));
+
+ return spi_nor_read_write_reg(nor, , buf);
}
static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
u_char *buf)
{
- return -EINVAL;
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
+ SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
+ SPI_MEM_OP_DATA_IN(len, buf, 1));
+ size_t remaining = len;
+ int ret;
+
+ /* get transfer protocols. */
+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
+ op.dummy.buswidth = op.addr.buswidth;
+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
+
+ /* convert the dummy cycles to the number of bytes */
+ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
+
+ while (remaining) {
+ op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
+ ret = spi_mem_adjust_op_size(nor->spi, );
+ if (ret)
+ return ret;
+
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
+
+ op.addr.val += op.data.nbytes;
+ remaining -= op.data.nbytes;
+ op.data.buf.in += op.data.nbytes;
+ }
+
+ return len;
}
static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
const u_char *buf)
{
- return -EINVAL;
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
+ SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(len, buf, 1));
+ size_t remaining = len;
+ int ret;
+
+ /* get transfer protocols. */
+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
+
+ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
+ op.addr.nbytes = 0;
+
+ while (remaining) {
+ op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
+ ret = spi_mem_adjust_op_s
[U-Boot] [PATCH v4 05/20] spi: spi-mem: Claim SPI bus before spi mem access
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/spi/spi-mem.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 334af682dc65..1bb0987edb72 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -210,6 +210,10 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
if (!spi_mem_supports_op(slave, op))
return -ENOTSUPP;
+ ret = spi_claim_bus(slave);
+ if (ret < 0)
+ return ret;
+
if (ops->mem_ops) {
#ifndef __UBOOT__
/*
@@ -232,6 +236,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
mutex_lock(>io_mutex);
#endif
ret = ops->mem_ops->exec_op(slave, op);
+
#ifndef __UBOOT__
mutex_unlock(>io_mutex);
mutex_unlock(>bus_lock_mutex);
@@ -245,8 +250,10 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
* read path) and expect the core to use the regular SPI
* interface in other cases.
*/
- if (!ret || ret != -ENOTSUPP)
+ if (!ret || ret != -ENOTSUPP) {
+ spi_release_bus(slave);
return ret;
+ }
}
#ifndef __UBOOT__
@@ -333,10 +340,6 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
op_buf = calloc(1, op_len);
- ret = spi_claim_bus(slave);
- if (ret < 0)
- return ret;
-
op_buf[pos++] = op->cmd.opcode;
if (op->addr.nbytes) {
--
2.20.1
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[U-Boot] [PATCH v4 07/20] sh: bitops: add hweight*() macros
Add hweight*() macros required for moving to new SF layer Signed-off-by: Vignesh R Reviewed-by: Jagan Teki --- arch/sh/include/asm/bitops.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index 8cb8385d76db..765f28f116bc 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -153,6 +153,10 @@ static inline int ffs (int x) } #define PLATFORM_FFS +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + #endif /* __KERNEL__ */ #endif /* __ASM_SH_BITOPS_H */ -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 06/20] spi: Add non DM version of SPI_MEM
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/spi/Kconfig| 4 +-
drivers/spi/Makefile | 1 +
drivers/spi/spi-mem-nodm.c | 105 +
3 files changed, 108 insertions(+), 2 deletions(-)
create mode 100644 drivers/spi/spi-mem-nodm.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index de4d62dd8fd1..df4c1a447842 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -16,8 +16,6 @@ config DM_SPI
typically use driver-private data instead of extending the
spi_slave structure.
-if DM_SPI
-
config SPI_MEM
bool "SPI memory extension"
help
@@ -25,6 +23,8 @@ config SPI_MEM
This extension is meant to simplify interaction with SPI memories
by providing an high-level interface to send memory-like commands.
+if DM_SPI
+
config ALTERA_SPI
bool "Altera SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4acec3ea17d7..39026712931b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
else
obj-y += spi.o
+obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
endif
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
new file mode 100644
index ..4447d4499135
--- /dev/null
+++ b/drivers/spi/spi-mem-nodm.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include
+#include
+
+int spi_mem_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ unsigned int pos = 0;
+ const u8 *tx_buf = NULL;
+ u8 *rx_buf = NULL;
+ u8 *op_buf;
+ int op_len;
+ u32 flag;
+ int ret;
+ int i;
+
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ rx_buf = op->data.buf.in;
+ else
+ tx_buf = op->data.buf.out;
+ }
+
+ op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ op_buf = calloc(1, op_len);
+
+ ret = spi_claim_bus(slave);
+ if (ret < 0)
+ return ret;
+
+ op_buf[pos++] = op->cmd.opcode;
+
+ if (op->addr.nbytes) {
+ for (i = 0; i < op->addr.nbytes; i++)
+ op_buf[pos + i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ pos += op->addr.nbytes;
+ }
+
+ if (op->dummy.nbytes)
+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+ /* 1st transfer: opcode + address + dummy cycles */
+ flag = SPI_XFER_BEGIN;
+ /* Make sure to set END bit if no tx or rx data messages follow */
+ if (!tx_buf && !rx_buf)
+ flag |= SPI_XFER_END;
+
+ ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag);
+ if (ret)
+ return ret;
+
+ /* 2nd transfer: rx or tx data path */
+ if (tx_buf || rx_buf) {
+ ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf,
+ rx_buf, SPI_XFER_END);
+ if (ret)
+ return ret;
+ }
+
+ spi_release_bus(slave);
+
+ for (i = 0; i < pos; i++)
+ debug("%02x ", op_buf[i]);
+ debug("| [%dB %s] ",
+ tx_buf || rx_buf ? op->data.nbytes : 0,
+ tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-");
+ for (i = 0; i < op->data.nbytes; i++)
+ debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
+ debug("[ret %d]\n", ret);
+
+ free(op_buf);
+
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int spi_mem_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ unsigned int len;
+
+ len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ if (slave->max_write_size && len > slave->max_write_size)
+ return -EINVAL;
+
+ if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_read_size);
+ else if (slave->max_write_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_write_size - len);
+
+ if (!op->data.nbytes)
+ return -EINVAL;
+
+ return 0;
+}
--
2.20.1
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[U-Boot] [PATCH v4 04/20] spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size
Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/spi/spi-mem.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 1da20b8de5c4..334af682dc65 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -412,6 +412,25 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct
spi_mem_op *op)
if (ops->mem_ops && ops->mem_ops->adjust_op_size)
return ops->mem_ops->adjust_op_size(slave, op);
+ if (!ops->mem_ops || !ops->mem_ops->exec_op) {
+ unsigned int len;
+
+ len = sizeof(op->cmd.opcode) + op->addr.nbytes +
+ op->dummy.nbytes;
+ if (slave->max_write_size && len > slave->max_write_size)
+ return -EINVAL;
+
+ if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_read_size);
+ else if (slave->max_write_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_write_size - len);
+
+ if (!op->data.nbytes)
+ return -EINVAL;
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
--
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[U-Boot] [PATCH v4 02/20] bitops: Fix GENMASK definition for Sandbox
In arch/sandbox/include/asm/types.h we have Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as CONFIG_PHYS64 is not set This messes up the current logic of GENMASK macro due to mismatch b/w size of unsigned long (64 bit) and that of BITS_PER_LONG. Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32 based on the host machine on which its being compiled. Without this patch: GENMASK(14,0) => 0x7fff After this patch: GENMASK(14,0) => 0x7fff Signed-off-by: Vignesh R Reviewed-by: Simon Glass --- Note: this patch is merged to u-boot-dm.git at: http://git.denx.de/?p=u-boot/u-boot-dm.git;a=commitdiff;h=aba05dfb5dc673606477b4510320e95fd577d9b6 But, is not part of u-boot/master yet. Patch is required for Sandbox tests to pass once this series is merged. include/linux/bitops.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index a47f6d17bb5f..259df43fb00f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -21,8 +21,13 @@ * position @h. For example * GENMASK_ULL(39, 21) gives us the 64bit vector 0x00e0. */ +#ifdef CONFIG_SANDBOX +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (CONFIG_SANDBOX_BITS_PER_LONG - 1 - (h +#else #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h +#endif #define GENMASK_ULL(h, l) \ (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 03/20] spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes
SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
---
drivers/spi/spi-mem.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index af9aef009a73..1da20b8de5c4 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -323,15 +323,6 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
return -EIO;
#else
- /* U-Boot does not support parallel SPI data lanes */
- if ((op->cmd.buswidth != 1) ||
- (op->addr.nbytes && op->addr.buswidth != 1) ||
- (op->dummy.nbytes && op->dummy.buswidth != 1) ||
- (op->data.nbytes && op->data.buswidth != 1)) {
- printf("Dual/Quad raw SPI transfers not supported\n");
- return -ENOTSUPP;
- }
-
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN)
rx_buf = op->data.buf.in;
--
2.20.1
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[U-Boot] [PATCH v4 01/20] configs: Move CONFIG_SPI_FLASH into defconfigs
Completely move CONFIG_SPI_FLASH from remaining board header files to defconfigs Signed-off-by: Vignesh R Reviewed-by: Jagan Teki Tested-by: Jagan Teki #zynq-microzed --- configs/cgtqmx6eval_defconfig| 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/evb-rk3036_defconfig | 1 + configs/evb-rk3128_defconfig | 1 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/fennec-rk3288_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig| 1 + configs/ls2080aqds_qspi_defconfig| 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/miqi-rk3288_defconfig| 1 + configs/phycore-rk3288_defconfig | 1 + configs/popmetal-rk3288_defconfig| 1 + configs/rock2_defconfig | 1 + configs/rock_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + configs/turris_omnia_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + include/configs/cgtqmx6eval.h| 1 - include/configs/ls2080aqds.h | 2 -- include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/turris_omnia.h | 1 - 32 files changed, 24 insertions(+), 9 deletions(-) diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index 80bff7dc2092..99c581b2de95 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -55,6 +55,7 @@ CONFIG_DFU_SF=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x1200 CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_SPI=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index fd4cd806e6bd..3ad4d7da0749 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -59,6 +59,7 @@ CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 88a37c5d82c0..0ce5ac54dc2f 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -64,6 +64,7 @@ CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 2e17e73ded6d..4e7feffefd34 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -60,6 +60,7 @@ CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 439e69138636..33eaa062f5b8 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y # CONFIG_SPL_DM_SERIAL is not set diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index 78c5ac6f530b..d2c0fb0aae37 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -29,6 +29,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 671bb8ca3c30..d0eba8a1a077 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -52,6 +52,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 10a5f09b313a..ad675173b61a 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -32,6 +32,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 25baf4cbbd1a..4e0898d81864 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig
[U-Boot] [PATCH v4 00/20] SF: Migrate to Linux SPI NOR framework
Here is the v4 of SPI NOR migration(github branch at [1]) with minor cleanups Travis ci report: https://travis-ci.org/r-vignesh/u-boot/builds/488868207 Change log: Since v3: Rebase on to the latest u-boot/master Drop MODULE_LICENSE, EXPORT_SYMBOL_GPL macros Make SPI_FLASH_BAR default for ZYNQ_QSPI as suggested by Jagan. Since v2: Split sync up patches into smaller versions so that its easier for review. Address comments by Jagan and Simon Goldschmidt on v2. Make SPI_FLASH_TINY(read only SF stack) as default for SPL build to offset against size increase due to new code. Since v1: Remove #ifindef __UBOOT__ Add back BAR support, but dont enable as default for all platform (see 10/11 for more details) Enable SPI_FLASH_TINY on boards where there is SPL size constraint as seen on travis ci builds. Drop sf_mtd changes for now as it seems to cause issues. v1: https://patchwork.ozlabs.org/cover/1012146/ Since RFC v2: Fix issues reported by Simon Goldschmidt wrt 4 use of byte addressing opcode Fix issues in compiling SFDP code Re organize file names and Makefile to simply spi-nor-tiny inclusion Remove SPI_FLASH_BAR and SF_DUAL_FLASH as these are no longer used RFC v2: https://patchwork.ozlabs.org/cover/1007589/ Since RFC v1: Add lightweight SPI flash stack for boards with SPL size constraints Provide non DM version of spi-mem Fix build issues on different platforms as reported by travis-ci on v1 RFC v1: https://patchwork.ozlabs.org/cover/1004689/ Background: U-Boot SPI NOR support (sf layer) is quite outdated as it does not support 4 byte addressing opcodes, SFDP table parsing and different types of quad mode enable sequences. Many newer flashes no longer support BANK registers used by sf layer to a access >16MB space. Also, many SPI controllers have special MMIO interfaces which provide accelerated read/write access but require knowledge of flash parameters to make use of it. Recent spi-mem layer provides a way to support such flashes but sf layer isn't using that. This patch series syncs SPI NOR framework from Linux v4.19. It also adds spi-mem support on top. So, we gain 4byte addressing support and SFDP support. This makes migrating to U-Boot MTD framework easier. Tested with few Spansion, micron and macronix flashes with TI's dra7xx, k2g, am43xx EVMs. I dont have access to flashes from other vendors. So, I would greatly appreciate testing on other platforms. Complete series with dependencies here[1] [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v4 Vignesh R (20): configs: Move CONFIG_SPI_FLASH into defconfigs bitops: Fix GENMASK definition for Sandbox spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size spi: spi-mem: Claim SPI bus before spi mem access spi: Add non DM version of SPI_MEM sh: bitops: add hweight*() macros mtd: spi: Port SPI NOR framework from Linux mtd: spi: spi-nor-core: Add SPI MEM support mtd: spi: spi-nor-core: Add 4 Byte addressing support mtd: spi: spi-nor-core: Add SFDP support mtd: spi: spi-nor-core: Add back U-Boot specific features mtd: spi: sf_probe: Add "jedec,spi-nor" compatible string mtd: spi: Switch to new SPI NOR framework mtd: spi: Remove unused files mtd: spi: Add lightweight SPI flash stack for SPL spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL configs: Remove SF_DUAL_FLASH configs: Don't use SPI_FLASH_BAR as default MAINTAINERS: Add an entry for SPI NOR MAINTAINERS |9 + arch/arm/mach-omap2/am33xx/Kconfig|1 - arch/sh/include/asm/bitops.h |4 + common/spl/Kconfig| 23 +- configs/alt_defconfig |1 - configs/am57xx_evm_defconfig |1 - configs/am57xx_hs_evm_defconfig |1 - configs/ap121_defconfig |1 - configs/ap143_defconfig |1 - configs/avnet_ultra96_rev1_defconfig |1 - configs/axs101_defconfig |1 - configs/axs103_defconfig |1 - configs/bg0900_defconfig |1 - configs/blanche_defconfig |1 - configs/cgtqmx6eval_defconfig |1 + configs/chromebit_mickey_defconfig|1 + configs/chromebook_jerry_defconfig|1 + configs/chromebook_minnie_defconfig |1 + configs/cl-som-am57x_defconfig|1 - configs/clearfog_defconfig|1 - configs/cm_t43_defconfig |1 - configs/db-88f6820-amc_defconfig |1 - configs/display5_defconfig|1 - configs/display5_factory_defconfig|1 - configs/dra7xx_evm_defconfig |1 - configs/dra7xx_hs_evm_defconfig |1 - configs/ds
Re: [U-Boot] [PATCH v3 19/20] configs: Don't use SPI_FLASH_BAR as default
[...] >>> Yes, zynq qspi ia unable to handle larger than 16MiB flashes so we used >>> BAR to access those. >>> >> >> I wonder how those boards work in kernel that does not support BAR. >> Anyways, if you provide a list of SPI controllers on zynq SoCs, I will >> add an imply SPI_FLASH_BAR for such Kconfigs and send a separate patch. > > for zynq_qspi driver used boards yes and other you can proceed at this moment. > You mean config ZYNQ_QSPI and config ZYNQMP_GQSPI need BAR support? I will send a follow up patch on top of this series ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 16/20] mtd: spi: Add lightweight SPI flash stack for SPL
On 01-Feb-19 9:18 PM, Jagan Teki wrote: > On Thu, Jan 31, 2019 at 11:20 PM Vignesh R wrote: >> [...] >>> >>> This doesn't look good to me, this change is part of 08/20 and now it >>> removed. better do the same change in 08/20 by adding new file >>> spi-nor-ids.c >>> >> >> This is intentional. Patch 8-11 clearly shows what all is being sync'd >> from Kernel and I would like to keep that as is. >> Merging U-Boot specific changes with those patches does not provide a >> clean history >> spi-nor-ids table is moved out of spi-nor-core.c in this patch because >> we need it for two separate compilation units (spi-nor-tiny and >> spi-nor-core). > > Understand this point, but since it's not a direct commit sync and we > even add changes wrt u-boot and remove unneeded changes related to > Linux. This is a direct sync. I removed code not related to U-Boot on your insistence. But, code organization is same as Linux. I had no intention of splitting ID table into a separate file (see RFC v1 where it was still in the original file) as there was no other user of ID table and keeping table in same file allows compiler to carry out compile time optimizations. It's fine to create -ids.c file in the same commit, otherwise > it is simply adding code and removing the same in following commit > doesn't suit for bisectable. > Sorry, I do not agree on this.. This patch clearly captures the _need_ to move ID table out of spi-nor-core.c. Code is being moved out of spi-nor-core.c to _support_ tiny stack. At no point in this series bisectablility is broken. Redoing patch 8/20 is non trivial and would be painful rework with no gain. I will have to rework patch 8/20 and 14/20 so as to not break compilation. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/20] SF: Migrate to Linux SPI NOR framework
On 31/01/19 8:15 PM, Jagan Teki wrote: > On Thu, Jan 31, 2019 at 8:12 PM Tom Rini wrote: >> >> On Thu, Jan 31, 2019 at 08:10:53PM +0530, Jagan Teki wrote: >>> On Tue, Jan 29, 2019 at 11:19 AM Vignesh R wrote: >>>> >>>> Here is the v3 of SPI NOR migration(github branch at [1]). I have >>>> retained Tested-by from v2 as this is just re split of patches and >>>> minor fixups. >>>> >>>> Travis ci reports all green. >>>> >>>> Change log: >>>> Since v2: >>>> Split sync up patches into smaller versions so that its easier for review. >>>> Address comments by Jagan and Simon Goldschmidt on v2. >>>> Make SPI_FLASH_TINY(read only SF stack) as default for SPL build to >>>> offset against size increase due to new code. >>>> >>>> Since v1: >>>> Remove #ifindef __UBOOT__ >>>> Add back BAR support, but dont enable as default for all platform (see >>>> 10/11 for more details) >>>> Enable SPI_FLASH_TINY on boards where there is SPL size constraint as >>>> seen on travis ci builds. >>>> Drop sf_mtd changes for now as it seems to cause issues. >>>> v1: https://patchwork.ozlabs.org/cover/1012146/ >>>> >>>> Since RFC v2: >>>> Fix issues reported by Simon Goldschmidt wrt 4 use of byte addressing >>>> opcode >>>> Fix issues in compiling SFDP code >>>> Re organize file names and Makefile to simply spi-nor-tiny inclusion >>>> Remove SPI_FLASH_BAR and SF_DUAL_FLASH as these are no longer used >>>> RFC v2: https://patchwork.ozlabs.org/cover/1007589/ >>>> >>>> Since RFC v1: >>>> Add lightweight SPI flash stack for boards with SPL size constraints >>>> Provide non DM version of spi-mem >>>> Fix build issues on different platforms as reported by travis-ci on v1 >>>> >>>> RFC v1: https://patchwork.ozlabs.org/cover/1004689/ >>>> >>>> Background: >>>> >>>> U-Boot SPI NOR support (sf layer) is quite outdated as it does not >>>> support 4 byte addressing opcodes, SFDP table parsing and different types >>>> of >>>> quad mode enable sequences. Many newer flashes no longer support BANK >>>> registers used by sf layer to a access >16MB space. >>>> Also, many SPI controllers have special MMIO interfaces which provide >>>> accelerated read/write access but require knowledge of flash parameters >>>> to make use of it. Recent spi-mem layer provides a way to support such >>>> flashes but sf layer isn't using that. >>>> This patch series syncs SPI NOR framework from Linux v4.19. It also adds >>>> spi-mem support on top. >>>> So, we gain 4byte addressing support and SFDP support. This makes >>>> migrating to U-Boot MTD framework easier. >>>> >>>> Tested with few Spansion, micron and macronix flashes with TI's dra7xx, >>>> k2g, am43xx EVMs. I dont have access to flashes from other vendors. So, >>>> I would greatly appreciate testing on other platforms. Complete series >>>> with dependencies here[1] >>>> >>>> For clean build on some platforms, depends on CONFIG_SPI_FLASH migration >>>> to defconfigs [2] >>>> >>>> [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v3 >>>> [2] https://patchwork.ozlabs.org/patch/1007485/ >>>> >>>> Vignesh R (20): >>>> configs: Move CONFIG_SPI_FLASH into defconfigs >>>> bitops: Fix GENMASK definition for Sandbox >>>> spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes >>>> spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size >>>> spi: spi-mem: Claim SPI bus before spi mem access >>>> spi: Add non DM version of SPI_MEM >>>> sh: bitops: add hweight*() macros >>>> mtd: spi: Port SPI NOR framework from Linux >>>> mtd: spi: spi-nor-core: Add SPI MEM support >>>> mtd: spi: spi-nor-core: Add 4 Byte addressing support >>>> mtd: spi: spi-nor-core: Add SFDP support >>>> mtd: spi: spi-nor-core: Add back U-Boot specific features >>>> mtd: spi: sf_probe: Add "jedec,spi-nor" compatible string >>>> mtd: spi: Switch to new SPI NOR framework >>>> mtd: spi: Remove unused files >>>> mtd: spi: Add lightweight SPI flash stack for SPL >>>> spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL >>>> configs: Remove SF_DUAL_FLASH >>>> configs: Don't use SPI_FLASH_BAR as default >>>> MAINTAINERS: Add an entry for SPI NOR >>> >>> Except 16/20 and 19/20, all look fine to me. >>> >>> Reviewed-by: Jagan Teki >>> Tested-by: Jagan Teki #zynq-microzed Thanks for all the reviews! >> >> And based on the Xilinx folks reply to 19/20, is 16/20 something we can >> deal with as a follow-up? Thanks! > > 19/20, can (If some don't believe me) and 16/20 can be fixed here. > I have replied to individual patches. In summary, 19/20 can be fixed as a follow up patch if Zynq SoCs cant really support 4 byte addressing. I will send a follow up patch to remove MODULE_LICENSE(), EXPORT_SYMBOL_GPL() macros. I dont plan to respin unless there are more objections -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 16/20] mtd: spi: Add lightweight SPI flash stack for SPL
On 31/01/19 5:36 PM, Jagan Teki wrote:
> On Tue, Jan 29, 2019 at 11:29 AM Vignesh R wrote:
>>
>> Add a tiny SPI flash stack that just supports reading data/images from
>> SPI flash. This is useful for boards that have SPL size constraints and
>> would need to use SPI flash framework just to read images/data from
>> flash. There is approximately 1.5 to 2KB savings with this.
>>
>> Based on prior work of reducing spi flash id table by
>> Simon Goldschmidt
>>
>> Signed-off-by: Vignesh R
>> Tested-by: Simon Goldschmidt
>> Tested-by: Stefan Roese
>> Tested-by: Horatiu Vultur
>> ---
>> common/spl/Kconfig | 11 +-
>> drivers/mtd/spi/Makefile | 10 +-
>> drivers/mtd/spi/sf_internal.h | 2 +
>> drivers/mtd/spi/spi-nor-core.c | 266 +--
>> drivers/mtd/spi/spi-nor-ids.c | 297
>> drivers/mtd/spi/spi-nor-tiny.c | 810 +
>> 6 files changed, 1132 insertions(+), 264 deletions(-)
>> create mode 100644 drivers/mtd/spi/spi-nor-ids.c
>> create mode 100644 drivers/mtd/spi/spi-nor-tiny.c
>>
>> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
>> index 2e1dd2705a62..416f5933b0d9 100644
>> --- a/common/spl/Kconfig
>> +++ b/common/spl/Kconfig
>> @@ -732,9 +732,18 @@ config SPL_SPI_FLASH_SUPPORT
>>
>> if SPL_SPI_FLASH_SUPPORT
>>
>> +config SPL_SPI_FLASH_TINY
>> + bool "Enable low footprint SPL SPI Flash support"
>> + depends on !SPI_FLASH_BAR
>> + help
>> +Enable lightweight SPL SPI Flash support that supports just reading
>> +data/images from flash. No support to write/erase flash. Enable
>> +this if you have SPL size limitations and don't need full
>> +fledged SPI flash support.
>> +
>> config SPL_SPI_FLASH_SFDP_SUPPORT
>> bool "SFDP table parsing support for SPI NOR flashes"
>> - depends on !SPI_FLASH_BAR
>> + depends on !SPI_FLASH_BAR && !SPL_SPI_FLASH_TINY
>> help
>> Enable support for parsing and auto discovery of parameters for
>> SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
>> diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
>> index 70058d3df2b9..f99f6cb16e29 100644
>> --- a/drivers/mtd/spi/Makefile
>> +++ b/drivers/mtd/spi/Makefile
>> @@ -4,12 +4,20 @@
>> # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
>>
>> obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
>> +spi-nor-y := sf_probe.o spi-nor-ids.o
>>
>> ifdef CONFIG_SPL_BUILD
>> obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
>> +ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y)
>> +spi-nor-y += spi-nor-tiny.o
>> +else
>> +spi-nor-y += spi-nor-core.o
>> +endif
>> +else
>> +spi-nor-y += spi-nor-core.o
>> endif
>>
>> -obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
>> +obj-$(CONFIG_SPI_FLASH) += spi-nor.o
>> obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
>> obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
>> obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
>> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
>> index fd00e0d1b23b..a6bf734830a7 100644
>> --- a/drivers/mtd/spi/sf_internal.h
>> +++ b/drivers/mtd/spi/sf_internal.h
>> @@ -16,7 +16,9 @@
>> #define SPI_NOR_MAX_ADDR_WIDTH 4
>>
>> struct flash_info {
>> +#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
>> char*name;
>> +#endif
>>
>> /*
>> * This array stores the ID bytes.
>> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
>> index dbaaf45c7e1e..80633f8fd070 100644
>> --- a/drivers/mtd/spi/spi-nor-core.c
>> +++ b/drivers/mtd/spi/spi-nor-core.c
>> @@ -879,284 +879,26 @@ static int stm_is_locked(struct spi_nor *nor, loff_t
>> ofs, uint64_t len)
>> }
>> #endif /* CONFIG_SPI_FLASH_STMICRO */
>>
>> -/* Used when the "_ext_id" is two bytes at most */
>> -#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
>> - .id = { \
>> - ((_jedec_id) >> 16) & 0xff, \
>> - ((_jedec_id) >> 8) & 0xff, \
>> - (_jedec_id) & 0xff, \
>> - ((_ext_id) >> 8) & 0xff,\
>> -
Re: [U-Boot] [PATCH v3 19/20] configs: Don't use SPI_FLASH_BAR as default
On 31/01/19 7:20 PM, Jagan Teki wrote: > On Thu, 31 Jan, 2019, 7:16 PM Vignesh R <mailto:vigne...@ti.com> wrote: > > On 31/01/19 7:06 PM, Jagan Teki wrote: > [...] > > >> configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - > > >> configs/zynq_cc108_defconfig | 1 - > > >> configs/zynq_cse_qspi_defconfig | 1 - > > >> configs/zynq_dlc20_rev1_0_defconfig | 1 - > > >> configs/zynq_microzed_defconfig | 1 - > > >> configs/zynq_minized_defconfig | 1 - > > >> configs/zynq_z_turn_defconfig | 1 - > > >> configs/zynq_zc702_defconfig | 1 - > > >> configs/zynq_zc706_defconfig | 1 - > > >> configs/zynq_zc770_xm010_defconfig | 1 - > > >> configs/zynq_zc770_xm013_defconfig | 1 - > > >> configs/zynq_zed_defconfig | 1 - > > >> configs/zynq_zybo_defconfig | 1 - > > >> configs/zynq_zybo_z7_defconfig | 1 - > > > > > > zynq targets do need BAR, same has commented in previous mails. > > > > Hmmm, Is this a limitation of SPI controller on the SoC or > flash on the > > board? > > AFAICS, zynq_spi.c, zynq_qspi.c zynq_spi.c zynqmp_gqspi.c are > all FIFO > > based SPI controllers and ideally should not care about > address length. > > Could you please explain why BAR is a requirement on these > platforms? > > > > Were you able to test this series on any of those platforms? > > > > > > Go back to the log history, initial intension for adding BAR was > on zynq. > > > > > Sorry, this is all I could find from mailing list (original series by > you that adds BAR support): > https://lists.denx.de/pipermail/u-boot/2013-June/157006.html > > There is nothing that mentions why Zynq platforms need BAR support and > cannot use 4 byte opcodes to access >16MB space? > > > Yes, zynq qspi ia unable to handle larger than 16MiB flashes so we used > BAR to access those. > I wonder how those boards work in kernel that does not support BAR. Anyways, if you provide a list of SPI controllers on zynq SoCs, I will add an imply SPI_FLASH_BAR for such Kconfigs and send a separate patch. > Michal, Siva: can you confirm? > > -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 19/20] configs: Don't use SPI_FLASH_BAR as default
On 31/01/19 7:06 PM, Jagan Teki wrote: [...] > >> configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - > >> configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - > >> configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - > >> configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - > >> configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - > >> configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - > >> configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - > >> configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - > >> configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - > >> configs/zynq_cc108_defconfig | 1 - > >> configs/zynq_cse_qspi_defconfig | 1 - > >> configs/zynq_dlc20_rev1_0_defconfig | 1 - > >> configs/zynq_microzed_defconfig | 1 - > >> configs/zynq_minized_defconfig | 1 - > >> configs/zynq_z_turn_defconfig | 1 - > >> configs/zynq_zc702_defconfig | 1 - > >> configs/zynq_zc706_defconfig | 1 - > >> configs/zynq_zc770_xm010_defconfig | 1 - > >> configs/zynq_zc770_xm013_defconfig | 1 - > >> configs/zynq_zed_defconfig | 1 - > >> configs/zynq_zybo_defconfig | 1 - > >> configs/zynq_zybo_z7_defconfig | 1 - > > > > zynq targets do need BAR, same has commented in previous mails. > > Hmmm, Is this a limitation of SPI controller on the SoC or flash on the > board? > AFAICS, zynq_spi.c, zynq_qspi.c zynq_spi.c zynqmp_gqspi.c are all FIFO > based SPI controllers and ideally should not care about address length. > Could you please explain why BAR is a requirement on these platforms? > > Were you able to test this series on any of those platforms? > > > Go back to the log history, initial intension for adding BAR was on zynq. > Sorry, this is all I could find from mailing list (original series by you that adds BAR support): https://lists.denx.de/pipermail/u-boot/2013-June/157006.html There is nothing that mentions why Zynq platforms need BAR support and cannot use 4 byte opcodes to access >16MB space? -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 02/20] bitops: Fix GENMASK definition for Sandbox
On 31/01/19 6:11 AM, Simon Glass wrote: > On Mon, 28 Jan 2019 at 22:49, Vignesh R wrote: >> >> In arch/sandbox/include/asm/types.h we have >> Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as >> CONFIG_PHYS64 is not set >> >> This messes up the current logic of GENMASK macro due to mismatch b/w >> size of unsigned long (64 bit) and that of BITS_PER_LONG. >> Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32 >> based on the host machine on which its being compiled. >> >> Without this patch: >> GENMASK(14,0) => 0x7fffffff >> After this patch: >> GENMASK(14,0) => 0x7fff >> >> Signed-off-by: Vignesh R >> --- >> include/linux/bitops.h | 5 + >> 1 file changed, 5 insertions(+) > > Reviewed-by: Simon Glass > I realised this patch is already merged to u-boot-dm when I posted it as an RFC. Please ignore. Thanks! -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 19/20] configs: Don't use SPI_FLASH_BAR as default
On 31/01/19 6:48 PM, Jagan Teki wrote: > On Tue, Jan 29, 2019 at 11:28 AM Vignesh R wrote: >> >> Now that new SPI NOR layer uses stateless 4 byte opcodes by default, >> don't enable SPI_FLASH_BAR. For SPI controllers that cannot support >> 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, >> renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to >> not break functionality. >> >> Signed-off-by: Vignesh R >> Tested-by: Simon Goldschmidt >> Tested-by: Stefan Roese >> Tested-by: Horatiu Vultur >> --- >> arch/arm/mach-omap2/am33xx/Kconfig | 1 - >> configs/alt_defconfig| 1 - >> configs/am57xx_evm_defconfig | 1 - >> configs/am57xx_hs_evm_defconfig | 1 - >> configs/ap121_defconfig | 1 - >> configs/ap143_defconfig | 1 - >> configs/avnet_ultra96_rev1_defconfig | 1 - >> configs/axs101_defconfig | 1 - >> configs/axs103_defconfig | 1 - >> configs/bg0900_defconfig | 1 - >> configs/blanche_defconfig| 1 - >> configs/cl-som-am57x_defconfig | 1 - >> configs/clearfog_defconfig | 1 - >> configs/cm_t43_defconfig | 1 - >> configs/db-88f6820-amc_defconfig | 1 - >> configs/display5_defconfig | 1 - >> configs/display5_factory_defconfig | 1 - >> configs/dra7xx_evm_defconfig | 1 - >> configs/dra7xx_hs_evm_defconfig | 1 - >> configs/ds109_defconfig | 1 - >> configs/ds414_defconfig | 1 - >> configs/evb-rv1108_defconfig | 1 - >> configs/gose_defconfig | 1 - >> configs/helios4_defconfig| 1 - >> configs/k2g_evm_defconfig| 1 - >> configs/k2g_hs_evm_defconfig | 1 - >> configs/koelsch_defconfig| 1 - >> configs/lager_defconfig | 1 - >> configs/maxbcm_defconfig | 1 - >> configs/mt7629_rfb_defconfig | 1 - >> configs/mx6sxsabreauto_defconfig | 1 - >> configs/mx6sxsabresd_defconfig | 1 - >> configs/mx6ul_14x14_evk_defconfig| 1 - >> configs/mx6ul_9x9_evk_defconfig | 1 - >> configs/mx6ull_14x14_evk_defconfig | 1 - >> configs/mx6ull_14x14_evk_plugin_defconfig| 1 - >> configs/mx7dsabresd_qspi_defconfig | 1 - >> configs/porter_defconfig | 1 - >> configs/r8a77970_eagle_defconfig | 1 - >> configs/silk_defconfig | 1 - >> configs/socfpga_arria5_defconfig | 1 - >> configs/socfpga_cyclone5_defconfig | 1 - >> configs/socfpga_is1_defconfig| 1 - >> configs/socfpga_sockit_defconfig | 1 - >> configs/socfpga_socrates_defconfig | 1 - >> configs/socfpga_sr1500_defconfig | 1 - >> configs/socfpga_stratix10_defconfig | 1 - >> configs/stout_defconfig | 1 - >> configs/topic_miami_defconfig| 1 - >> configs/topic_miamilite_defconfig| 1 - >> configs/topic_miamiplus_defconfig| 1 - >> configs/xilinx_versal_virt_defconfig | 1 - >> configs/xilinx_zynqmp_mini_qspi_defconfig| 1 - >> configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - >> configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - >> configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - >> configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - >> configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - >> configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 - >> configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - >> configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - >> configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - >> configs/xilinx_zy
Re: [U-Boot] [PATCH v3 14/20] mtd: spi: Switch to new SPI NOR framework
On 31/01/19 6:09 PM, Jagan Teki wrote: > On Thu, Jan 31, 2019 at 6:08 PM Vignesh R wrote: >> >> >> >> On 31/01/19 5:53 PM, Jagan Teki wrote: >>> On Tue, Jan 29, 2019 at 11:28 AM Vignesh R wrote: >>>> >>>> Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD >>>> layer. Fix up sf_dataflash to work in legacy way. And update sandbox to >>>> use new interfaces/definitions >>>> >>>> Signed-off-by: Vignesh R >>>> Tested-by: Simon Goldschmidt >>>> Tested-by: Stefan Roese >>>> Tested-by: Horatiu Vultur >>>> --- >>>> drivers/mtd/spi/Kconfig| 2 + >>>> drivers/mtd/spi/Makefile | 4 +- >>>> drivers/mtd/spi/sandbox.c | 36 +++--- >>> >>> Is this sanbox changes tested? >>> >> >> Here is the travis ci test pass: >> https://travis-ci.org/r-vignesh/u-boot/builds/485749118 >> >> I believe that covers sandbox test as well > > I'm referring about dm tests that run on sandbox[1] > > [1] http://www.openedev.com/wiki/U-Boot#Sandbox > https://travis-ci.org/r-vignesh/u-boot/jobs/485749177 Job #35.59 Just ran it locally: https://pastebin.ubuntu.com/p/hgbf2Nsryn/ All is well. -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 14/20] mtd: spi: Switch to new SPI NOR framework
On 31/01/19 5:53 PM, Jagan Teki wrote: > On Tue, Jan 29, 2019 at 11:28 AM Vignesh R wrote: >> >> Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD >> layer. Fix up sf_dataflash to work in legacy way. And update sandbox to >> use new interfaces/definitions >> >> Signed-off-by: Vignesh R >> Tested-by: Simon Goldschmidt >> Tested-by: Stefan Roese >> Tested-by: Horatiu Vultur >> --- >> drivers/mtd/spi/Kconfig| 2 + >> drivers/mtd/spi/Makefile | 4 +- >> drivers/mtd/spi/sandbox.c | 36 +++--- > > Is this sanbox changes tested? > Here is the travis ci test pass: https://travis-ci.org/r-vignesh/u-boot/builds/485749118 I believe that covers sandbox test as well -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/20] SF: Migrate to Linux SPI NOR framework
On 29/01/19 1:45 PM, Simon Goldschmidt wrote: > On Tue, Jan 29, 2019 at 6:49 AM Vignesh R wrote: >> >> Here is the v3 of SPI NOR migration(github branch at [1]). I have >> retained Tested-by from v2 as this is just re split of patches and >> minor fixups. > > So re-testing is not necessary? > There is no change in the code as such apart from minor fixup. But any sanity test is welcome! BTW, I have enabled SPI_FLASH_TINY as default like you suggested. > Regards, > Simon > >> >> Travis ci reports all green. >> >> Change log: >> Since v2: >> Split sync up patches into smaller versions so that its easier for review. >> Address comments by Jagan and Simon Goldschmidt on v2. >> Make SPI_FLASH_TINY(read only SF stack) as default for SPL build to >> offset against size increase due to new code. >> >> Since v1: >> Remove #ifindef __UBOOT__ >> Add back BAR support, but dont enable as default for all platform (see >> 10/11 for more details) >> Enable SPI_FLASH_TINY on boards where there is SPL size constraint as >> seen on travis ci builds. >> Drop sf_mtd changes for now as it seems to cause issues. >> v1: https://patchwork.ozlabs.org/cover/1012146/ >> >> Since RFC v2: >> Fix issues reported by Simon Goldschmidt wrt 4 use of byte addressing opcode >> Fix issues in compiling SFDP code >> Re organize file names and Makefile to simply spi-nor-tiny inclusion >> Remove SPI_FLASH_BAR and SF_DUAL_FLASH as these are no longer used >> RFC v2: https://patchwork.ozlabs.org/cover/1007589/ >> >> Since RFC v1: >> Add lightweight SPI flash stack for boards with SPL size constraints >> Provide non DM version of spi-mem >> Fix build issues on different platforms as reported by travis-ci on v1 >> >> RFC v1: https://patchwork.ozlabs.org/cover/1004689/ >> >> Background: >> >> U-Boot SPI NOR support (sf layer) is quite outdated as it does not >> support 4 byte addressing opcodes, SFDP table parsing and different types of >> quad mode enable sequences. Many newer flashes no longer support BANK >> registers used by sf layer to a access >16MB space. >> Also, many SPI controllers have special MMIO interfaces which provide >> accelerated read/write access but require knowledge of flash parameters >> to make use of it. Recent spi-mem layer provides a way to support such >> flashes but sf layer isn't using that. >> This patch series syncs SPI NOR framework from Linux v4.19. It also adds >> spi-mem support on top. >> So, we gain 4byte addressing support and SFDP support. This makes >> migrating to U-Boot MTD framework easier. >> >> Tested with few Spansion, micron and macronix flashes with TI's dra7xx, >> k2g, am43xx EVMs. I dont have access to flashes from other vendors. So, >> I would greatly appreciate testing on other platforms. Complete series >> with dependencies here[1] >> >> For clean build on some platforms, depends on CONFIG_SPI_FLASH migration >> to defconfigs [2] >> >> [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v3 >> [2] https://patchwork.ozlabs.org/patch/1007485/ >> >> Vignesh R (20): >> configs: Move CONFIG_SPI_FLASH into defconfigs >> bitops: Fix GENMASK definition for Sandbox >> spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes >> spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size >> spi: spi-mem: Claim SPI bus before spi mem access >> spi: Add non DM version of SPI_MEM >> sh: bitops: add hweight*() macros >> mtd: spi: Port SPI NOR framework from Linux >> mtd: spi: spi-nor-core: Add SPI MEM support >> mtd: spi: spi-nor-core: Add 4 Byte addressing support >> mtd: spi: spi-nor-core: Add SFDP support >> mtd: spi: spi-nor-core: Add back U-Boot specific features >> mtd: spi: sf_probe: Add "jedec,spi-nor" compatible string >> mtd: spi: Switch to new SPI NOR framework >> mtd: spi: Remove unused files >> mtd: spi: Add lightweight SPI flash stack for SPL >> spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL >> configs: Remove SF_DUAL_FLASH >> configs: Don't use SPI_FLASH_BAR as default >> MAINTAINERS: Add an entry for SPI NOR >> >> MAINTAINERS |9 + >> arch/arm/mach-omap2/am33xx/Kconfig|1 - >> arch/sh/include/asm/bitops.h |4 + >> common/spl/Kconfig| 23 +- >> configs/alt_defconfig |1 - >> configs/am57xx_ev
[U-Boot] [PATCH v3 2/7] soc: ti: k3: add navss ringacc driver
From: Grygorii Strashko The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh R --- drivers/Kconfig |2 + drivers/soc/Kconfig |5 + drivers/soc/Makefile|1 + drivers/soc/ti/Kconfig | 20 + drivers/soc/ti/Makefile |5 + drivers/soc/ti/k3-navss-ringacc.c | 1096 +++ include/linux/soc/ti/k3-navss-ringacc.h | 246 + 7 files changed, 1375 insertions(+) create mode 100644 drivers/soc/Kconfig create mode 100644 drivers/soc/ti/Kconfig create mode 100644 drivers/soc/ti/Makefile create mode 100644 drivers/soc/ti/k3-navss-ringacc.c create mode 100644 include/linux/soc/ti/k3-navss-ringacc.h diff --git a/drivers/Kconfig b/drivers/Kconfig index e9fbadd13d5a..1eedb3462b0a 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -96,6 +96,8 @@ source "drivers/smem/Kconfig" source "drivers/sound/Kconfig" +source "drivers/soc/Kconfig" + source "drivers/spi/Kconfig" source "drivers/spmi/Kconfig" diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig new file mode 100644 index ..7b4e4d613088 --- /dev/null +++ b/drivers/soc/Kconfig @@ -0,0 +1,5 @@ +menu "SOC (System On Chip) specific Drivers" + +source "drivers/soc/ti/Kconfig" + +endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 42037f99d587..8b7ead546e1c 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -3,3 +3,4 @@ # Makefile for the U-Boot SOC specific device drivers. obj-$(CONFIG_ARCH_KEYSTONE)+= keystone/ +obj-$(CONFIG_SOC_TI) += ti/ diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig new file mode 100644 index ..8c0f3c07b23f --- /dev/null +++ b/drivers/soc/ti/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ + +menuconfig SOC_TI + bool "TI SOC drivers support" + +if SOC_TI + +config TI_K3_NAVSS_RINGACC + bool "K3 Ring accelerator Sub System" + depends on ARCH_K3 + select MISC + help + Say y here to support the K3 AM65x Ring accelerator module. + The Ring Accelerator (RINGACC or RA) provides hardware acceleration + to enable straightforward passing of work between a producer + and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs + If unsure, say N. + + +endif # SOC_TI diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile new file mode 100644 index ..63e21aaad40f --- /dev/null +++ b/drivers/soc/ti/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# TI K3 SOC drivers +# +obj-$(CONFIG_TI_K3_NAVSS_RINGACC) += k3-navss-ringacc.o diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c new file mode 100644 index ..aeee9da47602 --- /dev/null +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -0,0 +1,1096 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define set
[U-Boot] [PATCH v3 3/7] soc: ti: k3: add CPPI5 description and helpers
From: Grygorii Strashko
Add TI Communications Port Programming Interface (CPPI) 5
interface description and helpers
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
---
include/linux/soc/ti/cppi5.h | 995 +++
1 file changed, 995 insertions(+)
create mode 100644 include/linux/soc/ti/cppi5.h
diff --git a/include/linux/soc/ti/cppi5.h b/include/linux/soc/ti/cppi5.h
new file mode 100644
index ..34038b31f702
--- /dev/null
+++ b/include/linux/soc/ti/cppi5.h
@@ -0,0 +1,995 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * CPPI5 descriptors interface
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#ifndef __TI_CPPI5_H__
+#define __TI_CPPI5_H__
+
+#include
+#include
+
+/**
+ * Descriptor header, present in all types of descriptors
+ */
+struct cppi5_desc_hdr_t {
+ u32 pkt_info0; /* Packet info word 0 (n/a in Buffer desc) */
+ u32 pkt_info1; /* Packet info word 1 (n/a in Buffer desc) */
+ u32 pkt_info2; /* Packet info word 2 Buffer reclamation info */
+ u32 src_dst_tag; /* Packet info word 3 (n/a in Buffer desc) */
+} __packed;
+
+/**
+ * Host-mode packet and buffer descriptor definition
+ */
+struct cppi5_host_desc_t {
+ struct cppi5_desc_hdr_t hdr;
+ u64 next_desc; /* w4/5: Linking word */
+ u64 buf_ptr;/* w6/7: Buffer pointer */
+ u32 buf_info1; /* w8: Buffer valid data length */
+ u32 org_buf_len; /* w9: Original buffer length */
+ u64 org_buf_ptr; /* w10/11: Original buffer pointer */
+ u32 epib[0];/* Extended Packet Info Data (optional, 4 words) */
+ /*
+* Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
+* and/or Other Software Data (0-N bytes, optional)
+*/
+} __packed;
+
+#define CPPI5_DESC_MIN_ALIGN (16U)
+
+#define CPPI5_INFO0_HDESC_EPIB_SIZE(16U)
+#define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE (128U)
+
+#define CPPI5_INFO0_HDESC_TYPE_SHIFT (30U)
+#define CPPI5_INFO0_HDESC_TYPE_MASKGENMASK(31, 30)
+#define CPPI5_INFO0_DESC_TYPE_VAL_HOST (1U)
+#define CPPI5_INFO0_DESC_TYPE_VAL_MONO (2U)
+#define CPPI5_INFO0_DESC_TYPE_VAL_TR (3U)
+#define CPPI5_INFO0_HDESC_EPIB_PRESENT BIT(29)
+/*
+ * Protocol Specific Words location:
+ * 0 - located in the descriptor,
+ * 1 = located in the SOP Buffer immediately prior to the data.
+ */
+#define CPPI5_INFO0_HDESC_PSINFO_LOCATION BIT(28)
+#define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT(22U)
+#define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
+#define CPPI5_INFO0_HDESC_PKTLEN_SHIFT (0)
+#define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
+
+#define CPPI5_INFO1_DESC_PKTERROR_SHIFT(28U)
+#define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
+#define CPPI5_INFO1_HDESC_PSFLGS_SHIFT (24U)
+#define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
+#define CPPI5_INFO1_DESC_PKTID_SHIFT (14U)
+#define CPPI5_INFO1_DESC_PKTID_MASKGENMASK(23, 14)
+#define CPPI5_INFO1_DESC_FLOWID_SHIFT (0)
+#define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
+
+#define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT(27U)
+#define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
+/* Return Policy: 0 - Entire packet 1 - Each buffer */
+#define CPPI5_INFO2_HDESC_RETPOLICYBIT(18)
+/*
+ * Early Return:
+ * 0 = desc pointers should be returned after all reads have been completed
+ * 1 = desc pointers should be returned immediately upon fetching
+ * the descriptor and beginning to transfer data.
+ */
+#define CPPI5_INFO2_HDESC_EARLYRET BIT(17)
+/*
+ * Return Push Policy:
+ * 0 = Descriptor must be returned to tail of queue
+ * 1 = Descriptor must be returned to head of queue
+ */
+#define CPPI5_INFO2_DESC_RETPUSHPOLICY BIT(16)
+#define CPPI5_INFO2_DESC_RETQ_SHIFT(0)
+#define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
+
+#define CPPI5_INFO3_DESC_SRCTAG_SHIFT (16U)
+#define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)
+#define CPPI5_INFO3_DESC_DSTTAG_SHIFT (0)
+#define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0)
+
+#define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT(0)
+#define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0)
+
+#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT(0)
+#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0)
+
+/*
+ * Host Packet Descriptor Extended Packet Info Block
+ */
+struct cppi5_desc_epib_t {
+ u32 timestamp; /* w0: application specific timestamp */
+ u32 sw_info0; /* w1: Software Info 0 */
+ u32 sw_info1; /* w2: Software Info 1 */
+ u32 sw_info2; /* w3: Software Info 2 */
+};
+
+/**
+ * Monolithic-mode packet descriptor
+ */
+struct cppi5_monolithic_desc_t {
+ struct cppi5_desc_hdr_t hdr;
+ u32 epib[0
[U-Boot] [PATCH v3 5/7] soc: keystone: Merge into TI specific directory
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.
Signed-off-by: Vignesh R
---
arch/arm/mach-keystone/Kconfig | 8
drivers/soc/Makefile | 1 -
drivers/soc/keystone/Makefile | 3 ---
drivers/soc/ti/Kconfig | 6 ++
drivers/soc/ti/Makefile| 5 ++---
drivers/soc/{keystone => ti}/keystone_serdes.c | 0
include/configs/ti_armv7_keystone2.h | 3 ---
scripts/config_whitelist.txt | 1 -
8 files changed, 16 insertions(+), 11 deletions(-)
delete mode 100644 drivers/soc/keystone/Makefile
rename drivers/soc/{keystone => ti}/keystone_serdes.c (100%)
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index d24596eccb0d..e06eba5aea1f 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -9,18 +9,24 @@ config TARGET_K2HK_EVM
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
select SPL_BOARD_INIT if SPL
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
config TARGET_K2G_EVM
bool "TI Keystone 2 Galileo EVM"
@@ -29,6 +35,8 @@ config TARGET_K2G_EVM
select TI_I2C_BOARD_DETECT
select CMD_DDR3
imply DM_I2C
+ imply SOC_TI
+ imply TI_KEYSTONE_SERDES
endchoice
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 8b7ead546e1c..ce253b7aa886 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,5 +2,4 @@
#
# Makefile for the U-Boot SOC specific device drivers.
-obj-$(CONFIG_ARCH_KEYSTONE)+= keystone/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/keystone/Makefile b/drivers/soc/keystone/Makefile
deleted file mode 100644
index dfebb143e09b..
--- a/drivers/soc/keystone/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig
index 8c0f3c07b23f..e4f88344487e 100644
--- a/drivers/soc/ti/Kconfig
+++ b/drivers/soc/ti/Kconfig
@@ -16,5 +16,11 @@ config TI_K3_NAVSS_RINGACC
and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs
If unsure, say N.
+config TI_KEYSTONE_SERDES
+ bool "Keystone SerDes driver for ethernet"
+ depends on ARCH_KEYSTONE
+ help
+SerDes driver for Keystone SoC used for ethernet support on TI
+K2 platforms.
endif # SOC_TI
diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
index 63e21aaad40f..4ec04ee1257e 100644
--- a/drivers/soc/ti/Makefile
+++ b/drivers/soc/ti/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
-#
-# TI K3 SOC drivers
-#
+
obj-$(CONFIG_TI_K3_NAVSS_RINGACC) += k3-navss-ringacc.o
+obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
diff --git a/drivers/soc/keystone/keystone_serdes.c
b/drivers/soc/ti/keystone_serdes.c
similarity index 100%
rename from drivers/soc/keystone/keystone_serdes.c
rename to drivers/soc/ti/keystone_serdes.c
diff --git a/include/configs/ti_armv7_keystone2.h
b/include/configs/ti_armv7_keystone2.h
index 0c7d66486832..6d8536a815f8 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -134,9 +134,6 @@
#define CONFIG_KSNET_SERDES_SGMII2_BASEKS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMIIKS2_LANES_PER_SGMII_SERDES
-/* SerDes */
-#define CONFIG_TI_KEYSTONE_SERDES
-
#define CONFIG_AEMIF_CNTRL_BASEKS2_AEMIF_CNTRL_BASE
/* I2C Configuration */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c05fc379645e..7a667ccbc3d2 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4420,7 +4420,6 @@ CONFIG_THOR_RESET_OFF
CONFIG_THUNDERX
CONFIG_TIMESTAMP
CONFIG_TIZEN
-CONFIG_TI_KEYSTONE_SERDES
CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
--
2.20.1
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[U-Boot] [PATCH v3 6/7] arm64: dts: ti: k3-am65: add mcu navss nodes
From: Grygorii Strashko
Add DT node for MCU NAVSS its components to get DMA working on AM654
SoC.
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 46
1 file changed, 46 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 143eb6d63092..5a934b106d04 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include
+#include
/ {
chosen {
@@ -63,6 +64,51 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x>;
};
+
+ navss_mcu: navss-mcu {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ti,sci-dev-id = <119>;
+
+ mcu_ringacc: ringacc@2b80 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>;
+ reg-names = "rt", "fifos",
+ "proxy_gcfg", "proxy_target";
+ ti,num-rings = <286>;
+ ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
+ ti,dma-ring-reset-quirk;
+ ti,sci = <>;
+ ti,sci-dev-id = <195>;
+ };
+
+ mcu_udmap: udmap@285c {
+ compatible = "ti,k3-navss-udmap";
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x2aa0 0x0 0x4>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ #dma-cells = <3>;
+
+ ti,ringacc = <_ringacc>;
+ ti,psil-base = <0x6000>;
+
+ ti,sci = <>;
+ ti,sci-dev-id = <194>;
+
+ ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
+ <0x2>; /* TX_CHAN */
+ ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
+ <0x4>; /* RX_CHAN */
+ ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
+ };
+ };
};
_wakeup {
--
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[U-Boot] [PATCH v3 1/7] firmware: ti_sci: Add support for NAVSS resource management
From: Grygorii Strashko
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.
This patch adds support for requesting and configuring such resources
from TI-SCI firmware.
Signed-off-by: Peter Ujfalusi
Signed-off-by: Grygorii Strashko
Reviewed-by: Tom Rini
Signed-off-by: Vignesh R
---
arch/arm/dts/k3-am65-wakeup.dtsi | 2 +-
drivers/firmware/ti_sci.c | 760 -
drivers/firmware/ti_sci.h | 642 +
include/linux/soc/ti/ti_sci_protocol.h | 300 ++
4 files changed, 1692 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
index 8d7b47f9dfbf..1f591ef8bb9e 100644
--- a/arch/arm/dts/k3-am65-wakeup.dtsi
+++ b/arch/arm/dts/k3-am65-wakeup.dtsi
@@ -7,7 +7,7 @@
_wakeup {
dmsc: dmsc {
- compatible = "ti,k2g-sci";
+ compatible = "ti,am654-sci";
ti,host-id = <12>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 91481260411a..ec78a520e702 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -31,16 +32,37 @@ struct ti_sci_xfer {
u8 rx_len;
};
+/**
+ * struct ti_sci_rm_type_map - Structure representing TISCI Resource
+ * management representation of dev_ids.
+ * @dev_id:TISCI device ID
+ * @type: Corresponding id as identified by TISCI RM.
+ *
+ * Note: This is used only as a work around for using RM range apis
+ * for AM654 SoC. For future SoCs dev_id will be used as type
+ * for RM range APIs. In order to maintain ABI backward compatibility
+ * type is not being changed for AM654 SoC.
+ */
+struct ti_sci_rm_type_map {
+ u32 dev_id;
+ u16 type;
+};
+
/**
* struct ti_sci_desc - Description of SoC integration
- * @host_id: Host identifier representing the compute entity
- * @max_rx_timeout_us: Timeout for communication with SoC (in Microseconds)
- * @max_msg_size: Maximum size of data per message that can be handled.
+ * @default_host_id: Host identifier representing the compute entity
+ * @max_rx_timeout_ms: Timeout for communication with SoC (in Milliseconds)
+ * @max_msgs: Maximum number of messages that can be pending
+ * simultaneously in the system
+ * @max_msg_size: Maximum size of data per message that can be handled.
+ * @rm_type_map: RM resource type mapping structure.
*/
struct ti_sci_desc {
- u8 host_id;
- int max_rx_timeout_us;
+ u8 default_host_id;
+ int max_rx_timeout_ms;
+ int max_msgs;
int max_msg_size;
+ struct ti_sci_rm_type_map *rm_type_map;
};
/**
@@ -136,7 +158,7 @@ static inline int ti_sci_get_response(struct ti_sci_info
*info,
int ret;
/* Receive the response */
- ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_us);
+ ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms);
if (ret) {
dev_err(info->dev, "%s: Message receive failed. ret = %d\n",
__func__, ret);
@@ -1441,6 +1463,147 @@ static int ti_sci_cmd_core_reboot(const struct
ti_sci_handle *handle)
return ret;
}
+static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
+ u16 *type)
+{
+ struct ti_sci_rm_type_map *rm_type_map = info->desc->rm_type_map;
+ bool found = false;
+ int i;
+
+ /* If map is not provided then assume dev_id is used as type */
+ if (!rm_type_map) {
+ *type = dev_id;
+ return 0;
+ }
+
+ for (i = 0; rm_type_map[i].dev_id; i++) {
+ if (rm_type_map[i].dev_id == dev_id) {
+ *type = rm_type_map[i].type;
+ found = true;
+ break;
+ }
+ }
+
+ if (!found)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * ti_sci_get_resource_range - Helper to get a range of resources assigned
+ *to a host. Resource is uniquely identified by
+ *type and subtype.
+ * @handle:Pointer to TISCI handle.
+ * @dev_id:TISCI device ID.
+ * @subtype: Resource assignment subtype that is being requested
+ * from the given device.
+ * @s_host:Host processor ID to which the resources are allocated
+ * @range_start: Start index of the resource range
+ * @range_num: Number of resources in the range
+ *
+ * Return
[U-Boot] [PATCH v3 0/7] AM65x: Add DMA support
This series adds DMA support for TI's AM654 SoC.
v3:
Minor comment/whitespace cleanups as pointed out by Tom Rini
v2:
Align DT bindings with latest proposed bindings as pointed out by Peter.
Merge drivers/soc/keystone into drivers/soc/ti
Background:
The AM65x TRM (http://www.ti.com/lit/pdf/spruid7b) describes the Data Movement
Architecture which is implmented by the k3-udma driver.
This DMA architecture is a big departure from 'traditional' architecture where
we had either EDMA or sDMA as system DMA.
Packet DMAs were used as dedicated DMAs to service only networking (K2)
or USB (am335x) while other peripherals were serviced by EDMA.
In AM65x the UDMA (Unified DMA) is used for all data movment within the SoC,
tasked to service all peripherals (UART, McSPI, McASP, networking, etc).
The NAVSS/UDMA is built around CPPI5 (Communications Port Programming Interface)
and it supports Packet mode (similar to CPPI4.1 in K2 for networking) and
TR mode (similar to EDMA descriptor).
The data movement is done within a PSI-L fabric, all peripherals (including the
UDMA-P). peripherals are not addressed by their I/O register as with traditional
DMAs but with their PSI-L thread ID.
To be able to use the DMA the following generic steps need to be taken:
- configure a DMA channel (tchan for TX, rchan for RX)
- channel mode: Packet or TR mode
- for memcpy a tchan and rchan pair is used.
- for packet mode RX we also need to configure a receive flow to configure the
packet receiption
- the source and destination threads must be paired
- at minimum one pair of rings need to be configured:
- tx: transfer ring and transfer completion ring
- rx: free descriptor ring and receive ring
When the channel setup is completed we only interract with the rings:
- TX: push a descriptor to t_ring and wait for it to be pushed to the tc_ring by
the UDMA-P
- RX: push a descriptor to the fd_ring and wait for UDMA-P to push it back to
the r_ring.
Resources Management and configuration of channel and ring is handled by
sending TI-SCI msgs to remote core.
Patches are based on kernel patches here:
https://patchwork.kernel.org/cover/10612465/
Grygorii Strashko (5):
firmware: ti_sci: Add support for NAVSS resource management
soc: ti: k3: add navss ringacc driver
soc: ti: k3: add CPPI5 description and helpers
arm64: dts: ti: k3-am65: add mcu navss nodes
configs: am65x_evm_a53: Enable DMA related configs
Vignesh R (2):
dma: ti: add driver to K3 UDMA
soc: keystone: Merge into ti specific directory
arch/arm/dts/k3-am65-wakeup.dtsi |2 +-
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 46 +
arch/arm/mach-keystone/Kconfig|8 +
configs/am65x_evm_a53_defconfig |4 +-
drivers/Kconfig |2 +
drivers/dma/Kconfig |2 +
drivers/dma/Makefile |2 +
drivers/dma/ti/Kconfig| 14 +
drivers/dma/ti/Makefile |3 +
drivers/dma/ti/k3-udma-hwdef.h| 184 ++
drivers/dma/ti/k3-udma.c | 1737 +
drivers/firmware/ti_sci.c | 760 +++-
drivers/firmware/ti_sci.h | 642 ++
drivers/soc/Kconfig |5 +
drivers/soc/Makefile |2 +-
drivers/soc/keystone/Makefile |3 -
drivers/soc/ti/Kconfig| 26 +
drivers/soc/ti/Makefile |4 +
drivers/soc/ti/k3-navss-ringacc.c | 1096 +++
.../soc/{keystone => ti}/keystone_serdes.c|0
include/configs/ti_armv7_keystone2.h |3 -
include/dt-bindings/dma/k3-udma.h | 31 +
include/linux/soc/ti/cppi5.h | 995 ++
include/linux/soc/ti/k3-navss-ringacc.h | 246 +++
include/linux/soc/ti/ti-udma.h| 24 +
include/linux/soc/ti/ti_sci_protocol.h| 300 +++
scripts/config_whitelist.txt |1 -
27 files changed, 6121 insertions(+), 21 deletions(-)
create mode 100644 drivers/dma/ti/Kconfig
create mode 100644 drivers/dma/ti/Makefile
create mode 100644 drivers/dma/ti/k3-udma-hwdef.h
create mode 100644 drivers/dma/ti/k3-udma.c
create mode 100644 drivers/soc/Kconfig
delete mode 100644 drivers/soc/keystone/Makefile
create mode 100644 drivers/soc/ti/Kconfig
create mode 100644 drivers/soc/ti/Makefile
create mode 100644 drivers/soc/ti/k3-navss-ringacc.c
rename drivers/soc/{keystone => ti}/keystone_serdes.c (100%)
create mode 100644 include/dt-bindings/dma/k3-udma.h
create mode 100644 include/linux/soc/ti/cppi5.h
create mode 100644 include/linux/soc/ti/k3-navss-ringacc.h
create mode 100644 include/linux/soc/ti/ti-udma.h
--
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[U-Boot] [PATCH v3 7/7] configs: am65x_evm_a53: Enable DMA related configs
From: Grygorii Strashko Enable TI K3 AM65x PSI-L, Ring Accelerator and UDMA drivers Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh R --- configs/am65x_evm_a53_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index a17cf7cb5040..9ce22157c92d 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -48,10 +48,11 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y -CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_K3_ARASAN=y @@ -67,5 +68,6 @@ CONFIG_REMOTEPROC_K3=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 16/20] mtd: spi: Add lightweight SPI flash stack for SPL
Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.
Based on prior work of reducing spi flash id table by
Simon Goldschmidt
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
common/spl/Kconfig | 11 +-
drivers/mtd/spi/Makefile | 10 +-
drivers/mtd/spi/sf_internal.h | 2 +
drivers/mtd/spi/spi-nor-core.c | 266 +--
drivers/mtd/spi/spi-nor-ids.c | 297
drivers/mtd/spi/spi-nor-tiny.c | 810 +
6 files changed, 1132 insertions(+), 264 deletions(-)
create mode 100644 drivers/mtd/spi/spi-nor-ids.c
create mode 100644 drivers/mtd/spi/spi-nor-tiny.c
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2e1dd2705a62..416f5933b0d9 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -732,9 +732,18 @@ config SPL_SPI_FLASH_SUPPORT
if SPL_SPI_FLASH_SUPPORT
+config SPL_SPI_FLASH_TINY
+ bool "Enable low footprint SPL SPI Flash support"
+ depends on !SPI_FLASH_BAR
+ help
+Enable lightweight SPL SPI Flash support that supports just reading
+data/images from flash. No support to write/erase flash. Enable
+this if you have SPL size limitations and don't need full
+fledged SPI flash support.
+
config SPL_SPI_FLASH_SFDP_SUPPORT
bool "SFDP table parsing support for SPI NOR flashes"
- depends on !SPI_FLASH_BAR
+ depends on !SPI_FLASH_BAR && !SPL_SPI_FLASH_TINY
help
Enable support for parsing and auto discovery of parameters for
SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 70058d3df2b9..f99f6cb16e29 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -4,12 +4,20 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+spi-nor-y := sf_probe.o spi-nor-ids.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
+ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y)
+spi-nor-y += spi-nor-tiny.o
+else
+spi-nor-y += spi-nor-core.o
+endif
+else
+spi-nor-y += spi-nor-core.o
endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
+obj-$(CONFIG_SPI_FLASH) += spi-nor.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index fd00e0d1b23b..a6bf734830a7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -16,7 +16,9 @@
#define SPI_NOR_MAX_ADDR_WIDTH 4
struct flash_info {
+#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
char*name;
+#endif
/*
* This array stores the ID bytes.
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index dbaaf45c7e1e..80633f8fd070 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -879,284 +879,26 @@ static int stm_is_locked(struct spi_nor *nor, loff_t
ofs, uint64_t len)
}
#endif /* CONFIG_SPI_FLASH_STMICRO */
-/* Used when the "_ext_id" is two bytes at most */
-#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
- .id = { \
- ((_jedec_id) >> 16) & 0xff, \
- ((_jedec_id) >> 8) & 0xff, \
- (_jedec_id) & 0xff, \
- ((_ext_id) >> 8) & 0xff,\
- (_ext_id) & 0xff, \
- }, \
- .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),
\
- .sector_size = (_sector_size), \
- .n_sectors = (_n_sectors), \
- .page_size = 256, \
- .flags = (_flags),
-
-#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
- .id = { \
- ((_jedec_id) >> 16) & 0xff, \
- ((_jedec_id) >> 8) & 0xff, \
- (_jedec_id) & 0xff, \
- ((_ext_id) >> 16) & 0xff, \
-
[U-Boot] [PATCH v3 4/7] dma: ti: add driver to K3 UDMA
The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet mode) - MEM_TO_DEV (Packet mode) Signed-off-by: Peter Ujfalusi Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh R --- drivers/dma/Kconfig |2 + drivers/dma/Makefile |2 + drivers/dma/ti/Kconfig| 14 + drivers/dma/ti/Makefile |3 + drivers/dma/ti/k3-udma-hwdef.h| 184 +++ drivers/dma/ti/k3-udma.c | 1737 + include/dt-bindings/dma/k3-udma.h | 31 + include/linux/soc/ti/ti-udma.h| 24 + 8 files changed, 1997 insertions(+) create mode 100644 drivers/dma/ti/Kconfig create mode 100644 drivers/dma/ti/Makefile create mode 100644 drivers/dma/ti/k3-udma-hwdef.h create mode 100644 drivers/dma/ti/k3-udma.c create mode 100644 include/dt-bindings/dma/k3-udma.h create mode 100644 include/linux/soc/ti/ti-udma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1820676d7a18..4f37ba7d35eb 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -57,4 +57,6 @@ config APBH_DMA_BURST8 endif +source "drivers/dma/ti/Kconfig" + endmenu # menu "DMA Support" diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index b5f9147e0a54..afab324461b9 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o + +obj-y += ti/ diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig new file mode 100644 index ..3d5498326c42 --- /dev/null +++ b/drivers/dma/ti/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ + +if ARCH_K3 + +config TI_K3_NAVSS_UDMA +bool "Texas Instruments UDMA" +depends on ARCH_K3 +select DMA +select TI_K3_NAVSS_RINGACC +select TI_K3_NAVSS_PSILCFG +default n +help + Support for UDMA used in K3 devices. +endif diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile new file mode 100644 index ..de2f9ac91a46 --- /dev/null +++ b/drivers/dma/ti/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_TI_K3_NAVSS_UDMA) += k3-udma.o diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h new file mode 100644 index ..c88399a815ea --- /dev/null +++ b/drivers/dma/ti/k3-udma-hwdef.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef K3_NAVSS_UDMA_HWDEF_H_ +#define K3_NAVSS_UDMA_HWDEF_H_ + +#define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000 + +/* Global registers */ +#define UDMA_REV_REG 0x0 +#define UDMA_PERF_CTL_REG 0x4 +#define UDMA_EMU_CTL_REG 0x8 +#define UDMA_PSIL_TO_REG 0x10 +#define UDMA_UTC_CTL_REG 0x1c +#define UDMA_CAP_REG(i)(0x20 + (i * 4)) +#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 +#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 + +/* RX Flow regs */ +#define UDMA_RFLOW_RFA_REG 0x0 +#define UDMA_RFLOW_RFB_REG 0x4 +#define UDMA_RFLOW_RFC_REG 0x8 +#define UDMA_RFLOW_RFD_REG 0xc +#define UDMA_RFLOW_RFE_REG 0x10 +#define UDMA_RFLOW_RFF_REG 0x14 +#define UDMA_RFLOW_RFG_REG 0x18 +#define UDMA_RFLOW_RFH_REG 0x1c + +#define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG) + +/* TX chan regs */ +#define UDMA_TCHAN_TCFG_REG0x0 +#define UDMA_TCHAN_TCREDIT_REG 0x4 +#define UDMA_TCHAN_TCQ_REG 0x14 +#define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4) +#define UDMA_TCHAN_TEOES_REG 0x60 +#define UDMA_TCHAN_TPRI_CTRL_REG 0x64 +#define UDMA_TCHAN_THREAD_ID_REG 0x68 +#define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70 +#define UDMA_TCHAN_TST_SCHED_REG 0x80 + +/* RX chan regs */ +#define UDMA_RCHAN_RCFG_REG0x0 +#define UDMA_RCHAN_RCQ_REG 0x14 +#define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4) +#define UDMA_RCHAN_REOES_REG 0x60 +#define UDMA_RCHAN_RPRI_CTRL_REG 0x64 +#define UDMA_RCHAN_THREAD_ID_REG 0x68 +#d
[U-Boot] [PATCH v3 18/20] configs: Remove SF_DUAL_FLASH
SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above enums yield no user and therefore support seems to be incomplete. Remove these configs so as to avoid confusion. Signed-off-by: Vignesh R --- configs/topic_miamilite_defconfig | 1 - configs/topic_miamiplus_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - doc/SPI/README.dual-flash | 92 --- include/configs/socfpga_stratix10_socdk.h | 1 - 17 files changed, 108 deletions(-) delete mode 100644 doc/SPI/README.dual-flash diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index e4d52f6a915e..95fa7678d639 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -40,7 +40,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index f742838d7c1f..6d753c0326a1 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -39,7 +39,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_NETDEVICES is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 3ec435e7ffe7..911d1beed2e1 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -54,7 +54,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 983e61e48e1a..35952d38157d 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 10d3489b6905..9c412ebf9544 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index 9ac3dd85f196..d1108b8e7d89 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index c154b15871f1..e5e4eb2b745e 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -42,7 +42,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index f2caac790a1a..dd6f50df4ee4 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -62,7 +62,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs
[U-Boot] [PATCH v3 13/20] mtd: spi: sf_probe: Add "jedec, spi-nor" compatible string
Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible SPI Flash device nodes. Therefore make U-Boot also to look for the same compatible string so that we can use Linux DTS files as is. Signed-off-by: Vignesh R Tested-by: Simon Goldschmidt Tested-by: Stefan Roese Tested-by: Horatiu Vultur https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 19/20] configs: Don't use SPI_FLASH_BAR as default
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R Tested-by: Simon Goldschmidt Tested-by: Stefan Roese Tested-by: Horatiu Vultur --- arch/arm/mach-omap2/am33xx/Kconfig | 1 - configs/alt_defconfig| 1 - configs/am57xx_evm_defconfig | 1 - configs/am57xx_hs_evm_defconfig | 1 - configs/ap121_defconfig | 1 - configs/ap143_defconfig | 1 - configs/avnet_ultra96_rev1_defconfig | 1 - configs/axs101_defconfig | 1 - configs/axs103_defconfig | 1 - configs/bg0900_defconfig | 1 - configs/blanche_defconfig| 1 - configs/cl-som-am57x_defconfig | 1 - configs/clearfog_defconfig | 1 - configs/cm_t43_defconfig | 1 - configs/db-88f6820-amc_defconfig | 1 - configs/display5_defconfig | 1 - configs/display5_factory_defconfig | 1 - configs/dra7xx_evm_defconfig | 1 - configs/dra7xx_hs_evm_defconfig | 1 - configs/ds109_defconfig | 1 - configs/ds414_defconfig | 1 - configs/evb-rv1108_defconfig | 1 - configs/gose_defconfig | 1 - configs/helios4_defconfig| 1 - configs/k2g_evm_defconfig| 1 - configs/k2g_hs_evm_defconfig | 1 - configs/koelsch_defconfig| 1 - configs/lager_defconfig | 1 - configs/maxbcm_defconfig | 1 - configs/mt7629_rfb_defconfig | 1 - configs/mx6sxsabreauto_defconfig | 1 - configs/mx6sxsabresd_defconfig | 1 - configs/mx6ul_14x14_evk_defconfig| 1 - configs/mx6ul_9x9_evk_defconfig | 1 - configs/mx6ull_14x14_evk_defconfig | 1 - configs/mx6ull_14x14_evk_plugin_defconfig| 1 - configs/mx7dsabresd_qspi_defconfig | 1 - configs/porter_defconfig | 1 - configs/r8a77970_eagle_defconfig | 1 - configs/silk_defconfig | 1 - configs/socfpga_arria5_defconfig | 1 - configs/socfpga_cyclone5_defconfig | 1 - configs/socfpga_is1_defconfig| 1 - configs/socfpga_sockit_defconfig | 1 - configs/socfpga_socrates_defconfig | 1 - configs/socfpga_sr1500_defconfig | 1 - configs/socfpga_stratix10_defconfig | 1 - configs/stout_defconfig | 1 - configs/topic_miami_defconfig| 1 - configs/topic_miamilite_defconfig| 1 - configs/topic_miamiplus_defconfig| 1 - configs/xilinx_versal_virt_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig| 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - configs/zynq_cc108_defconfig | 1 - configs/zynq_cse_qspi_defconfig | 1 - configs/zynq_dlc20_rev1_0_defconfig | 1 - configs/zynq_microzed_defconfig | 1 - configs/zynq_minized_defconfig | 1 - configs/zynq_z_turn_defconfig| 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 1 - configs/zynq_zybo_z7_defconfig | 1 - doc/SPI/README.ti_qspi_dra_test
[U-Boot] [PATCH v3 12/20] mtd: spi: spi-nor-core: Add back U-Boot specific features
For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework
Signed-off-by: Vignesh R
---
drivers/mtd/spi/spi-nor-core.c | 162 -
include/linux/mtd/spi-nor.h| 9 ++
2 files changed, 168 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 97ec8e8e7a19..c3f6929db506 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -291,6 +291,7 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
+#ifndef CONFIG_SPI_FLASH_BAR
static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
{
size_t i;
@@ -365,6 +366,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
}
+#endif /* !CONFIG_SPI_FLASH_BAR */
/* Enable/disable 4-byte addressing mode. */
static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
@@ -499,6 +501,79 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
DEFAULT_READY_WAIT_JIFFIES);
}
+#ifdef CONFIG_SPI_FLASH_BAR
+/*
+ * This "clean_bar" is necessary in a situation when one was accessing
+ * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
+ *
+ * After it the BA24 bit shall be cleared to allow access to correct
+ * memory region after SW reset (by calling "reset" command).
+ *
+ * Otherwise, the BA24 bit may be left set and then after reset, the
+ * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
+ */
+static int clean_bar(struct spi_nor *nor)
+{
+ u8 cmd, bank_sel = 0;
+
+ if (nor->bank_curr == 0)
+ return 0;
+ cmd = nor->bank_write_cmd;
+ nor->bank_curr = 0;
+ write_enable(nor);
+
+ return nor->write_reg(nor, cmd, _sel, 1);
+}
+
+static int write_bar(struct spi_nor *nor, u32 offset)
+{
+ u8 cmd, bank_sel;
+ int ret;
+
+ bank_sel = offset / SZ_16M;
+ if (bank_sel == nor->bank_curr)
+ goto bar_end;
+
+ cmd = nor->bank_write_cmd;
+ write_enable(nor);
+ ret = nor->write_reg(nor, cmd, _sel, 1);
+ if (ret < 0) {
+ debug("SF: fail to write bank register\n");
+ return ret;
+ }
+
+bar_end:
+ nor->bank_curr = bank_sel;
+ return nor->bank_curr;
+}
+
+static int read_bar(struct spi_nor *nor, const struct flash_info *info)
+{
+ u8 curr_bank = 0;
+ int ret;
+
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_SPANSION:
+ nor->bank_read_cmd = SPINOR_OP_BRRD;
+ nor->bank_write_cmd = SPINOR_OP_BRWR;
+ break;
+ default:
+ nor->bank_read_cmd = SPINOR_OP_RDEAR;
+ nor->bank_write_cmd = SPINOR_OP_WREAR;
+ }
+
+ ret = nor->read_reg(nor, nor->bank_read_cmd,
+ _bank, 1);
+ if (ret) {
+ debug("SF: fail to read bank addr register\n");
+ return ret;
+ }
+ nor->bank_curr = curr_bank;
+
+ return 0;
+}
+#endif
+
/*
* Initiate the erasure of a single sector
*/
@@ -543,6 +618,11 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
len = instr->len;
while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = write_bar(nor, addr);
+ if (ret < 0)
+ return ret;
+#endif
write_enable(nor);
ret = spi_nor_erase_sector(nor, addr);
@@ -557,9 +637,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
goto erase_err;
}
+erase_err:
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(nor);
+#endif
write_disable(nor);
-erase_err:
return ret;
}
@@ -1144,8 +1227,23 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
from, size_t len,
while (len) {
loff_t addr = from;
+ size_t read_len = len;
- ret = nor->read(nor, addr, len, buf);
+#ifdef CONFIG_SPI_FLASH_BAR
+ u32 remain_len;
+
+ ret = write_bar(nor, addr);
+ if (ret < 0)
+ return log_ret(ret);
+ remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
+
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+#endif
+
+ ret = nor->read(nor, addr, read_len, buf);
if (ret == 0) {
/* We shouldn't see 0-leng
[U-Boot] [PATCH v3 20/20] MAINTAINERS: Add an entry for SPI NOR
Add myself as co-maintainer for U-Boot SPI NOR subsystem. Signed-off-by: Vignesh R --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 33f1127e50a4..e06089133731 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -668,6 +668,15 @@ F: drivers/mtd/spi/ F: drivers/spi/ F: include/spi* +SPI-NOR +M: Jagan Teki +M: Vignesh R +S: Maintained +F: drivers/mtd/spi/ +F: include/spi_flash.h +F: include/linux/mtd/cfi.h +F: include/linux/mtd/spi-nor.h + SPMI M: Mateusz Kulikowski S: Maintained -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 15/20] mtd: spi: Remove unused files
spi_flash and spi_flash_ids are no longer needed after SPI NOR
migration. Remove them.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/mtd/spi/spi_flash.c | 1337 ---
drivers/mtd/spi/spi_flash_ids.c | 211 -
2 files changed, 1548 deletions(-)
delete mode 100644 drivers/mtd/spi/spi_flash.c
delete mode 100644 drivers/mtd/spi/spi_flash_ids.c
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
deleted file mode 100644
index 0c2392f28a43..
--- a/drivers/mtd/spi/spi_flash.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPI Flash Core
- *
- * Copyright (C) 2015 Jagan Teki
- * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
- * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
- * Copyright (C) 2008 Atmel Corporation
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "sf_internal.h"
-
-static void spi_flash_addr(u32 addr, u8 *cmd)
-{
- /* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
-}
-
-static int read_sr(struct spi_flash *flash, u8 *rs)
-{
- int ret;
- u8 cmd;
-
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, , 1, rs, 1);
- if (ret < 0) {
- debug("SF: fail to read status register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int read_fsr(struct spi_flash *flash, u8 *fsr)
-{
- int ret;
- const u8 cmd = CMD_FLAG_STATUS;
-
- ret = spi_flash_read_common(flash, , 1, fsr, 1);
- if (ret < 0) {
- debug("SF: fail to read flag status register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_sr(struct spi_flash *flash, u8 ws)
-{
- u8 cmd;
- int ret;
-
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, , 1, , 1);
- if (ret < 0) {
- debug("SF: fail to write status register\n");
- return ret;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int read_cr(struct spi_flash *flash, u8 *rc)
-{
- int ret;
- u8 cmd;
-
- cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash, , 1, rc, 1);
- if (ret < 0) {
- debug("SF: fail to read config register\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_cr(struct spi_flash *flash, u8 wc)
-{
- u8 data[2];
- u8 cmd;
- int ret;
-
- ret = read_sr(flash, [0]);
- if (ret < 0)
- return ret;
-
- cmd = CMD_WRITE_STATUS;
- data[1] = wc;
- ret = spi_flash_write_common(flash, , 1, , 2);
- if (ret) {
- debug("SF: fail to write config register\n");
- return ret;
- }
-
- return 0;
-}
-#endif
-
-int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash)
-{
- u8 status;
- int ret;
-
- ret = read_sr(flash, );
- if (ret)
- return ret;
-
- return (status >> 2) & 7;
-}
-
-#ifdef CONFIG_SPI_FLASH_BAR
-/*
- * This "clean_bar" is necessary in a situation when one was accessing
- * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
- *
- * After it the BA24 bit shall be cleared to allow access to correct
- * memory region after SW reset (by calling "reset" command).
- *
- * Otherwise, the BA24 bit may be left set and then after reset, the
- * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
- */
-static int clean_bar(struct spi_flash *flash)
-{
- u8 cmd, bank_sel = 0;
-
- if (flash->bank_curr == 0)
- return 0;
- cmd = flash->bank_write_cmd;
- flash->bank_curr = 0;
-
- return spi_flash_write_common(flash, , 1, _sel, 1);
-}
-
-static int write_bar(struct spi_flash *flash, u32 offset)
-{
- u8 cmd, bank_sel;
- int ret;
-
- bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
- if (bank_sel == flash->bank_curr)
- goto bar_end;
-
- cmd = flash->bank_write_cmd;
- ret = spi_flash_write_common(flash, , 1, _sel, 1);
- if (ret < 0) {
- debug("SF: fail to write bank register\n");
- return ret;
- }
-
-bar_end:
- flash->bank_curr = bank_sel;
- return flash->bank_curr;
-}
-
-static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
-{
- u8 curr_bank = 0;
- int ret;
-
- if (flash->size <= SPI_FLASH_16MB_BOUN)
- goto bar_end;
-
- switch (JEDEC_MFR(info)) {
-
[U-Boot] [PATCH v3 17/20] spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL
SPL only needs to be able to read from SPI Flash to load next stage and does not really need write/erase etc. Therefore in order to reduce SPI Flash code size in SPL, enable SPI_FLASH_TINY, that only supports reading from SPI flash, as default. Note: Since, SPI_FLASH_TINY does not support SPI_FLASH_BAR, SPI_FLASH_TINY is not enabled for boards with SPI controllers that cannot support 4 byte addressing. Signed-off-by: Vignesh R --- common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 416f5933b0d9..39a38a138b6b 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -735,6 +735,7 @@ if SPL_SPI_FLASH_SUPPORT config SPL_SPI_FLASH_TINY bool "Enable low footprint SPL SPI Flash support" depends on !SPI_FLASH_BAR + default y if SPI_FLASH help Enable lightweight SPL SPI Flash support that supports just reading data/images from flash. No support to write/erase flash. Enable -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 14/20] mtd: spi: Switch to new SPI NOR framework
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/mtd/spi/Kconfig| 2 +
drivers/mtd/spi/Makefile | 4 +-
drivers/mtd/spi/sandbox.c | 36 +++---
drivers/mtd/spi/sf_dataflash.c | 11 +-
drivers/mtd/spi/sf_internal.h | 225 ++---
drivers/mtd/spi/sf_probe.c | 32 +++--
drivers/mtd/spi/spi-nor-core.c | 59 +
drivers/spi/stm32_qspi.c | 4 +-
include/spi_flash.h| 105 ---
9 files changed, 113 insertions(+), 365 deletions(-)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 4ba95d58b371..e3b40fc157d6 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -27,6 +27,8 @@ config SPI_FLASH_SANDBOX
config SPI_FLASH
bool "Legacy SPI Flash Interface support"
+ depends on SPI
+ select SPI_MEM
help
Enable the legacy SPI flash support. This will include basic
standard support for things like probing, read / write, and
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index b4c7e1c98bd5..70058d3df2b9 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -9,7 +9,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
-obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
+obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 7b9891cb981c..084c66e9840b 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -92,7 +92,7 @@ struct sandbox_spi_flash {
/* The current flash status (see STAT_XXX defines above) */
u16 status;
/* Data describing the flash we're emulating */
- const struct spi_flash_info *data;
+ const struct flash_info *data;
/* The file on disk to serv up data from */
int fd;
};
@@ -122,7 +122,7 @@ static int sandbox_sf_probe(struct udevice *dev)
/* spec = idcode:file */
struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
size_t len, idname_len;
- const struct spi_flash_info *data;
+ const struct flash_info *data;
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
struct sandbox_state *state = state_get_current();
struct dm_spi_slave_platdata *slave_plat;
@@ -155,7 +155,7 @@ static int sandbox_sf_probe(struct udevice *dev)
idname_len = strlen(spec);
debug("%s: device='%s'\n", __func__, spec);
- for (data = spi_flash_ids; data->name; data++) {
+ for (data = spi_nor_ids; data->name; data++) {
len = strlen(data->name);
if (idname_len != len)
continue;
@@ -243,43 +243,43 @@ static int sandbox_sf_process_cmd(struct
sandbox_spi_flash *sbsf, const u8 *rx,
sbsf->cmd = rx[0];
switch (sbsf->cmd) {
- case CMD_READ_ID:
+ case SPINOR_OP_RDID:
sbsf->state = SF_ID;
sbsf->cmd = SF_ID;
break;
- case CMD_READ_ARRAY_FAST:
+ case SPINOR_OP_READ_FAST:
sbsf->pad_addr_bytes = 1;
- case CMD_READ_ARRAY_SLOW:
- case CMD_PAGE_PROGRAM:
+ case SPINOR_OP_READ:
+ case SPINOR_OP_PP:
sbsf->state = SF_ADDR;
break;
- case CMD_WRITE_DISABLE:
+ case SPINOR_OP_WRDI:
debug(" write disabled\n");
sbsf->status &= ~STAT_WEL;
break;
- case CMD_READ_STATUS:
+ case SPINOR_OP_RDSR:
sbsf->state = SF_READ_STATUS;
break;
- case CMD_READ_STATUS1:
+ case SPINOR_OP_RDSR2:
sbsf->state = SF_READ_STATUS1;
break;
- case CMD_WRITE_ENABLE:
+ case SPINOR_OP_WREN:
debug(" write enabled\n");
sbsf->status |= STAT_WEL;
break;
- case CMD_WRITE_STATUS:
+ case SPINOR_OP_WRSR:
sbsf->state = SF_WRITE_STATUS;
break;
default: {
int flags = sbsf->data->flags;
/* we only support erase here */
- if (sbsf->cmd == CMD_ERASE_CHIP) {
+ if (sbsf->cmd == SPINOR_OP_CHIP_ERASE) {
sbsf->erase_size = sbsf->data->sector_size *
sbsf->data->n_sectors;
[U-Boot] [PATCH v3 11/20] mtd: spi: spi-nor-core: Add SFDP support
Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
common/spl/Kconfig | 13 +-
drivers/mtd/spi/Kconfig| 14 +-
drivers/mtd/spi/spi-nor-core.c | 629 -
3 files changed, 649 insertions(+), 7 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 54b0dc34f595..2e1dd2705a62 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -730,13 +730,24 @@ config SPL_SPI_FLASH_SUPPORT
lines). This enables the drivers in drivers/mtd/spi as part of an
SPL build. This normally requires SPL_SPI_SUPPORT.
+if SPL_SPI_FLASH_SUPPORT
+
+config SPL_SPI_FLASH_SFDP_SUPPORT
+ bool "SFDP table parsing support for SPI NOR flashes"
+ depends on !SPI_FLASH_BAR
+ help
+Enable support for parsing and auto discovery of parameters for
+SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
+tables as per JESD216 standard in SPL.
+
config SPL_SPI_LOAD
bool "Support loading from SPI flash"
- depends on SPL_SPI_FLASH_SUPPORT
help
Enable support for loading next stage, U-Boot or otherwise, from
SPI NOR in U-Boot SPL.
+endif # SPL_SPI_FLASH_SUPPORT
+
config SPL_SPI_SUPPORT
bool "Support SPI drivers"
help
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 76d5a1d11527..4ba95d58b371 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -34,9 +34,18 @@ config SPI_FLASH
If unsure, say N
+if SPI_FLASH
+
+config SPI_FLASH_SFDP_SUPPORT
+ bool "SFDP table parsing support for SPI NOR flashes"
+ depends on !SPI_FLASH_BAR
+ help
+Enable support for parsing and auto discovery of parameters for
+SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
+tables as per JESD216 standard.
+
config SPI_FLASH_BAR
bool "SPI flash Bank/Extended address register support"
- depends on SPI_FLASH
help
Enable the SPI flash Bank/Extended address register support.
Bank/Extended address registers are used to access the flash
@@ -44,13 +53,10 @@ config SPI_FLASH_BAR
config SF_DUAL_FLASH
bool "SPI DUAL flash memory support"
- depends on SPI_FLASH
help
Enable this option to support two flash memories connected to a single
controller. Currently Xilinx Zynq qspi supports this.
-if SPI_FLASH
-
config SPI_FLASH_ATMEL
bool "Atmel SPI flash support"
help
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 570383464193..97ec8e8e7a19 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -81,6 +81,7 @@ struct flash_info {
* to support memory size above 128Mib.
*/
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
+#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
int (*quad_enable)(struct spi_nor *nor);
@@ -1411,6 +1412,39 @@ static int spansion_read_cr_quad_enable(struct spi_nor
*nor)
return 0;
}
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
+/**
+ * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
+ * @nor: pointer to a 'struct spi_nor'
+ *
+ * Set the Quad Enable (QE) bit in the Configuration Register.
+ * This function should be used with QSPI memories not supporting the Read
+ * Configuration Register (35h) instruction.
+ *
+ * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
+ * memories.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
+{
+ u8 sr_cr[2];
+ int ret;
+
+ /* Keep the current value of the Status Register. */
+ ret = read_sr(nor);
+ if (ret < 0) {
+ dev_dbg(nor->dev, "error while reading status register\n");
+ return -EINVAL;
+ }
+ sr_cr[0] = ret;
+ sr_cr[1] = CR_QUAD_EN_SPAN;
+
+ return write_sr_cr(nor, sr_cr);
+}
+
+#endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
#endif /* CONFIG_SPI_FLASH_SPANSION */
struct spi_nor_read_command {
@@ -1500,6 +1534,573 @@ spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
pp->proto = proto;
}
+#if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
+/*
+ * Serial Flash Discoverable Parameters (SFDP) parsing.
+ */
+
+/**
+ * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
+ * @nor: pointer to a 'struct spi_nor'
+ * @addr
[U-Boot] [PATCH v3 08/20] mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
Jagan, this patch is still 1.7K lines. But half of it is just flash ids
table and associated macros. Apart from that, it should be easier
to review.
drivers/mtd/spi/spi-nor-core.c | 1722
include/linux/mtd/cfi.h| 32 +
include/linux/mtd/spi-nor.h| 410
3 files changed, 2164 insertions(+)
create mode 100644 drivers/mtd/spi/spi-nor-core.c
create mode 100644 include/linux/mtd/cfi.h
create mode 100644 include/linux/mtd/spi-nor.h
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
new file mode 100644
index ..19171766ce82
--- /dev/null
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -0,0 +1,1722 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Based on m25p80.c, by Mike Lavender (m...@steroidmicros.com), with
+ * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
+ *
+ * Copyright (C) 2005, Intec Automation Inc.
+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
+ *
+ * Synced from Linux v4.19
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/* Define max times to check status register before we give up. */
+
+/*
+ * For everything but full-chip erase; probably could be much smaller, but kept
+ * around for safety for now
+ */
+
+#define HZ CONFIG_SYS_HZ
+
+#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+
+#define SPI_NOR_MAX_ID_LEN 6
+#define SPI_NOR_MAX_ADDR_WIDTH 4
+
+struct flash_info {
+ char*name;
+
+ /*
+* This array stores the ID bytes.
+* The first three bytes are the JEDIC ID.
+* JEDEC ID zero means "no ID" (mostly older chips).
+*/
+ u8 id[SPI_NOR_MAX_ID_LEN];
+ u8 id_len;
+
+ /* The size listed here is what works with SPINOR_OP_SE, which isn't
+* necessarily called a "sector" by the vendor.
+*/
+ unsigned intsector_size;
+ u16 n_sectors;
+
+ u16 page_size;
+ u16 addr_width;
+
+ u16 flags;
+#define SECT_4KBIT(0) /* SPINOR_OP_BE_4K works
uniformly */
+#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
+#define SST_WRITE BIT(2) /* use SST byte programming */
+#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
+#define SECT_4K_PMCBIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly
*/
+#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
+#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
+#define USE_FSRBIT(7) /* use flag status register */
+#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
+#define SPI_NOR_HAS_TB BIT(9) /*
+* Flash SR has Top/Bottom (TB) protect
+* bit. Must be used with
+* SPI_NOR_HAS_LOCK.
+*/
+#defineSPI_S3ANBIT(10) /*
+* Xilinx Spartan 3AN In-System Flash
+* (MFR cannot be used for probing
+* because it has the same value as
+* ATMEL flashes)
+*/
+#define SPI_NOR_4B_OPCODES BIT(11) /*
+* Use dedicated 4byte address op codes
+* to support memory size above 128Mib.
+*/
+#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
+#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
+};
+
+#define JEDEC_MFR(info)((info)->id[0])
+
+static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
+{
+ return -EINVAL;
+}
+
+static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+ return -EINVAL;
+}
+
+static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
+u_char *buf)
+{
+ return -EI
[U-Boot] [PATCH v3 06/20] spi: Add non DM version of SPI_MEM
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/spi/Kconfig| 4 +-
drivers/spi/Makefile | 1 +
drivers/spi/spi-mem-nodm.c | 105 +
3 files changed, 108 insertions(+), 2 deletions(-)
create mode 100644 drivers/spi/spi-mem-nodm.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index de4d62dd8fd1..df4c1a447842 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -16,8 +16,6 @@ config DM_SPI
typically use driver-private data instead of extending the
spi_slave structure.
-if DM_SPI
-
config SPI_MEM
bool "SPI memory extension"
help
@@ -25,6 +23,8 @@ config SPI_MEM
This extension is meant to simplify interaction with SPI memories
by providing an high-level interface to send memory-like commands.
+if DM_SPI
+
config ALTERA_SPI
bool "Altera SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4acec3ea17d7..39026712931b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
else
obj-y += spi.o
+obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
endif
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
new file mode 100644
index ..4447d4499135
--- /dev/null
+++ b/drivers/spi/spi-mem-nodm.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include
+#include
+
+int spi_mem_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ unsigned int pos = 0;
+ const u8 *tx_buf = NULL;
+ u8 *rx_buf = NULL;
+ u8 *op_buf;
+ int op_len;
+ u32 flag;
+ int ret;
+ int i;
+
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ rx_buf = op->data.buf.in;
+ else
+ tx_buf = op->data.buf.out;
+ }
+
+ op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ op_buf = calloc(1, op_len);
+
+ ret = spi_claim_bus(slave);
+ if (ret < 0)
+ return ret;
+
+ op_buf[pos++] = op->cmd.opcode;
+
+ if (op->addr.nbytes) {
+ for (i = 0; i < op->addr.nbytes; i++)
+ op_buf[pos + i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ pos += op->addr.nbytes;
+ }
+
+ if (op->dummy.nbytes)
+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+ /* 1st transfer: opcode + address + dummy cycles */
+ flag = SPI_XFER_BEGIN;
+ /* Make sure to set END bit if no tx or rx data messages follow */
+ if (!tx_buf && !rx_buf)
+ flag |= SPI_XFER_END;
+
+ ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag);
+ if (ret)
+ return ret;
+
+ /* 2nd transfer: rx or tx data path */
+ if (tx_buf || rx_buf) {
+ ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf,
+ rx_buf, SPI_XFER_END);
+ if (ret)
+ return ret;
+ }
+
+ spi_release_bus(slave);
+
+ for (i = 0; i < pos; i++)
+ debug("%02x ", op_buf[i]);
+ debug("| [%dB %s] ",
+ tx_buf || rx_buf ? op->data.nbytes : 0,
+ tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-");
+ for (i = 0; i < op->data.nbytes; i++)
+ debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
+ debug("[ret %d]\n", ret);
+
+ free(op_buf);
+
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int spi_mem_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ unsigned int len;
+
+ len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ if (slave->max_write_size && len > slave->max_write_size)
+ return -EINVAL;
+
+ if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_read_size);
+ else if (slave->max_write_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_write_size - len);
+
+ if (!op->data.nbytes)
+ return -EINVAL;
+
+ return 0;
+}
--
2.20.1
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[U-Boot] [PATCH v3 04/20] spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size
Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/spi/spi-mem.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 1da20b8de5c4..334af682dc65 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -412,6 +412,25 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct
spi_mem_op *op)
if (ops->mem_ops && ops->mem_ops->adjust_op_size)
return ops->mem_ops->adjust_op_size(slave, op);
+ if (!ops->mem_ops || !ops->mem_ops->exec_op) {
+ unsigned int len;
+
+ len = sizeof(op->cmd.opcode) + op->addr.nbytes +
+ op->dummy.nbytes;
+ if (slave->max_write_size && len > slave->max_write_size)
+ return -EINVAL;
+
+ if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_read_size);
+ else if (slave->max_write_size)
+ op->data.nbytes = min(op->data.nbytes,
+ slave->max_write_size - len);
+
+ if (!op->data.nbytes)
+ return -EINVAL;
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
--
2.20.1
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[U-Boot] [PATCH v3 09/20] mtd: spi: spi-nor-core: Add SPI MEM support
Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/mtd/spi/spi-nor-core.c | 97 --
1 file changed, 93 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 19171766ce82..633b7226f37f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -88,26 +88,115 @@ struct flash_info {
#define JEDEC_MFR(info)((info)->id[0])
+static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
+ *op, void *buf)
+{
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ op->data.buf.in = buf;
+ else
+ op->data.buf.out = buf;
+ return spi_mem_exec_op(nor->spi, op);
+}
+
static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
{
- return -EINVAL;
+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(len, NULL, 1));
+ int ret;
+
+ ret = spi_nor_read_write_reg(nor, , val);
+ if (ret < 0)
+ dev_dbg(>spimem->spi->dev, "error %d reading %x\n", ret,
+ code);
+
+ return ret;
}
static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
- return -EINVAL;
+ struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(len, NULL, 1));
+
+ return spi_nor_read_write_reg(nor, , buf);
}
static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
u_char *buf)
{
- return -EINVAL;
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
+ SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
+ SPI_MEM_OP_DATA_IN(len, buf, 1));
+ size_t remaining = len;
+ int ret;
+
+ /* get transfer protocols. */
+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
+ op.dummy.buswidth = op.addr.buswidth;
+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
+
+ /* convert the dummy cycles to the number of bytes */
+ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
+
+ while (remaining) {
+ op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
+ ret = spi_mem_adjust_op_size(nor->spi, );
+ if (ret)
+ return ret;
+
+ ret = spi_mem_exec_op(nor->spi, );
+ if (ret)
+ return ret;
+
+ op.addr.val += op.data.nbytes;
+ remaining -= op.data.nbytes;
+ op.data.buf.in += op.data.nbytes;
+ }
+
+ return len;
}
static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
const u_char *buf)
{
- return -EINVAL;
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
+ SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(len, buf, 1));
+ size_t remaining = len;
+ int ret;
+
+ /* get transfer protocols. */
+ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
+ op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
+ op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
+
+ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
+ op.addr.nbytes = 0;
+
+ while (remaining) {
+ op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
+ ret = spi_mem_adjust_op_size(nor->spi, );
+ if (ret)
+
[U-Boot] [PATCH v3 07/20] sh: bitops: add hweight*() macros
Add hweight*() macros required for moving to new SF layer Signed-off-by: Vignesh R --- arch/sh/include/asm/bitops.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index 8cb8385d76db..765f28f116bc 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -153,6 +153,10 @@ static inline int ffs (int x) } #define PLATFORM_FFS +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + #endif /* __KERNEL__ */ #endif /* __ASM_SH_BITOPS_H */ -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 05/20] spi: spi-mem: Claim SPI bus before spi mem access
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/spi/spi-mem.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 334af682dc65..1bb0987edb72 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -210,6 +210,10 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
if (!spi_mem_supports_op(slave, op))
return -ENOTSUPP;
+ ret = spi_claim_bus(slave);
+ if (ret < 0)
+ return ret;
+
if (ops->mem_ops) {
#ifndef __UBOOT__
/*
@@ -232,6 +236,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
mutex_lock(>io_mutex);
#endif
ret = ops->mem_ops->exec_op(slave, op);
+
#ifndef __UBOOT__
mutex_unlock(>io_mutex);
mutex_unlock(>bus_lock_mutex);
@@ -245,8 +250,10 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
* read path) and expect the core to use the regular SPI
* interface in other cases.
*/
- if (!ret || ret != -ENOTSUPP)
+ if (!ret || ret != -ENOTSUPP) {
+ spi_release_bus(slave);
return ret;
+ }
}
#ifndef __UBOOT__
@@ -333,10 +340,6 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
op_buf = calloc(1, op_len);
- ret = spi_claim_bus(slave);
- if (ret < 0)
- return ret;
-
op_buf[pos++] = op->cmd.opcode;
if (op->addr.nbytes) {
--
2.20.1
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[U-Boot] [PATCH v3 10/20] mtd: spi: spi-nor-core: Add 4 Byte addressing support
Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/mtd/spi/spi-nor-core.c | 141 +
1 file changed, 141 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 633b7226f37f..570383464193 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -290,6 +290,126 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info
*mtd)
return mtd->priv;
}
+static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
+{
+ size_t i;
+
+ for (i = 0; i < size; i++)
+ if (table[i][0] == opcode)
+ return table[i][1];
+
+ /* No conversion found, keep input op code. */
+ return opcode;
+}
+
+static u8 spi_nor_convert_3to4_read(u8 opcode)
+{
+ static const u8 spi_nor_3to4_read[][2] = {
+ { SPINOR_OP_READ, SPINOR_OP_READ_4B },
+ { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
+ { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
+ { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
+ { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
+ { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+
+ { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
+ { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
+ { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
+ };
+
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
+ ARRAY_SIZE(spi_nor_3to4_read));
+}
+
+static u8 spi_nor_convert_3to4_program(u8 opcode)
+{
+ static const u8 spi_nor_3to4_program[][2] = {
+ { SPINOR_OP_PP, SPINOR_OP_PP_4B },
+ { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
+ { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ };
+
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
+ ARRAY_SIZE(spi_nor_3to4_program));
+}
+
+static u8 spi_nor_convert_3to4_erase(u8 opcode)
+{
+ static const u8 spi_nor_3to4_erase[][2] = {
+ { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
+ { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
+ { SPINOR_OP_SE, SPINOR_OP_SE_4B },
+ };
+
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
+ ARRAY_SIZE(spi_nor_3to4_erase));
+}
+
+static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
+ const struct flash_info *info)
+{
+ /* Do some manufacturer fixups first */
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_SPANSION:
+ /* No small sector erase for 4-byte command set */
+ nor->erase_opcode = SPINOR_OP_SE;
+ nor->mtd.erasesize = info->sector_size;
+ break;
+
+ default:
+ break;
+ }
+
+ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
+ nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
+ nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
+}
+
+/* Enable/disable 4-byte addressing mode. */
+static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
+int enable)
+{
+ int status;
+ bool need_wren = false;
+ u8 cmd;
+
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_ST:
+ case SNOR_MFR_MICRON:
+ /* Some Micron need WREN command; all will accept it */
+ need_wren = true;
+ case SNOR_MFR_MACRONIX:
+ case SNOR_MFR_WINBOND:
+ if (need_wren)
+ write_enable(nor);
+
+ cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
+ status = nor->write_reg(nor, cmd, NULL, 0);
+ if (need_wren)
+ write_disable(nor);
+
+ if (!status && !enable &&
+ JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
+ /*
+* On Winbond W25Q256FV, leaving 4byte mode causes
+* the Extended Address Register to be set to 1, so all
+* 3-byte-address reads come from the second 16M.
+* We must clear the register to enable normal behavior.
+*/
+ write_enable(nor);
+ nor->cmd_buf[0] = 0;
+
[U-Boot] [PATCH v3 02/20] bitops: Fix GENMASK definition for Sandbox
In arch/sandbox/include/asm/types.h we have Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as CONFIG_PHYS64 is not set This messes up the current logic of GENMASK macro due to mismatch b/w size of unsigned long (64 bit) and that of BITS_PER_LONG. Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32 based on the host machine on which its being compiled. Without this patch: GENMASK(14,0) => 0x7fff After this patch: GENMASK(14,0) => 0x7fff Signed-off-by: Vignesh R --- include/linux/bitops.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index a47f6d17bb5f..259df43fb00f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -21,8 +21,13 @@ * position @h. For example * GENMASK_ULL(39, 21) gives us the 64bit vector 0x00e0. */ +#ifdef CONFIG_SANDBOX +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (CONFIG_SANDBOX_BITS_PER_LONG - 1 - (h +#else #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h +#endif #define GENMASK_ULL(h, l) \ (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 03/20] spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes
SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.
Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
---
drivers/spi/spi-mem.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index af9aef009a73..1da20b8de5c4 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -323,15 +323,6 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct
spi_mem_op *op)
return -EIO;
#else
- /* U-Boot does not support parallel SPI data lanes */
- if ((op->cmd.buswidth != 1) ||
- (op->addr.nbytes && op->addr.buswidth != 1) ||
- (op->dummy.nbytes && op->dummy.buswidth != 1) ||
- (op->data.nbytes && op->data.buswidth != 1)) {
- printf("Dual/Quad raw SPI transfers not supported\n");
- return -ENOTSUPP;
- }
-
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN)
rx_buf = op->data.buf.in;
--
2.20.1
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[U-Boot] [PATCH v3 00/20] SF: Migrate to Linux SPI NOR framework
Here is the v3 of SPI NOR migration(github branch at [1]). I have retained Tested-by from v2 as this is just re split of patches and minor fixups. Travis ci reports all green. Change log: Since v2: Split sync up patches into smaller versions so that its easier for review. Address comments by Jagan and Simon Goldschmidt on v2. Make SPI_FLASH_TINY(read only SF stack) as default for SPL build to offset against size increase due to new code. Since v1: Remove #ifindef __UBOOT__ Add back BAR support, but dont enable as default for all platform (see 10/11 for more details) Enable SPI_FLASH_TINY on boards where there is SPL size constraint as seen on travis ci builds. Drop sf_mtd changes for now as it seems to cause issues. v1: https://patchwork.ozlabs.org/cover/1012146/ Since RFC v2: Fix issues reported by Simon Goldschmidt wrt 4 use of byte addressing opcode Fix issues in compiling SFDP code Re organize file names and Makefile to simply spi-nor-tiny inclusion Remove SPI_FLASH_BAR and SF_DUAL_FLASH as these are no longer used RFC v2: https://patchwork.ozlabs.org/cover/1007589/ Since RFC v1: Add lightweight SPI flash stack for boards with SPL size constraints Provide non DM version of spi-mem Fix build issues on different platforms as reported by travis-ci on v1 RFC v1: https://patchwork.ozlabs.org/cover/1004689/ Background: U-Boot SPI NOR support (sf layer) is quite outdated as it does not support 4 byte addressing opcodes, SFDP table parsing and different types of quad mode enable sequences. Many newer flashes no longer support BANK registers used by sf layer to a access >16MB space. Also, many SPI controllers have special MMIO interfaces which provide accelerated read/write access but require knowledge of flash parameters to make use of it. Recent spi-mem layer provides a way to support such flashes but sf layer isn't using that. This patch series syncs SPI NOR framework from Linux v4.19. It also adds spi-mem support on top. So, we gain 4byte addressing support and SFDP support. This makes migrating to U-Boot MTD framework easier. Tested with few Spansion, micron and macronix flashes with TI's dra7xx, k2g, am43xx EVMs. I dont have access to flashes from other vendors. So, I would greatly appreciate testing on other platforms. Complete series with dependencies here[1] For clean build on some platforms, depends on CONFIG_SPI_FLASH migration to defconfigs [2] [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v3 [2] https://patchwork.ozlabs.org/patch/1007485/ Vignesh R (20): configs: Move CONFIG_SPI_FLASH into defconfigs bitops: Fix GENMASK definition for Sandbox spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size spi: spi-mem: Claim SPI bus before spi mem access spi: Add non DM version of SPI_MEM sh: bitops: add hweight*() macros mtd: spi: Port SPI NOR framework from Linux mtd: spi: spi-nor-core: Add SPI MEM support mtd: spi: spi-nor-core: Add 4 Byte addressing support mtd: spi: spi-nor-core: Add SFDP support mtd: spi: spi-nor-core: Add back U-Boot specific features mtd: spi: sf_probe: Add "jedec,spi-nor" compatible string mtd: spi: Switch to new SPI NOR framework mtd: spi: Remove unused files mtd: spi: Add lightweight SPI flash stack for SPL spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL configs: Remove SF_DUAL_FLASH configs: Don't use SPI_FLASH_BAR as default MAINTAINERS: Add an entry for SPI NOR MAINTAINERS |9 + arch/arm/mach-omap2/am33xx/Kconfig|1 - arch/sh/include/asm/bitops.h |4 + common/spl/Kconfig| 23 +- configs/alt_defconfig |1 - configs/am57xx_evm_defconfig |1 - configs/am57xx_hs_evm_defconfig |1 - configs/ap121_defconfig |1 - configs/ap143_defconfig |1 - configs/avnet_ultra96_rev1_defconfig |1 - configs/axs101_defconfig |1 - configs/axs103_defconfig |1 - configs/bg0900_defconfig |1 - configs/blanche_defconfig |1 - configs/cgtqmx6eval_defconfig |1 + configs/chromebit_mickey_defconfig|1 + configs/chromebook_jerry_defconfig|1 + configs/chromebook_minnie_defconfig |1 + configs/cl-som-am57x_defconfig|1 - configs/clearfog_defconfig|1 - configs/cm_t43_defconfig |1 - configs/db-88f6820-amc_defconfig |1 - configs/display5_defconfig|1 - configs/display5_factory_defconfig|1 - configs/dra7xx_evm_defconfig |1 - configs/dra7xx_hs_evm_defconfig |1 - configs/ds
[U-Boot] [PATCH v3 01/20] configs: Move CONFIG_SPI_FLASH into defconfigs
Completely move CONFIG_SPI_FLASH from remaining board header files to defconfigs Signed-off-by: Vignesh R --- configs/cgtqmx6eval_defconfig| 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/evb-rk3036_defconfig | 1 + configs/evb-rk3128_defconfig | 1 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/fennec-rk3288_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig| 1 + configs/ls2080aqds_qspi_defconfig| 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/miqi-rk3288_defconfig| 1 + configs/phycore-rk3288_defconfig | 1 + configs/popmetal-rk3288_defconfig| 1 + configs/rock2_defconfig | 1 + configs/rock_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + configs/turris_omnia_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + include/configs/cgtqmx6eval.h| 1 - include/configs/ls2080aqds.h | 2 -- include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/turris_omnia.h | 1 - 32 files changed, 24 insertions(+), 9 deletions(-) diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index 7f4c8de8f121..e6484b721954 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -55,6 +55,7 @@ CONFIG_DFU_SF=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x1200 CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_SPI=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 1c20dcd882d0..d74596dffd7a 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -60,6 +60,7 @@ CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 94a1af01be06..06744e34abbf 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -62,6 +62,7 @@ CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index cb7f52f040fd..565871496414 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -61,6 +61,7 @@ CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 439e69138636..33eaa062f5b8 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y # CONFIG_SPL_DM_SERIAL is not set diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index 00bf907ff132..d318478267ee 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -29,6 +29,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3128=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 980f7f7b3d61..eb4edd7c15e6 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -52,6 +52,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 10a5f09b313a..ad675173b61a 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -32,6 +32,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 2795ad82b063..df307f95be2d 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec
Re: [U-Boot] [PATCH v2 04/11] mtd: spi: Port SPI NOR framework from Linux
On 28/01/19 12:18 AM, Jagan Teki wrote:
> Do you have this whole series in some branch in github? I'm unable to
> apply it on master.
>
Here is my tentative v3 branch[1] based on top of today's master. I
haven't got to splitting up this patch yet. But have addressed all other
comments by you and Simon on this version.
[1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v3
Let me know if there are any additional comments. Thanks for the review!
> On Fri, Dec 21, 2018 at 12:15 PM Vignesh R wrote:
>>
>> Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
>> support 4 byte addressing opcodes, SFDP table parsing and different types of
>> quad mode enable sequences. Many newer flashes no longer support BANK
>> registers used by sf layer to a access >16MB space.
>> Also, many SPI controllers have special MMIO interfaces which provide
>> accelerated read/write access but require knowledge of flash parameters
>> to make use of it. Recent spi-mem layer provides a way to support such
>> flashes but sf layer isn't using that.
>> So sync SPI NOR framework from Linux v4.19 and add spi-mem support on top.
>> in order to gain 4 byte addressing support, SFDP support and a way to
>> support SPI controllers with MMIO flash interface.
>
> Understand the usage if direct complete sync, however it's difficult
> for me to review whole stuff. Can you please break into few patches
> like Basic sync, SFDP and other.
>
Ok, Let me see how that can be done.
>>
>> Signed-off-by: Vignesh R
>> ---
>> drivers/mtd/spi/spi-nor-core.c | 2590
>> include/linux/mtd/cfi.h| 32 +
>> include/linux/mtd/spi-nor.h| 410 +
>> 3 files changed, 3032 insertions(+)
>> create mode 100644 drivers/mtd/spi/spi-nor-core.c
>> create mode 100644 include/linux/mtd/cfi.h
>> create mode 100644 include/linux/mtd/spi-nor.h
>>
[...]
>> +static int spi_nor_sr_ready(struct spi_nor *nor)
>> +{
>> + int sr = read_sr(nor);
>> +
>> + if (sr < 0)
>> + return sr;
>> +
>> +#ifndef CONFIG_SPL_BUILD
>> + if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
>> + if (sr & SR_E_ERR)
>> + dev_dbg(nor->dev, "Erase Error occurred\n");
>> + else
>> + dev_dbg(nor->dev, "Programming Error occurred\n");
>> +
>> + nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
>> + return -EIO;
>> + }
>> +#endif
>
> Does it increase SPL size? or do we always assume SPL can't access
> flash that would require CLSR?
>
Code size increase.. But now that we have SPI_FLASH_TINY, will drop this...
>> +
>> + return !(sr & SR_WIP);
>> +}
>> +
[...]
>> +enum spi_nor_read_command_index {
>> + SNOR_CMD_READ,
>> + SNOR_CMD_READ_FAST,
>> + SNOR_CMD_READ_1_1_1_DTR,
>> +
>> + /* Dual SPI */
>> + SNOR_CMD_READ_1_1_2,
>> + SNOR_CMD_READ_1_2_2,
>> + SNOR_CMD_READ_2_2_2,
>> + SNOR_CMD_READ_1_2_2_DTR,
>> +
>> + /* Quad SPI */
>> + SNOR_CMD_READ_1_1_4,
>> + SNOR_CMD_READ_1_4_4,
>> + SNOR_CMD_READ_4_4_4,
>> + SNOR_CMD_READ_1_4_4_DTR,
>> +
>> + /* Octo SPI */
>> + SNOR_CMD_READ_1_1_8,
>> + SNOR_CMD_READ_1_8_8,
>> + SNOR_CMD_READ_8_8_8,
>> + SNOR_CMD_READ_1_8_8_DTR,
>> +
>> + SNOR_CMD_READ_MAX
>> +};
>> +
>> +enum spi_nor_pp_command_index {
>> + SNOR_CMD_PP,
>> +
>> + /* Quad SPI */
>> + SNOR_CMD_PP_1_1_4,
>> + SNOR_CMD_PP_1_4_4,
>> + SNOR_CMD_PP_4_4_4,
>> +
>> + /* Octo SPI */
>> + SNOR_CMD_PP_1_1_8,
>> + SNOR_CMD_PP_1_8_8,
>> + SNOR_CMD_PP_8_8_8,
>> +
>> + SNOR_CMD_PP_MAX
>> +};
>
> I'm afraid whether we teatsed all thse combinations? or we doing for
> the sake of Linux sync?
>
Code exists for 1_1_1, 1_1_2, 1_1_4 and 4_4_4 modes and has been tested
(on par with current U-Boot SF stack). 1-2-2 and 1-4-4 should work with
SFDP(haven't tested it on a real hw though). Other modes are not
implemented (but exists as a result of sync up with Linux) and enums are
dummy definitions with no effect on code (are there for future use). I
can drop unused once if you prefer.
--
Regards
Vignesh
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Re: [U-Boot] [PATCH 03/16] spi: Add non DM version of SPI_MEM
On 28/01/19 12:27 PM, Jagan Teki wrote:
> On Wed, Dec 12, 2018 at 11:08 PM Vignesh R wrote:
>>
>> Add non DM version of SPI_MEM to support easy migration to new SPI NOR
>> framework. This can be removed once DM_SPI conversion is complete.
>>
>> Signed-off-by: Vignesh R
>> ---
>> drivers/spi/Kconfig| 4 +-
>> drivers/spi/Makefile | 1 +
>> drivers/spi/spi-mem-nodm.c | 89 ++
>> 3 files changed, 92 insertions(+), 2 deletions(-)
>> create mode 100644 drivers/spi/spi-mem-nodm.c
>>
[...]
>> +int spi_mem_adjust_op_size(struct spi_slave *slave,
>> + struct spi_mem_op *op)
>> +{
>> + return 0;
>
> Does it not return data size of SPI mem, or not need for non-dm?
>
/**
* spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
* match controller limitations
* @slave: the SPI device
* @op: the operation to adjust
*
* Some controllers have FIFO limitations and must split a data transfer
* operation into multiple ones, others require a specific alignment for
* optimized accesses. This function allows SPI mem drivers to split a single
* operation into multiple sub-operations when required.
*
* Return: a negative error code if the controller can't properly adjust @op,
* 0 otherwise. Note that @op->data.nbytes will be updated if @op
* can't be handled in a single step.
*/
I will modify the function to take care of spi->max_write_size and
spi->max_read_size
in DM and non-DM case (instead of spi-nor-core.c).
--
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Vignesh
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Re: [U-Boot] [PATCH v2 01/11] spi-mem: Claim SPI bus before spi mem access
On 28/01/19 12:24 PM, Jagan Teki wrote: > On Fri, Dec 21, 2018 at 12:08 PM Vignesh R wrote: >> >> It is necessary to call spi_claim_bus() before starting any SPI >> transactions and this restriction would also apply when calling spi-mem >> operationss. Therefore claim and release bus before requesting transfer >> via exec_op. >> >> Signed-off-by: Vignesh R >> --- >> drivers/spi/spi-mem.c | 6 ++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c >> index 1da20b8de5c4..4c1463118ab2 100644 >> --- a/drivers/spi/spi-mem.c >> +++ b/drivers/spi/spi-mem.c >> @@ -231,7 +231,13 @@ int spi_mem_exec_op(struct spi_slave *slave, const >> struct spi_mem_op *op) >> mutex_lock(>bus_lock_mutex); >> mutex_lock(>io_mutex); >> #endif >> + ret = spi_claim_bus(slave); >> + if (ret < 0) >> + return ret; >> + >> ret = ops->mem_ops->exec_op(slave, op); >> + >> + spi_release_bus(slave); > > This making spi claims twice, since it's been doing before spi_xfer in > below code. better to make it before the if. > Ok, I will call it from common place -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] spi: Add support for the Aspeed ast2500 SPI controllers
Hi Cédric, On 25/01/19 11:30 PM, Boris Brezillon wrote: > +Vignesh > [...] >> The first is about performing direct accesses on the AHB window on which >> the flash contents is mapped. > > We have introduced the dirmap API/interface exactly for this purpose, > and the SPI NOR layer will use it in 5.1 (see [1]). > >> >> How do you distinguish a flash read (fast, dual, etc) from a RDSFPD command >> for instance ? > > Why do you need to know the access type? > >> Are the drivers expected to check the SPI OP command and >> depending on the target/command redirect to the appropriate address space ? >> > > Definitely not, the SPI MEM layer is supposed to be memory-type > agnostic, so you should not guess the operation type based on the > opcode. For direct mapping accesses, just implement the ->dirmap_xxx > hooks at the controller level and you'll be able to use the feature.>> >> Also, Aspeed SPI controllers have a Read Timing Compensation Register which >> defines different data input delay cycles depending on SPI clock rates. This >> register is supposed to be tuned when the flash chip characteristics are >> known, after the first bus scan. Is there a way to know that our SPI slave >> is alive and well detected before starting hammering successive reads on it >> to see how it behaves. > > Vignesh mentioned that a while back (couldn't find the thread where > this discussion happened) and I suggested adding a new hook to do this > "link training" process where you'd pass a spi_mem_op template + the > expected result so that the controller can test different setups until > it finds a working one. > Right, Cadence QSPI/OSPI needs PHY DLL values to be tuned for operating at higher frequencies. So idea is to use READID to read flash ID at lowest speed and use that as golden reference for tuning/link training at higher frequencies. I am guessing Aspeed SPI controller has similar need. Here is the discussion that Boris was talking about: https://lkml.org/lkml/2018/10/4/468 I haven't been able to get to implement his suggestions yet, but I think idea is generic enough. >> >> >> I think the U-Boot and Linux driver will be very similar wrt the issues >> above ? > I have submitted patches[1] to sync SPI NOR framework from kernel to U-Boot. Once that's merged then Aspeed SPI can make use of spi-mem interface in U-Boot as well. [1] https://patchwork.ozlabs.org/cover/1017335/ -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 09/11] configs: Remove SF_DUAL_FLASH
On 25/01/19 8:17 PM, Jagan Teki wrote: > On Fri, Dec 21, 2018 at 12:18 PM Vignesh R wrote: >> >> SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and >> SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above >> enums yield no user and therefore support seems to be incomplete. Remove >> these configs so as to avoid confusion. > > So, with Linux sync. all dual flash code is dropped is it? > Yes, because Linux does not support dual flash. I did try to add back dual flash support, but could not find any SPI flash claiming SF_DUAL_FLASH capability in today's U-Boot code. Therefore, this patch just drops the CONFIG option. Dual flash can always be added back to this framework when there is an actual user of the code in _mainline_ U-Boot. -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] configs: Move CONFIG_SPI_FLASH into defconfigs
On 04/12/18 2:15 PM, Vignesh R wrote: > Completely move CONFIG_SPI_FLASH from remaining board header files to > defconfigs > > Signed-off-by: Vignesh R > --- > Done with the help of moveconfig.py. Compile tested on travis-ci: > https://travis-ci.org/r-vignesh/u-boot/builds/463155999 > Gentle ping... > configs/cgtqmx6eval_defconfig| 1 + > configs/chromebit_mickey_defconfig | 1 + > configs/chromebook_jerry_defconfig | 1 + > configs/chromebook_minnie_defconfig | 1 + > configs/evb-rk3036_defconfig | 1 + > configs/evb-rk3128_defconfig | 1 + > configs/evb-rk3288_defconfig | 1 + > configs/evb-rk3328_defconfig | 1 + > configs/fennec-rk3288_defconfig | 1 + > configs/firefly-rk3288_defconfig | 1 + > configs/kylin-rk3036_defconfig | 1 + > configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + > configs/ls2080aqds_defconfig | 1 + > configs/ls2080aqds_nand_defconfig| 1 + > configs/ls2080aqds_qspi_defconfig| 1 + > configs/ls2080aqds_sdcard_defconfig | 1 + > configs/miqi-rk3288_defconfig| 1 + > configs/phycore-rk3288_defconfig | 1 + > configs/popmetal-rk3288_defconfig| 1 + > configs/rock2_defconfig | 1 + > configs/rock_defconfig | 1 + > configs/tinker-rk3288_defconfig | 1 + > configs/turris_omnia_defconfig | 1 + > configs/vyasa-rk3288_defconfig | 1 + > include/configs/cgtqmx6eval.h| 1 - > include/configs/ls2080aqds.h | 2 -- > include/configs/rk3036_common.h | 1 - > include/configs/rk3128_common.h | 1 - > include/configs/rk3188_common.h | 1 - > include/configs/rk3288_common.h | 1 - > include/configs/rk3328_common.h | 1 - > include/configs/turris_omnia.h | 1 - > 32 files changed, 24 insertions(+), 9 deletions(-) > > diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig > index 015bab0c643b..c6be96c496f1 100644 > --- a/configs/cgtqmx6eval_defconfig > +++ b/configs/cgtqmx6eval_defconfig > @@ -54,6 +54,7 @@ CONFIG_DFU_SF=y > CONFIG_USB_FUNCTION_FASTBOOT=y > CONFIG_FASTBOOT_BUF_ADDR=0x1200 > CONFIG_FSL_ESDHC=y > +CONFIG_SPI_FLASH=y > CONFIG_PHYLIB=y > CONFIG_MII=y > CONFIG_SPI=y > diff --git a/configs/chromebit_mickey_defconfig > b/configs/chromebit_mickey_defconfig > index 79ab6acaecf0..0ab5f632ad09 100644 > --- a/configs/chromebit_mickey_defconfig > +++ b/configs/chromebit_mickey_defconfig > @@ -60,6 +60,7 @@ CONFIG_CROS_EC_SPI=y > CONFIG_PWRSEQ=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SPI_FLASH=y > CONFIG_PINCTRL=y > CONFIG_SPL_PINCTRL=y > # CONFIG_SPL_PINCTRL_FULL is not set > diff --git a/configs/chromebook_jerry_defconfig > b/configs/chromebook_jerry_defconfig > index d892d65bf0a1..68bbc1d2b5c2 100644 > --- a/configs/chromebook_jerry_defconfig > +++ b/configs/chromebook_jerry_defconfig > @@ -62,6 +62,7 @@ CONFIG_CROS_EC_SPI=y > CONFIG_PWRSEQ=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SPI_FLASH=y > CONFIG_PINCTRL=y > CONFIG_SPL_PINCTRL=y > # CONFIG_SPL_PINCTRL_FULL is not set > diff --git a/configs/chromebook_minnie_defconfig > b/configs/chromebook_minnie_defconfig > index b0428740736b..e0b9ceea798b 100644 > --- a/configs/chromebook_minnie_defconfig > +++ b/configs/chromebook_minnie_defconfig > @@ -61,6 +61,7 @@ CONFIG_CROS_EC_SPI=y > CONFIG_PWRSEQ=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SPI_FLASH=y > CONFIG_PINCTRL=y > CONFIG_SPL_PINCTRL=y > # CONFIG_SPL_PINCTRL_FULL is not set > diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig > index 787d6f95c1bb..ba70bc6727f4 100644 > --- a/configs/evb-rk3036_defconfig > +++ b/configs/evb-rk3036_defconfig > @@ -41,6 +41,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_LED=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SPI_FLASH=y > CONFIG_PINCTRL=y > CONFIG_PINCTRL_ROCKCHIP_RK3036=y > # CONFIG_SPL_DM_SERIAL is not set > diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig > index 044e60735af0..2d2460c9c654 100644 > --- a/configs/evb-rk3128_defconfig > +++ b/configs/evb-rk3128_defconfig > @@ -29,6 +29,7 @@ CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MMC_DW=y > CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SPI_FLASH=y > CONFIG_PHY=y > CONFIG_PINCTRL=y > CONFIG_PINCTRL_ROCKCHIP_RK3128=y > diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig > index 1485844aa6c6..cf691df3c898 100644 > --- a/configs/evb-rk328
Re: [U-Boot] [PATCH 4/6] dma: ti: add driver to K3 UDMA
On 23/01/19 7:26 PM, Tom Rini wrote: > On Wed, Jan 23, 2019 at 07:13:11PM +0530, Vignesh R wrote: >> Tom, >> >> On 23/01/19 4:05 PM, Peter Ujfalusi wrote: >>> Tom, >>> >>> On 22/01/2019 20.56, Tom Rini wrote: >>>> On Tue, Jan 22, 2019 at 08:33:57PM +0530, Vignesh R wrote: >>>> >>>>> The UDMA-P is intended to perform similar (but significantly upgraded) >>>>> functions >>>>> as the packet-oriented DMA used on previous SoC devices. The UDMA-P module >>>>> supports the transmission and reception of various packet types. >>>>> The UDMA-P also supports acting as both a UTC and UDMA-C for its internal >>>>> channels. Channels in the UDMA-P can be configured to be either >>>>> Packet-Based or >>>>> Third-Party channels on a channel by channel basis. >>>>> >>>>> The initial driver supports: >>>>> - MEM_TO_MEM (TR mode) >>>>> - DEV_TO_MEM (Packet mode) >>>>> - MEM_TO_DEV (Packet mode) >>>>> >>>>> Signed-off-by: Peter Ujfalusi >>>>> Signed-off-by: Grygorii Strashko >>>>> Signed-off-by: Vignesh R >>>> >>>> Reviewed-by: Tom Rini >>>> >>>> And the DT binding is common to Linux, and been reviewed there? Or? >> >> As Peter pointed out DT bindings are not yet frozen and may change. >> Hence, I have added the nodes in -u-boot.dtsi. As and when DT bindings >> are accepted, these would be moved to base dtsi. >> >> UDMA support in kernel is currently blocked due to on going discussions >> on how UDMA/ring interrupts needs to be modeled and supported (not a so >> important for U-Boot UDMA support). But, I submitted patches for U-Boot >> as UDMA is support is required to support networking on AM654 which is >> essential for ease of booting the platform with U-Boot. >> >>> >>> The binding is the same for Linux but unfortunately it has not went >>> through a proper review yet due to the fact that I need to wait for the >>> interrupt support to arrive to mainline. >>> >>> However I have sent an earlier version as RFC: >>> https://www.spinics.net/lists/dmaengine/msg16661.html >>> >>> As for the bindings (and code): >>> The linux bindings are different: >>> >>> - there is no ti,psi-proxy anymore. >> >> Will drop this as U-Boot driver does not use them either. >> >>> - ringacc uses tisci to get GP ring range and we need >>> ti,sci-rm-range-gp-rings property in DT for it >>> - UDMA also uses tisci to get resource ranges and needs: >>> ti,sci-rm-range-tchan, ti,sci-rm-range-rchan, ti,sci-rm-range-rflow in DT >>> - UDMA does not have/need dma-channels property >> >> I plan to align above bindings with Linux as when bindings are accepted >> into kernel and then port it to U-Boot along with relevant TI-SCI driver >> code. >> >> Meanwhile would it be acceptable to add these nodes in -u-boot.dtsi to >> get closer to enable tftp? > > ... I knew I should have read the whole thread first. So, how likely do > we think the kernel bindings are to see big changes? I wonder if we > should re-align things now, or not. > I have posted v2 with bindings that are in full alignment with proposed Linux bindings that Peter pointed out above. IMO, I dont expect any big change in these bindings in upstream. -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
