This patch adds the CH7301 HDMI options and the common configuration
for DCU on LS1021AQDS board.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
Cc: Jason Jin jason@freescale.com
---
board/freescale/ls1021aqds/Makefile | 1
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li
HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Acked-by: York Sun york...@freescale.com
of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Acked-by: York Sun york...@freescale.com
---
arch/arm/include/asm/arch-ls102xa
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Acked-by: York Sun york...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h
is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Acked-by: York Sun york...@freescale.com
---
.../include/asm/arch-ls102xa/ls102xa_stream_id.h| 17 +
board/freescale/common/Makefile | 2
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.
This patch adds BE mode support for smp pen address.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Acked-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3
.
Xiubo Li (6):
ARM: HYP/non-sec: add the pen address BE mode support.
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
ls1021a: adding a secondary core boot address and kick functions
ls102xa: changing a few targets' configurations.
ARM: ls102xa: allow all the peripheral access
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li
manner.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 15 +++
arch/arm/include/asm/arch-ls102xa/config.h| 2 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
include/configs/ls1021aqds.h
Change for V3:
- Fix the language in commit message.
Change for V2:
- All the registers are defined as a struct, here use it.
- Use CONFIG_PEN_ADDR_BIG_ENDIAN instead of CONFIG_SOC_BIG_ENDIAN.
Xiubo Li (5):
ARM: HYP/non-sec: add the pen address BE mode support.
ARM: HYP/non-sec: Fix
of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm
is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
.../include/asm/arch-ls102xa/ls102xa_stream_id.h| 17 +
board/freescale/common/Makefile | 2 ++
board/freescale/common/ls102xa_stream_id.c
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.
This patch adds BE mode support for smp pen address.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
include/configs
For some SoCs, the pen address may has different endianness with
the CPUs, so this need the byte revertion for it,
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch
manner.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 15 +++
arch/arm/include/asm/arch-ls102xa/config.h| 2 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
include/configs/ls1021aqds.h
Change for V2:
- All the registers are defined as a struct, here use it.
- Use CONFIG_PEN_ADDR_BIG_ENDIAN instead of CONFIG_SOC_BIG_ENDIAN.
Xiubo Li (4):
ARM: HYP/non-sec: add the pen address byte reverting support.
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
ls102xa: HYP/non
of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 17 +
board/freescale/common/Makefile| 2 ++
board/freescale/common/ls102xa_stream_id.c | 19 +++
board/freescale/ls1021aqds
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
include/configs
Xiubo Li (4):
ARM: HYP/non-sec: add the pen address byte reverting support.
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
ls102xa: HYP/non-sec: support for ls102xa boards
ARM: ls102xa: allow all device accessable in non-secure state
arch/arm/cpu/armv7/ls102xa/cpu.c
manner.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 15 +++
arch/arm/include/asm/arch-ls102xa/config.h| 2 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
include/configs/ls1021aqds.h
For some SoCs, the pen address may has different endianness with
the CPUs, so this need the byte revertion for it,
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch
of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm
The memory where loaded the smp_waitloop code section probablly
be corrupted by Linux Kernel, then the secondary cores will be
running the random code, leading booting the secondary cores
failed.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 6
This adds CONFIG_TLB_SIZE for individual board, whose TLB size maybe
larger than PGTABLE_SIZE.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/lib/board.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index dc34190..b7327ce 100644
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
1 file changed, 2
For some SoCs, the pen address may has different endianness with
the CPUs, so this need the byte revertion for it,
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch
specific
manner.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 12
include/configs/ls1021aqds.h | 9 +
include/configs/ls1021atwr.h | 9 +
3 files changed, 30 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch
that are not synchronized, effectively seeing time
going backward...
Patch work:
http://patchwork.ozlabs.org/patch/343084/
Xiubo Li (4):
ARM: fix the ARCH Timer frequency setting.
ARM: add the pen address byte reverting support.
ARM: LS1021A: enable ARMv7 virt support for LS1021A A7
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +--
board/freescale/ls1021aqds/ls1021aqds.c | 110 +++--
board/freescale/ls1021atwr/ls1021atwr.c | 111 --
3 files
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