The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/cpu/andesv5/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch
On Tue, Dec 26, 2023 at 02:54:41PM +0800, Leo Yu-Chi Liang wrote:
> Enable MISC_INIT_R for ae350 to support CPU name detection
> and re-sync the configs via make savedefconfig.
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> ---
> configs/ae
On Tue, Dec 26, 2023 at 02:54:27PM +0800, Leo Yu-Chi Liang wrote:
> Detect CPU name through marchid and then save it to env.
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> ---
> board/AndesTech/ae350/ae350.c | 23 +++
> 1 file chan
On Tue, Dec 26, 2023 at 02:17:35PM +0800, Leo Yu-Chi Liang wrote:
> Andes CPU supports cache and TLB ECC.
> Enable them by default.
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> ---
> arch/riscv/cpu/andesv5/cpu.c| 3 ++-
> arch/riscv/i
On Tue, Dec 26, 2023 at 02:17:34PM +0800, Leo Yu-Chi Liang wrote:
> Andes CPU has memboost feature including prefetch,
> write-around and non-blocking load. Enable them by default.
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> ---
> arch/riscv
On Tue, Dec 26, 2023 at 02:17:33PM +0800, Leo Yu-Chi Liang wrote:
> Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
> Provide the corresponding implementation to the options.
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> ---
&g
On Tue, Dec 26, 2023 at 02:17:32PM +0800, Leo Yu-Chi Liang wrote:
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> arch/riscv/include/asm/arch-andes/csr.h | 20
> arch/riscv/include/asm/csr.h| 1 +
> 2 files changed, 9 inser
e cleanups to macros/functions.
Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to
single-bit-per-hart strategy")
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Randolph
---
arch/riscv/lib/andes_plicsw.c | 33 +++--
1 file changed, 15 insertion
or U-Boot SPL binaries.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Samuel Holland
---
Changes v1 -> v2:
- Drop imply conditions for *ANDES_PLMT_TIMER
- Add Samuel's RB-tag
---
arch/riscv/cpu/andesv5/Kconfig | 3 ++-
drivers/timer/Kconfig | 9 -
drivers/timer/Makef
Hi Samuel,
On Wed, Sep 27, 2023 at 04:32:30PM -0500, Samuel Holland wrote:
> On 9/27/23 02:25, Yu Chien Peter Lin wrote:
> > The Andes PLMT driver directly accesses the mtime MMIO region,
> > indicating its intended use in the M-mode boot stage. However,
> > since U-Boot prop
-off-by: Yu Chien Peter Lin
---
arch/riscv/cpu/andesv5/Kconfig | 3 ++-
drivers/timer/Kconfig | 9 -
drivers/timer/Makefile | 2 +-
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
index
This patch adds ISA string to the -march to generate zbb instructions
for U-Boot binaries, along with optimized string functions introduced
from Linux kernel.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/Kconfig | 92 +
arch/riscv/Makefile
The 'booti' command is unable to boot Image.gz due to the absence
of required environment variables 'kernel_comp_addr_r' and
'kernel_comp_size'.
This commit adds these variables and reorganizes the memory layout
to prevent any overlap between binaries and files.
Signed-off-by: Yu Chien Peter Lin
On some AE350 boards, we need to explicitly initialize the priority
registers to a non-zero value so the boot hart can instruct secondary
harts to jump to OpenSBI.
This patch also updates the information about PLICSW.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/lib/andes_plicsw.c | 25
On Fri, Feb 17, 2023 at 02:26:17PM +0100, Heinrich Schuchardt wrote:
> On 2/14/23 11:18, Yu Chien Peter Lin wrote:
> > This patch adds a brief introduction to the RISC-V architecture and
> > the typical boot process used on a variety of RISC-V platforms.
> >
> > Signed
On Fri, Feb 17, 2023 at 04:57:01PM +0800, Rick Chen wrote:
> Add the 'missing-msg' for more detailed output
> on missing system firmware.
>
> Signed-off-by: Rick Chen
> Reviewed-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> ---
> Changes in v2
> - Add
On Tue, Feb 14, 2023 at 08:42:50PM +0800, Leo Yu-Chi Liang wrote:
> Adjust the initial stack pointer address to 0x1000(256M)
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
> ---
> Change v1 -> v2:
> * Modify the address from 0x100(16MB
This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Samuel Holland
Reviewed-by: Simon Glass
---
Changes v1 -> v2
- Use 'boot phases' rather than 'boot stages'
- P
Hi Heinrich,
On Mon, Feb 13, 2023 at 08:36:30AM +0100, Heinrich Schuchardt wrote:
> On 2/12/23 08:00, Yu Chien Peter Lin wrote:
> > This patch adds a brief introduction to the RISC-V architecture and
> > the typical boot process used on a variety of RISC-V platforms.
> >
This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Samuel Holland
Reviewed-by: Simon Glass
---
Changes v1 -> v2
- Use 'boot phases' rather than 'boot stages'
- P
On Sun, Feb 12, 2023 at 12:25:56PM -0700, Simon Glass wrote:
> On Sun, 12 Feb 2023 at 00:01, Yu Chien Peter Lin
> wrote:
> >
> > This patch adds a brief introduction to the RISC-V architecture and
> > the typical boot process used on a variety of RISC-V platforms.
> &g
On Thu, Feb 09, 2023 at 04:34:13PM +0800, Leo Yu-Chi Liang wrote:
> The current ae350-related defconfigs could also
> support newer Andes CPU IP, so modify the names of CPU
> from ax25 to andesv5, and board name from ax25-ae350 to ae350.
>
> Signed-off-by: Leo Yu-Chi Liang
Review
Fix typo and whitespace in the document.
Signed-off-by: Yu Chien Peter Lin
---
doc/develop/devicetree/dt_qemu.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/develop/devicetree/dt_qemu.rst
b/doc/develop/devicetree/dt_qemu.rst
index c25c4fb053..8ba2b22559 100644
This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin
---
Hi RISC-V community,
Please leave a comment if there is anything I've missed that should
be mentioned in the document. Thanks
This patch fixes following warning for the riscv32 toolchain.
drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
122 | regs = (struct l2cache *)dev_read_addr(dev);
|^
Signed-off-by: Yu Chien Peter
Display information about CPU and board during start up.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
---
configs/ae350_rv32_defconfig | 2 ++
configs/ae350_rv32_spl_defconfig | 2 ++
configs/ae350_rv32_spl_xip_defconfig | 2 ++
configs/ae350_rv32_xip_defconfig
Loading an image via TFTP is often interrupted when retrying more than
10 times, increase the number of retries so that it does not simply stop
the transfer.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
---
configs/ae350_rv32_defconfig | 1 +
configs
To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
ca06444aac2c643db3a3f2eb37afc60fae15177e
Turing on does not significantly increase the size of u-boot-spl.bin,
so we enable it by default to improve performance.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
This patch refines L1 cache enable/disable and v5l2-cache enable
functions.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/ax25/cache.c | 98 +
1 file changed, 68 insertions(+), 30 deletions(-)
diff --git a/arch/riscv/cpu
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
drivers/cache/cache-v5l2.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv
/bd7ef4139829da5c30fa980f7498d385124408fa
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/ax25/cpu.c | 49 ++---
arch/riscv/include/asm/arch-andes/csr.h | 29 +++
2 files changed, 41 insertions(+), 37 deletions
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
---
drivers/cache/cache-v5l2.c | 32
The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
Reviewed-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +
1 file changed, 9
From: Leo Yu-Chi Liang
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
Reviewed-by: Rick Chen
---
arch/riscv/cpu/ax25/Kconfig | 10 -
arch/riscv/cpu/ax25/cache.c | 84
(1):
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
Yu Chien Peter Lin (9):
board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2
platform
riscv: cpu: ax25: Simplify cache e
PLIC is used for external interrupt, while PLICSW is an Andes-specific
design for software interrupt.
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
Reviewed-by: Rick Chen
---
Change v1 -> v2
- Separate from patchset of cache operation
---
arch/riscv/include/asm/global_dat
This patch improves the cache enabling operation in harts_early_init(),
also moves the CSR definition to include/asm/arch-andes/csr.h and drops
unnecessary i/d-cache disable functions from cleanup_before_linux().
Signed-off-by: Yu Chien Peter Lin
Reviewed-by: Leo Yu-Chi Liang
---
Changes v1
Hi Leo,
On Tue, Jan 31, 2023 at 07:07:02AM +, Leo Liang wrote:
> Hi Peter,
> On Thu, Jan 19, 2023 at 03:05:38PM +0800, Yu Chien Peter Lin wrote:
> > This patch improves the cache enabling operation in harts_early_init(),
> > also moves the CSR definition to include/as
This patch fixes following warning for riscv32 compilation.
drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
122 | regs = (struct l2cache *)dev_read_addr(dev);
|^
Signed-off-by: Yu Chien Peter Lin
Display information about CPU and board during start up.
Signed-off-by: Yu Chien Peter Lin
---
configs/ae350_rv32_defconfig | 2 ++
configs/ae350_rv32_spl_defconfig | 2 ++
configs/ae350_rv32_spl_xip_defconfig | 2 ++
configs/ae350_rv32_xip_defconfig | 2 ++
configs
Loading image over TFTP is often interrupted since it does more than
10 times retries, increase the number of retries so it will not easily
stop the transmission.
Signed-off-by: Yu Chien Peter Lin
---
configs/ae350_rv32_defconfig | 1 +
configs/ae350_rv32_spl_defconfig | 1
Enable cache-v5l2 driver for each AE350 defconfig.
Signed-off-by: Yu Chien Peter Lin
---
configs/ae350_rv32_defconfig | 1 +
configs/ae350_rv32_spl_defconfig | 3 +++
configs/ae350_rv32_spl_xip_defconfig | 3 +++
configs/ae350_rv32_xip_defconfig | 1 +
configs
This patch refines L1 cache enable/disable and v5l2-cache enable
functions.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/cpu/ax25/cache.c | 100
1 file changed, 68 insertions(+), 32 deletions(-)
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
drivers/cache/cache-v5l2.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts
This patch improves the cache enabling operation in harts_early_init(),
also moves the CSR definition to include/asm/arch-andes/csr.h and drops
unnecessary i/d-cache disable functions from cleanup_before_linux().
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/cpu/ax25/cpu.c | 46
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.
Signed-off-by: Yu Chien Peter Lin
---
drivers/cache/cache-v5l2.c | 32
1 file changed
The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.
Signed-off-by: Yu Chien Peter Lin
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/board
From: Leo Yu-Chi Liang
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
---
arch/riscv/cpu/ax25/Kconfig | 10 -
arch/riscv/cpu/ax25/cache.c | 84 +
drivers/cache
PLIC is used for external interrupt, while PLICSW is an Andes-specific
design for software interrupt.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/include/asm/global_data.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv
This patchset is intended to enable L2-cache in U-boot SPL, along with
cache operations cleanup for AE350 platforms.
Leo Yu-Chi Liang (1):
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
Yu Chien Peter Lin (10):
riscv: global_data.h: Correct the comment for PLICSW
board: Andes
On Sun, Nov 13, 2022 at 03:47:38PM -0600, Samuel Holland wrote:
> On 11/5/22 01:02, Yu Chien Peter Lin wrote:
> > We should check the string until it hits underscore, in case it
> > searches for the letters in the custom extension. For example,
> > "rv64imac_xandes"
izing FCSR.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/cpu/cpu.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 52ab02519f..d34c8efce0 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -36
On Fri, Nov 04, 2022 at 11:39:43PM -0500, Samuel Holland wrote:
> On 11/4/22 06:21, Yu Chien Peter Lin wrote:
> > We should check the string until it hits underscore, in case it
> > searches for the letters in the custom extension. For example,
> > "rv64imac_xandes"
izing FCSR.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/cpu/cpu.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 52ab02519f..dc949c1306 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -36
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/Kconfig
The IPI scheme in OpenSBI has been updated to support 8-core AE350
platform, the plicsw configuration needs to be modified accordingly.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/lib/andes_plic.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/lib
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