[U-Boot] [PATCH v3] armv8: QSPI: Add AHB bus 16MB+ size support

2016-11-30 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
Rename the CONFIG_SYS_QSPI_ADDR to SYS_FSL_QSPI_ADDR.
Changed in v2:
Remove the CONFIG_QSPI_AHB_INIT into Kconfig.
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  7 
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 42 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 configs/ls1012afrdm_qspi_defconfig |  1 +
 configs/ls1012aqds_qspi_defconfig  |  1 +
 configs/ls1012ardb_qspi_defconfig  |  1 +
 configs/ls1046ardb_qspi_defconfig  |  1 +
 9 files changed, 56 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..f078712 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -71,6 +71,13 @@ config NUM_DDR_CONTROLLERS
default 3 if ARCH_LS2080A
default 1
 
+config QSPI_AHB_INIT
+   bool "Init the QSPI AHB bus"
+   help
+ The default setting for QSPI AHB bus just support 3bytes addressing.
+ But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
+ bus for those flashes to support the full QSPI flash size.
+
 config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c42387..2f54625 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -373,6 +373,45 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+   u32 *qspi_lut, lut_key, *qspi_key;
+
+   qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
+   qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
+
+   lut_key = in_be32(qspi_key);
+
+   if (lut_key == 0x5af05af0) {
+   /* That means the register is BE */
+   out_be32(qspi_key, 0x5af05af0);
+   /* Unlock the lut table */
+   out_be32(qspi_key + 1, 0x0002);
+   out_be32(qspi_lut, 0x0820040c);
+   out_be32(qspi_lut + 1, 0x1c080c08);
+   out_be32(qspi_lut + 2, 0x2400);
+   /* Lock the lut table */
+   out_be32(qspi_key, 0x5af05af0);
+   out_be32(qspi_key + 1, 0x0001);
+   } else {
+   /* That means the register is LE */
+   out_le32(qspi_key, 0x5af05af0);
+   /* Unlock the lut table */
+   out_le32(qspi_key + 1, 0x0002);
+   out_le32(qspi_lut, 0x0820040c);
+   out_le32(qspi_lut + 1, 0x1c080c08);
+   out_le32(qspi_lut + 2, 0x2400);
+   /* Lock the lut table */
+   out_le32(qspi_key, 0x5af05af0);
+   out_le32(qspi_key + 1, 0x0001);
+   }
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -382,6 +421,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+   qspi_ahb_init();
+#endif
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..ff0a88a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x0040)
 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0053)
+#define SYS_FSL_QSPI_ADDR  (CONFIG_SYS_IMMR + 0x0055)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0056)
 #define CONFIG_SYS_FSL_CSU_ADDR(CONFIG_SYS_IMMR + 
0x0051)
 #define CONFIG_SYS_FSL_GUTS_ADDR   (CONFIG_SYS_IMMR + 0x00ee)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 2df56f7..e18dcbd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR   (CONFIG_SYS_IMMR + 0x0030)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR   (CONFIG_SYS_IMMR + 0x0031)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR   (CONFIG

[U-Boot] [PATCH v2] armv8: QSPI: Add AHB bus 16MB+ size support

2016-11-29 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Remove the CONFIG_QSPI_AHB_INIT into Kconfig.
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  7 
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 38 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 configs/ls1012afrdm_qspi_defconfig |  1 +
 configs/ls1012aqds_qspi_defconfig  |  1 +
 configs/ls1012ardb_qspi_defconfig  |  1 +
 configs/ls1046ardb_qspi_defconfig  |  1 +
 scripts/config_whitelist.txt   |  1 +
 9 files changed, 52 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..f078712 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -71,6 +71,13 @@ config NUM_DDR_CONTROLLERS
default 3 if ARCH_LS2080A
default 1
 
+config QSPI_AHB_INIT
+   bool "Init the QSPI AHB bus"
+   help
+ The default setting for QSPI AHB bus just support 3bytes addressing.
+ But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
+ bus for those flashes to support the full QSPI flash size.
+
 config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c42387..44927b1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -373,6 +373,41 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+   u32 *qspi_lut, lut_key, *qspi_key;
+
+   qspi_key = (void *)CONFIG_SYS_QSPI_ADDR + 0x300;
+   qspi_lut = (void *)CONFIG_SYS_QSPI_ADDR + 0x310;
+
+   lut_key = in_be32(qspi_key);
+
+   if (lut_key == 0x5af05af0) {
+   /* That means the register is BE */
+   out_be32(qspi_key, 0x5af05af0);
+   out_be32(qspi_key + 1, 0x0002);
+   out_be32(qspi_lut, 0x0820040c);
+   out_be32(qspi_lut + 1, 0x1c080c08);
+   out_be32(qspi_lut + 2, 0x2400);
+   out_be32(qspi_key, 0x5af05af0);
+   out_be32(qspi_key + 1, 0x0001);
+   } else {
+   /* That means the register is LE */
+   out_le32(qspi_key, 0x5af05af0);
+   out_le32(qspi_key + 1, 0x0002);
+   out_le32(qspi_lut, 0x0820040c);
+   out_le32(qspi_lut + 1, 0x1c080c08);
+   out_le32(qspi_lut + 2, 0x2400);
+   out_le32(qspi_key, 0x5af05af0);
+   out_le32(qspi_key + 1, 0x0001);
+   }
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -382,6 +417,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+   qspi_ahb_init();
+#endif
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..a28b1fd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x0040)
 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0053)
+#define CONFIG_SYS_QSPI_ADDR   (CONFIG_SYS_IMMR + 0x0055)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0056)
 #define CONFIG_SYS_FSL_CSU_ADDR(CONFIG_SYS_IMMR + 
0x0051)
 #define CONFIG_SYS_FSL_GUTS_ADDR   (CONFIG_SYS_IMMR + 0x00ee)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 2df56f7..e0cf0e4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR   (CONFIG_SYS_IMMR + 0x0030)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR   (CONFIG_SYS_IMMR + 0x0031)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR   (CONFIG_SYS_IMMR + 0x0037)
+#define CONFIG_SYS_QSPI_ADDR   (CONFIG_SYS_IMMR + 0x010c)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x011400

[U-Boot] [PATCH v2] ls1021a: QSPI: update the node for QSPI support

2016-11-29 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add the name for register space and memory space.
<0x155 0x1 > is the QSPI register space.
<0x4000 0x400> is the QSPI memory space.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Updated the commit message.
---
 arch/arm/dts/ls1021a.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1af..37be169 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -176,6 +176,7 @@
#size-cells = <0>;
reg = <0x155 0x1>,
<0x4000 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3] armv8: fsl-layerscape: Add Readme for deploy QSPI image

2016-11-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
Rename README.deploy to README.qspi
Changed in v2:
Move the readme for QSPI deploy out of only for ls2080aqds.
---
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi | 42 +++
 1 file changed, 42 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi
new file mode 100644
index 000..de86f4b
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi
@@ -0,0 +1,42 @@
+QSPI Boot source support Overview
+---
+   1. LS1043A
+   LS1043AQDS
+   2. LS2080A
+   LS2080AQDS
+   3. LS1012A
+   LS1012AQDS
+   LS1012ARDB
+   4. LS1046A
+   LS1046AQDS
+   LS1046ARDB
+
+Booting from QSPI
+---
+Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
+The difference between QSPI boot RCW image and NOR boot image is the PBI
+command sequence for setting the boot location pointer. It's should point
+to the address for u-boot in QSPI flash.
+
+RCW image should be written to the beginning of QSPI flash device.
+Example of using u-boot command
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 0 +
+SF: 65536 bytes @ 0x0 Erased: OK
+=> sf write  0 
+SF: 164 bytes @ 0x0 Written: OK
+
+To get the QSPI image, build u-boot with QSPI config, for example,
+_qspi_defconfig. The image needed is u-boot-dtb.bin.
+The u-boot image should be written to 0x1(but 0x1000 for LS1043A, LS2080A).
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 1 +
+SF: 589824 bytes @ 0x1 Erased: OK
+=> sf write  1 
+SF: 580966 bytes @ 0x1 Written: OK
+
+With these two images in QSPI flash device, the board can boot from QSPI.
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2] arm: ls1021a: improve the core frequency to 1.2GHZ

2016-11-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Change core clock to 1.2GHz in the configurations for SD and NAND boot.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Updated the commit message.
---
 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg| 2 +-
 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg  | 4 ++--
 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg | 4 ++--
 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg  | 2 +-
 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 
b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
index 222c71d..d76e913 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # serdes protocol
-0608000a   
+0608000c   
 6000 00407900 e0106a00 21046000
    00038000
  001b7200  
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 
b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
index 9d99bd8..f0cf9c2 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a   
+0608000c   
 6000 00407900 60040a00 21046000
    00038000
  001b7200  
 
 #disable IFC, enable QSPI and DSPI
-#0608000a   
+#0608000c   
 #6000 00407900 60040a00 21046000
 #   00038000
 #20024800 001b7200  
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 
b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
index 2bd398c..10cc4a9 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-#0608000a   
+#0608000c   
 #6000 00407900 60040a00 21046000
 #   00038000
 # 001b7200  
 
 #disable IFC, enable QSPI and DSPI
-0608000a   
+0608000c   
 6000 00407900 60040a00 21046000
    00038000
 20024800 001b7200  
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 
b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
index 205606f..f94997d 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a   
+0608000c   
 3000 7900 60040a00 21046000
    2000
 0008 881b7340  
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 
b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
index 6767e09..541b604 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #disable IFC, enable QSPI and DSPI
-0608000a   
+0608000c   
 3000 7900 60040a00 21046000
    2000
 20024800 881b7340  
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] arm: ls1021a: improve the core frequency to 1.2GHZ

2016-11-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

LS1021A is working stability with 1.2GHZ, so as a performance
requirements we can improve the core frequency to 1.2GHZ for
SD boot and NAND boot.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg| 2 +-
 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg  | 4 ++--
 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg | 4 ++--
 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg  | 2 +-
 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 
b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
index 222c71d..d76e913 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # serdes protocol
-0608000a   
+0608000c   
 6000 00407900 e0106a00 21046000
    00038000
  001b7200  
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 
b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
index 9d99bd8..f0cf9c2 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a   
+0608000c   
 6000 00407900 60040a00 21046000
    00038000
  001b7200  
 
 #disable IFC, enable QSPI and DSPI
-#0608000a   
+#0608000c   
 #6000 00407900 60040a00 21046000
 #   00038000
 #20024800 001b7200  
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 
b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
index 2bd398c..10cc4a9 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-#0608000a   
+#0608000c   
 #6000 00407900 60040a00 21046000
 #   00038000
 # 001b7200  
 
 #disable IFC, enable QSPI and DSPI
-0608000a   
+0608000c   
 6000 00407900 60040a00 21046000
    00038000
 20024800 001b7200  
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 
b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
index 205606f..f94997d 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a   
+0608000c   
 3000 7900 60040a00 21046000
    2000
 0008 881b7340  
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 
b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
index 6767e09..541b604 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #disable IFC, enable QSPI and DSPI
-0608000a   
+0608000c   
 3000 7900 60040a00 21046000
    2000
 20024800 881b7340  
-- 
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[U-Boot] [PATCH v2] armv8: fsl-layerscape: Add Readme for deploy QSPI image

2016-11-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Move the readme for QSPI deploy out of only for ls2080aqds.
---
 .../arm/cpu/armv8/fsl-layerscape/doc/README.deploy | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy
new file mode 100644
index 000..25813b3
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy
@@ -0,0 +1,44 @@
+Boot source support Overview
+---
+   1. LS1043A
+   LS1043AQDS:QSPI, SD, NOR, NAND
+   LS1043ARDB:SD, NOR, NAND
+   2. LS2080A
+   LS2080AQDS:QSPI, SD, NOR, NAND
+   LS2080ARDB:NOR, NAND
+   3. LS1012A
+   LS1012AQDS:QSPI
+   LS1012ARDB:QSPI
+   4. LS1046A
+   LS1046AQDS:QSPI, SD, NOR, NAND
+   LS1046ARDB:QSPI, SD
+
+Booting from QSPI
+---
+Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
+The difference between QSPI boot RCW image and NOR boot image is the PBI
+command sequence for setting the boot location pointer. It's should point
+to the address for u-boot in QSPI flash.
+
+RCW image should be written to the beginning of QSPI flash device.
+Example of using u-boot command
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 0 +
+SF: 65536 bytes @ 0x0 Erased: OK
+=> sf write  0 
+SF: 164 bytes @ 0x0 Written: OK
+
+To get the QSPI image, build u-boot with QSPI config, for example,
+_qspi_defconfig. The image needed is u-boot-dtb.bin.
+The u-boot image should be written to 0x1(but 0x1000 for LS1043A, LS2080A).
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 1 +
+SF: 589824 bytes @ 0x1 Erased: OK
+=> sf write  1 
+SF: 580966 bytes @ 0x1 Written: OK
+
+With these two images in QSPI flash device, the board can boot from QSPI.
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: QSPI: Add AHB bus 16MB+ size support

2016-10-25 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 37 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 include/configs/ls1012a_common.h   |  1 +
 include/configs/ls1046ardb.h   |  1 +
 5 files changed, 41 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d68eeba..18d753e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -370,6 +370,40 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+   u32 *qspi_lut, lut_key, *qspi_key;
+
+   qspi_key = (void *)CONFIG_SYS_QSPI_ADDR + 0x300;
+   qspi_lut = (void *)CONFIG_SYS_QSPI_ADDR + 0x310;
+
+   lut_key = in_be32(qspi_key);
+
+   if (lut_key == 0x5af05af0) {
+   /* That means the register is BE */
+   out_be32(qspi_key, 0x5af05af0);
+   out_be32(qspi_key + 1, 0x0002);
+   out_be32(qspi_lut, 0x0820040c);
+   out_be32(qspi_lut + 1, 0x1c080c08);
+   out_be32(qspi_lut + 2, 0x2400);
+   out_be32(qspi_key, 0x5af05af0);
+   out_be32(qspi_key + 1, 0x0001);
+   } else {
+   /* That means the register is LE */
+   out_le32(qspi_key, 0x5af05af0);
+   out_le32(qspi_key + 1, 0x0002);
+   out_le32(qspi_lut, 0x0820040c);
+   out_le32(qspi_lut + 1, 0x1c080c08);
+   out_le32(qspi_lut + 2, 0x2400);
+   out_le32(qspi_key, 0x5af05af0);
+   out_le32(qspi_key + 1, 0x0001);
+   }
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -379,6 +413,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+   qspi_ahb_init();
+#endif
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..a28b1fd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x0040)
 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0053)
+#define CONFIG_SYS_QSPI_ADDR   (CONFIG_SYS_IMMR + 0x0055)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0056)
 #define CONFIG_SYS_FSL_CSU_ADDR(CONFIG_SYS_IMMR + 
0x0051)
 #define CONFIG_SYS_FSL_GUTS_ADDR   (CONFIG_SYS_IMMR + 0x00ee)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..8aefc76 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR   (CONFIG_SYS_IMMR + 0x0030)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR   (CONFIG_SYS_IMMR + 0x0031)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR   (CONFIG_SYS_IMMR + 0x0037)
+#define CONFIG_SYS_QSPI_ADDR   (CONFIG_SYS_IMMR + 0x010c)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0114)
 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0124)
 #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 
0x011C0500)
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 80603c9..c1e1102 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -61,6 +61,7 @@
 
 #define FSL_QSPI_FLASH_SIZE(1 << 24)
 #define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_QSPI_AHB_INIT
 
 /*
  * Environment
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 2fe8fc1..662ecb1 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -209,6 +209,7 @@
 #define FSL_QSPI_FLASH_SIZE(1 << 26)
 #define FSL_QSPI_FLASH_NUM 2
 #define CONFIG_SPI_FLASH_BAR
+#define CONFIG_QSPI_AHB_INIT
 #endif
 
 /* SATA */
-- 
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[U-Boot] [PATCH] board/ls2080qds: add the procedure to deply QSPI image.

2016-10-11 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 board/freescale/ls2080aqds/README | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/board/freescale/ls2080aqds/README 
b/board/freescale/ls2080aqds/README
index f288750..0f7446a 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -188,3 +188,38 @@ DPMAC14 -> PHY4-P1
 DPMAC15 -> PHY4-P2
 DPMAC16 -> PHY4-P3
 
+
+Booting from QSPI
+---
+Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
+The difference between QSPI boot RCW image and NOR boot image is the PBI
+command sequence. Below is the setting for PBI commands for QDS which boot
+on QSPI flash device.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x
+2) CCSR 4-byte write to 0x00e00400, data=0x2001
+The above two commands set bootloc register to 0x_2001 where
+the u-boot code will be running in QSPI flash.
+
+RCW image should be written to the beginning of QSPI flash device.
+Example of using u-boot command
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 0 +
+SF: 65536 bytes @ 0x0 Erased: OK
+=> sf write  0 
+SF: 164 bytes @ 0x0 Written: OK
+
+To get the QSPI image, build u-boot with QSPI config, for example,
+ls2080aqds_qspi_defconfig. The image needed is u-boot-dtb.bin.
+The u-boot image should be written to 0x1.
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 1 +
+SF: 589824 bytes @ 0x1 Erased: OK
+=> sf write  1 
+SF: 580966 bytes @ 0x1 Written: OK
+
+With these two images in QSPI flash device, the board can boot from QSPI.
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] ls1021a: QSPI: update the node for QSPI support

2016-10-11 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add the address value and size value name for QSPI dts node.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/ls1021a.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1af..37be169 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -176,6 +176,7 @@
#size-cells = <0>;
reg = <0x155 0x1>,
<0x4000 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
-- 
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[U-Boot] [PATCH] configs: ls2080ardb: Enable DSPI flash support

2016-10-10 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

There is the stmicro DSPI flash on LS12080ARDB.
Enable DSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080ardb.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b93e919..90e31d4 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -271,6 +271,7 @@ unsigned long get_board_sys_clk(void);
 #ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_STMICRO
 #endif
 
 /*
-- 
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[U-Boot] [PATCH v1 2/4] spi: fsl_qspi: Add 4bytes address support

2016-09-28 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The QSPI support the direct 4bytes address command for flash
read/write/erase.
And the address can cover the whole QSPI memory space.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/spi/fsl_qspi.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 2144fca..119b782 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE 0x40
 #endif
 
-#define OFFSET_BITS_MASK   GENMASK(23, 0)
+#define OFFSET_BITS_MASK   ((FSL_QSPI_FLASH_SIZE  > SZ_16M) ? \
+   GENMASK(27, 0) :  GENMASK(23, 0))
 
 #define FLASH_STATUS_WEL   0x02
 
@@ -760,7 +761,10 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int 
bitlen,
if (dout) {
if (flags & SPI_XFER_BEGIN) {
priv->cur_seqid = *(u8 *)dout;
-   memcpy(, dout, 4);
+   if (FSL_QSPI_FLASH_SIZE  > SZ_16M)
+   memcpy(, dout + 1, 4);
+   else
+   memcpy(, dout, 4);
}
 
if (flags == SPI_XFER_END) {
-- 
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[U-Boot] [PATCH v1 4/4] armv8: ls1046a: update the flash size to 64M.

2016-09-28 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The QSPI flash on LS1046A is 64MB, and don't support BAR.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls1046ardb.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 693cc8d..3322953 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -209,9 +209,8 @@
 /* QSPI device */
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE(1 << 26)
+#define FSL_QSPI_FLASH_SIZESZ_64M
 #define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_BAR
 #endif
 
 /* SATA */
-- 
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[U-Boot] [PATCH v1 1/4] sf: add ADDR_4B for 4byte address support

2016-09-28 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Some new flash don't support bar register but use 4bytes address to
support exceed 16MB flash size.
So add flash flag:
ADDR_4B
for some flash which support 4bytes address.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/mtd/spi/sf_internal.h |  4 +++-
 drivers/mtd/spi/sf_params.c   |  2 +-
 drivers/mtd/spi/spi_flash.c   | 38 +-
 include/spi_flash.h   |  1 +
 4 files changed, 30 insertions(+), 15 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index cde4cfb..9ae1549 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -26,7 +26,8 @@ enum spi_nor_option_flags {
 };
 
 #define SPI_FLASH_3B_ADDR_LEN  3
-#define SPI_FLASH_CMD_LEN  (1 + SPI_FLASH_3B_ADDR_LEN)
+#define SPI_FLASH_4B_ADDR_LEN  4
+#define SPI_FLASH_CMD_MAX_LEN  (1 + SPI_FLASH_4B_ADDR_LEN)
 #define SPI_FLASH_16MB_BOUN0x100
 
 /* CFI Manufacture ID's */
@@ -130,6 +131,7 @@ struct spi_flash_params {
 #define RD_DUALBIT(5)
 #define RD_QUADIO  BIT(6)
 #define RD_DUALIO  BIT(7)
+#define ADDR_4BBIT(8)
 #define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO | 
RD_DUALIO)
 };
 
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 5b50114..9c26cc8 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -68,7 +68,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"S25FL128S_64K",  0x012018, 0x4d01,64 * 1024,   256, RD_FULL | 
WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL | 
WR_QPP},
{"S25FL256S_64K",  0x010219, 0x4d01,64 * 1024,   512, RD_FULL | 
WR_QPP},
-   {"S25FS512S",  0x010220, 0x4D00,   128 * 1024,   512, RD_FULL | 
WR_QPP},
+   {"S25FS512S",  0x010220, 0x4D00,   128 * 1024,   512, RD_FULL | 
WR_QPP | ADDR_4B},
{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL | 
WR_QPP},
{"S25FL512S_64K",  0x010220, 0x4d01,64 * 1024,  1024, RD_FULL | 
WR_QPP},
{"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL | 
WR_QPP},
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7f6e9ae..487488f 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -22,12 +22,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd)
 {
/* cmd[0] is actual command */
-   cmd[1] = addr >> 16;
-   cmd[2] = addr >> 8;
-   cmd[3] = addr >> 0;
+   int i;
+
+   for (i = flash->cmd_len - 1; i > 0; i--) {
+   cmd[i] = addr;
+   addr = addr >> 8;
+   }
 }
 
 static int read_sr(struct spi_flash *flash, u8 *rs)
@@ -327,7 +330,7 @@ int spi_flash_write_common(struct spi_flash *flash, const 
u8 *cmd,
 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 {
u32 erase_size, erase_addr;
-   u8 cmd[SPI_FLASH_CMD_LEN];
+   u8 cmd[SPI_FLASH_CMD_MAX_LEN];
int ret = -1;
 
erase_size = flash->erase_size;
@@ -357,7 +360,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 
offset, size_t len)
if (ret < 0)
return ret;
 #endif
-   spi_flash_addr(erase_addr, cmd);
+   spi_flash_addr(flash, erase_addr, cmd);
 
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
  cmd[2], cmd[3], erase_addr);
@@ -382,7 +385,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 
offset,
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
-   u8 cmd[SPI_FLASH_CMD_LEN];
+   u8 cmd[SPI_FLASH_CMD_MAX_LEN];
int ret = -1;
 
page_size = flash->page_size;
@@ -415,7 +418,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 
offset,
chunk_len = min(chunk_len,
(size_t)spi->max_write_size);
 
-   spi_flash_addr(write_addr, cmd);
+   spi_flash_addr(flash, write_addr, cmd);
 
debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = 
%zu\n",
  buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
@@ -492,7 +495,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 
offset,
return 0;
}
 
-   cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
+   cmdsz = flash->cmd_len + flash->dummy_byte;
cmd = calloc(1, cmdsz);
if (!cmd) {
debug("SF: Failed to al

[U-Boot] [PATCH v1 3/4] armv8: ls1012a: update the flash size to 64M.

2016-09-28 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The QSPI flash on LS1012A is 64MB, and don't support BAR.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls1012a_common.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 5fb6c47..4a900bf 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -60,9 +60,8 @@
 #define CONFIG_FSL_QSPI
 #define QSPI0_AMBA_BASE0x4000
 #define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_BAR
 
-#define FSL_QSPI_FLASH_SIZE(1 << 24)
+#define FSL_QSPI_FLASH_SIZESZ_64M
 #define FSL_QSPI_FLASH_NUM 2
 
 /*
-- 
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[U-Boot] [PATCH v1 0/4] sf: add ADDR_4B for 4byte address support

2016-09-28 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Some new flash don't support bar but use 4bytes address to direct
support exceed 16MB flash size. So add flash flag:
ADDR_4B
for some flash which support 4bytes address.

Yuan Yao (4):
  sf: add ADDR_4B for 4byte address support
  spi: fsl_qspi: Add 4bytes address support
  armv8: ls1012a: update the flash size to 64M.
  armv8: ls1046a: update the flash size to 64M.

 drivers/mtd/spi/sf_internal.h|  4 +++-
 drivers/mtd/spi/sf_params.c  |  2 +-
 drivers/mtd/spi/spi_flash.c  | 38 +-
 drivers/spi/fsl_qspi.c   |  8 ++--
 include/configs/ls1012a_common.h |  3 +--
 include/configs/ls1046ardb.h |  3 +--
 include/spi_flash.h  |  1 +
 7 files changed, 38 insertions(+), 21 deletions(-)

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 04/10] armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded clocks. 
---
 board/freescale/ls2080aqds/ls2080aqds.c |  3 +++
 include/configs/ls2080aqds.h| 10 ++
 2 files changed, 13 insertions(+)

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index d7acb48..19bb4c6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -219,6 +219,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+   i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
 #ifdef CONFIG_FSL_QSPI
/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..ccc987c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV0x7e
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR   0x66
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-- 
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[U-Boot] [PATCH v6 06/10] dm: dts: ls2080aqds: Add QSPI dts node

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 09/10] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v6:
Add CONFIG_CMD_SF in defconfig.
---
 configs/ls2080aqds_nand_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 1302313..d567878 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -18,6 +26,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 07/10] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 9 +
 include/configs/ls2080aqds.h   | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index bfff2ec..7c47cc8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,6 +128,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
 #define DCFG_RCWSR13   0x130
 #define DCFG_RCWSR13_DSPI  (0 << 8)
+#define DCFG_RCWSR15   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 19bb4c6..8bdcb04 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -208,6 +208,15 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+   if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+   QIXIS_WRITE(brdcfg[9],
+   (QIXIS_READ(brdcfg[9]) & 0xf8) |
+FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 8e193a6..7152c2b 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -303,6 +303,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM 4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
 
 #endif
 
-- 
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[U-Boot] [PATCH v6 10/10] armv8: ls2080aqds: Enable QSPI boot support

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v6:
Add CONFIG_CMD_SF in defconfig.
Changed in v4:
Merged the below patch into one:
board: freescale: ls2080aqds: Enable early I2C access for QSPI boot
Changed in v3:
1, Rebase to lastest code.
2, Give up to change the sequence for "show_board_info" in 
"init_sequence_f".
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 
 board/freescale/ls2080aqds/ls2080aqds.c|  2 ++
 configs/ls2080aqds_qspi_defconfig  | 28 ++
 include/configs/ls2080a_common.h   |  2 ++
 include/configs/ls2080aqds.h   | 10 +
 5 files changed, 46 insertions(+)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..f07a49a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -121,6 +121,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -175,6 +177,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 8bdcb04..23ebcc1 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -81,6 +81,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+   else if (sw == 0xf)
+   puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
diff --git a/configs/ls2080aqds_qspi_defconfig 
b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 000..194d280
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index eab410e..71f830a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE   0x8040
 #else
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 55d6c27..5dfba7a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#def

[U-Boot] [PATCH v6 08/10] configs: ls2080a: Increase load image len in NAND boot

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 48b1e15..eab410e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -283,7 +283,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 7152c2b..55d6c27 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
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[U-Boot] [PATCH v6 05/10] configs: ls2080aqds: Enable QSPI flash support

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v6:
remove CONFIG_CMD_SF.
---
 include/configs/ls2080aqds.h | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index ccc987c..8e193a6 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
+
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 03/10] configs: ls2080a_common: Remove duplicate NOR configs

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c78aeb5..48b1e15 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -138,13 +138,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aaf..7f245b5 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 02/10] armv8: ls2080aqds: Select QSPI CLK div via SCFG

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..bfff2ec 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,6 +139,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..d7acb48 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -219,6 +220,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 01/10] drivers: i2c: mxc: Add early init

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add early i2c init function with conservative divider when the exact
clock rate is not available.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
New add in v3.
---
 drivers/i2c/i2c_core.c |  5 +
 drivers/i2c/mxc_i2c.c  | 27 +++
 include/i2c.h  |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8..16b1aba 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21..f340208 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT   2
 #define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX   0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE  CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE  0x7e
+#endif
+
 /* Register index */
 #define IADR   0
 #define IFDR   1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
 }
 
 /*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+   ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+   bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+   & I2C_QUIRK_FLAG ? true : false;
+   int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+   /* Set I2C divider value */
+   writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+   /* Reset module */
+   writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+   writeb(0, base + (I2SR << reg_shift));
+   /* Enable I2C */
+   writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
  * Init I2C Bus
  */
 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae45..d500445 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose  i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 00/10] armv8: ls2080aqds: Enable QSPI boot support

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Yuan Yao (10):
  drivers: i2c: mxc: Add early init
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
  configs: ls2080aqds: Enable QSPI flash support
Changed in v6.
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
Changed in v6.
  armv8: ls2080aqds: Enable QSPI boot support
Changed in v6.

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 19 ++
 configs/ls2080aqds_nand_defconfig  |  8 
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 drivers/i2c/i2c_core.c |  5 +++
 drivers/i2c/mxc_i2c.c  | 27 ++
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 include/i2c.h  |  3 ++
 13 files changed, 171 insertions(+), 10 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 09/10] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 configs/ls2080aqds_nand_defconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 1302313..32f35cc 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 08/10] configs: ls2080a: Increase load image len in NAND boot

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 48b1e15..eab410e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -283,7 +283,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 13e18db..b28cf36 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 10/10] armv8: ls2080aqds: Enable QSPI boot support

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v4:
Merged the below patch into one:
board: freescale: ls2080aqds: Enable early I2C access for QSPI boot
Changed in v3:
1, Rebase to lastest code.
2, Give up to change the sequence for "show_board_info" in 
"init_sequence_f".
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 
 board/freescale/ls2080aqds/ls2080aqds.c|  2 ++
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 include/configs/ls2080a_common.h   |  2 ++
 include/configs/ls2080aqds.h   | 10 ++
 5 files changed, 45 insertions(+)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..f07a49a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -121,6 +121,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -175,6 +177,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 8bdcb04..23ebcc1 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -81,6 +81,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+   else if (sw == 0xf)
+   puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
diff --git a/configs/ls2080aqds_qspi_defconfig 
b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 000..40a2cd9
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index eab410e..71f830a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE   0x8040
 #else
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index b28cf36..97afda6 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_QSPI 0x62
 #defineQIXIS_RST_FORCE

[U-Boot] [PATCH v5 06/10] dm: dts: ls2080aqds: Add QSPI dts node

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v5 07/10] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 9 +
 include/configs/ls2080aqds.h   | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index bfff2ec..7c47cc8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,6 +128,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
 #define DCFG_RCWSR13   0x130
 #define DCFG_RCWSR13_DSPI  (0 << 8)
+#define DCFG_RCWSR15   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 19bb4c6..8bdcb04 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -208,6 +208,15 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+   if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+   QIXIS_WRITE(brdcfg[9],
+   (QIXIS_READ(brdcfg[9]) & 0xf8) |
+FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index f917484..13e18db 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -304,6 +304,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM 4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
 #endif
 
 /*
-- 
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[U-Boot] [PATCH v5 04/10] armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded clocks. 
---
 board/freescale/ls2080aqds/ls2080aqds.c |  3 +++
 include/configs/ls2080aqds.h| 10 ++
 2 files changed, 13 insertions(+)

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index d7acb48..19bb4c6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -219,6 +219,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+   i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
 #ifdef CONFIG_FSL_QSPI
/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..99b0551 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR   0x66
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV0x7e
+#endif
+
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-- 
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[U-Boot] [PATCH v5 01/10] drivers: i2c: mxc: Add early init

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add early i2c init function with conservative divider when the exact
clock rate is not available.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
New add in v3.
---
 drivers/i2c/i2c_core.c |  5 +
 drivers/i2c/mxc_i2c.c  | 27 +++
 include/i2c.h  |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8..16b1aba 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21..f340208 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT   2
 #define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX   0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE  CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE  0x7e
+#endif
+
 /* Register index */
 #define IADR   0
 #define IFDR   1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
 }
 
 /*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+   ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+   bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+   & I2C_QUIRK_FLAG ? true : false;
+   int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+   /* Set I2C divider value */
+   writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+   /* Reset module */
+   writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+   writeb(0, base + (I2SR << reg_shift));
+   /* Enable I2C */
+   writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
  * Init I2C Bus
  */
 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae45..d500445 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose  i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-- 
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[U-Boot] [PATCH v5 05/10] configs: ls2080aqds: Enable QSPI flash support

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 99b0551..f917484 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+#define CONFIG_CMD_SF
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
 #endif
 
 /*
-- 
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[U-Boot] [PATCH v5 00/10] armv8: ls2080aqds: Enable QSPI boot support

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Yuan Yao (10):
  drivers: i2c: mxc: Add early init
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
Changed in v5.
  configs: ls2080aqds: Enable QSPI flash support
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
  armv8: ls2080aqds: Enable QSPI boot support

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 19 ++
 configs/ls2080aqds_nand_defconfig  |  8 
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 drivers/i2c/i2c_core.c |  5 +++
 drivers/i2c/mxc_i2c.c  | 27 ++
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 include/i2c.h  |  3 ++
 13 files changed, 171 insertions(+), 10 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
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[U-Boot] [PATCH v5 02/10] armv8: ls2080aqds: Select QSPI CLK div via SCFG

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..bfff2ec 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,6 +139,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..d7acb48 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -219,6 +220,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
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[U-Boot] [PATCH v5 03/10] configs: ls2080a_common: Remove duplicate NOR configs

2016-06-08 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c78aeb5..48b1e15 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -138,13 +138,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aaf..7f245b5 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
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[U-Boot] [PATCH v4 10/10] armv8: ls2080aqds: Enable QSPI boot support

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
1, Rebase to lastest code.
2, Give up to change the sequence for "show_board_info" in 
"init_sequence_f".
Changed in v4:
Merged the below patch into one:
board: freescale: ls2080aqds: Enable early I2C access for QSPI boot
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 
 board/freescale/ls2080aqds/ls2080aqds.c|  5 +
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 include/configs/ls2080a_common.h   |  2 ++
 include/configs/ls2080aqds.h   | 18 +
 5 files changed, 52 insertions(+), 4 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..f07a49a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -121,6 +121,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -175,6 +177,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 80a6e93..23ebcc1 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -81,6 +81,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+   else if (sw == 0xf)
+   puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
@@ -228,6 +230,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+   i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
 #ifdef CONFIG_FSL_QSPI
/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/configs/ls2080aqds_qspi_defconfig 
b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 000..40a2cd9
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index eab410e..71f830a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE   0x8040
 #else
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 0e54d37..97afda6 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -21,14 +21,14 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
-#define CONFIG_SYS_CLK_FREQ1
-#define CONFIG_DDR_CLK_FREQ1

[U-Boot] [PATCH v4 08/10] configs: ls2080a: Increase load image len in NAND boot

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 48b1e15..eab410e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -283,7 +283,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index bebbc88..0e54d37 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4 07/10] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 9 +
 include/configs/ls2080aqds.h   | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index bfff2ec..7c47cc8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,6 +128,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
 #define DCFG_RCWSR13   0x130
 #define DCFG_RCWSR13_DSPI  (0 << 8)
+#define DCFG_RCWSR15   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index d7acb48..80a6e93 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -208,6 +208,15 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+   if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+   QIXIS_WRITE(brdcfg[9],
+   (QIXIS_READ(brdcfg[9]) & 0xf8) |
+FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index c0c2a97..bebbc88 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -304,6 +304,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM 4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4 09/10] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 configs/ls2080aqds_nand_defconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 1302313..32f35cc 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4 04/10] configs: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC
due to pin mux.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..a14b465 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,8 +17,18 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_CLK_FREQ1
+#define CONFIG_DDR_CLK_FREQ1
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR   0x66
+#else
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
+#endif
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
 
 #define CONFIG_DDR_SPD
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4 06/10] dm: dts: ls2080aqds: Add QSPI dts node

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4 05/10] configs: ls2080aqds: Enable QSPI flash support

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index a14b465..c0c2a97 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+#define CONFIG_CMD_SF
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
 #endif
 
 /*
-- 
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[U-Boot] [PATCH v4 01/10] drivers: i2c: mxc: Add early init

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add early i2c init function with conservative divider when the exact
clock rate is not available.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/i2c/i2c_core.c |  5 +
 drivers/i2c/mxc_i2c.c  | 27 +++
 include/i2c.h  |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8..16b1aba 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21..f340208 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT   2
 #define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX   0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE  CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE  0x7e
+#endif
+
 /* Register index */
 #define IADR   0
 #define IFDR   1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
 }
 
 /*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+   ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+   bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+   & I2C_QUIRK_FLAG ? true : false;
+   int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+   /* Set I2C divider value */
+   writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+   /* Reset module */
+   writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+   writeb(0, base + (I2SR << reg_shift));
+   /* Enable I2C */
+   writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
  * Init I2C Bus
  */
 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae45..d500445 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose  i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-- 
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[U-Boot] [PATCH v4 03/10] configs: ls2080a_common: Remove duplicate NOR configs

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c78aeb5..48b1e15 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -138,13 +138,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aaf..7f245b5 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
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[U-Boot] [PATCH v4 02/10] armv8: ls2080aqds: Select QSPI CLK div via SCFG

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..bfff2ec 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,6 +139,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..d7acb48 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -219,6 +220,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4 00/10] armv8: ls2080aqds: Enable QSPI boot support

2016-06-07 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Yuan Yao (10):
  drivers: i2c: mxc: Add early init
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  configs: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
  configs: ls2080aqds: Enable QSPI flash support
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
  armv8: ls2080aqds: Enable QSPI boot support
Changed in v4.

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 19 ++
 configs/ls2080aqds_nand_defconfig  |  8 
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 drivers/i2c/i2c_core.c |  5 +++
 drivers/i2c/mxc_i2c.c  | 27 ++
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 include/i2c.h  |  3 ++
 13 files changed, 171 insertions(+), 10 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
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[U-Boot] [PATCH v3 09/11] armv8: ls2080aqds: Enable QSPI boot support

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
1, Rebase to lastest code.
2, Give up to change the sequence for "show_board_info" in 
"init_sequence_f".
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 
 board/freescale/ls2080aqds/ls2080aqds.c|  2 ++
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 include/configs/ls2080a_common.h   |  2 ++
 include/configs/ls2080aqds.h   | 10 ++
 5 files changed, 45 insertions(+)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..f07a49a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -121,6 +121,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -175,6 +177,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 80a6e93..45dc298 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -81,6 +81,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+   else if (sw == 0xf)
+   puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
diff --git a/configs/ls2080aqds_qspi_defconfig 
b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 000..40a2cd9
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index eab410e..71f830a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE   0x8040
 #else
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 0e54d37..adb6901 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_QSPI 0x62
 #defineQIXIS_RST_FORCE_MEM 0x01
 
 #define CONFIG_SYS_CSPR3_EXT   (0x0)
@@ -267,11 +269,19 @@ unsigned long get_board_ddr_clk(void);

[U-Boot] [PATCH v3 04/11] configs: ls2080aqds: Enable QSPI flash support

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index a14b465..c0c2a97 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+#define CONFIG_CMD_SF
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 05/11] dm: dts: ls2080aqds: Add QSPI dts node

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 01/11] armv8: ls2080aqds: Select QSPI CLK div via SCFG

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..bfff2ec 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,6 +139,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..d7acb48 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -219,6 +220,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 06/11] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 9 +
 include/configs/ls2080aqds.h   | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index bfff2ec..7c47cc8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,6 +128,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
 #define DCFG_RCWSR13   0x130
 #define DCFG_RCWSR13_DSPI  (0 << 8)
+#define DCFG_RCWSR15   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index d7acb48..80a6e93 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -208,6 +208,15 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+   if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+   QIXIS_WRITE(brdcfg[9],
+   (QIXIS_READ(brdcfg[9]) & 0xf8) |
+FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index c0c2a97..bebbc88 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -304,6 +304,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM 4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
 #endif
 
 /*
-- 
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[U-Boot] [PATCH v3 03/11] configs: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC
due to pin mux.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..a14b465 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,8 +17,18 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_CLK_FREQ1
+#define CONFIG_DDR_CLK_FREQ1
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR   0x66
+#else
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
+#endif
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
 
 #define CONFIG_DDR_SPD
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 08/11] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 configs/ls2080aqds_nand_defconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index 1302313..32f35cc 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 11/11] board: freescale: ls2080aqds: Enable early I2C access for QSPI boot

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

When QSPI boot is used, board FPGA is not accessible from IFC.
To use I2C interface instead, i2c needs to be initialized before knowing
the exact clock rate.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
New add in v3.
---
 board/freescale/ls2080aqds/ls2080aqds.c | 3 +++
 include/configs/ls2080aqds.h| 8 
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 45dc298..23ebcc1 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -230,6 +230,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+   i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
 #ifdef CONFIG_FSL_QSPI
/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index adb6901..97afda6 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -21,14 +21,14 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
-#define CONFIG_SYS_CLK_FREQ1
-#define CONFIG_DDR_CLK_FREQ1
 #define CONFIG_QIXIS_I2C_ACCESS
 #define CONFIG_SYS_I2C_FPGA_ADDR   0x66
-#else
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV0x7e
+#endif
+
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
-#endif
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
 
 #define CONFIG_DDR_SPD
-- 
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[U-Boot] [PATCH v3 10/11] drivers: i2c: mxc: Add early init

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add early i2c init function with conservative divider when the exact
clock rate is not available.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
New add in v3.
---
 drivers/i2c/i2c_core.c |  5 +
 drivers/i2c/mxc_i2c.c  | 27 +++
 include/i2c.h  |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8..16b1aba 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21..f340208 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT   2
 #define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX   0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE  CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE  0x7e
+#endif
+
 /* Register index */
 #define IADR   0
 #define IFDR   1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
 }
 
 /*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+   ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+   bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+   & I2C_QUIRK_FLAG ? true : false;
+   int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+   /* Set I2C divider value */
+   writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+   /* Reset module */
+   writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+   writeb(0, base + (I2SR << reg_shift));
+   /* Enable I2C */
+   writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
  * Init I2C Bus
  */
 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae45..d500445 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose  i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 00/11] armv8: ls2080aqds: Enable QSPI boot support

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Yuan Yao (11):
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  configs: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
  configs: ls2080aqds: Enable QSPI flash support
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
  armv8: ls2080aqds: Enable QSPI boot support
Rebase in v3.
  drivers: i2c: mxc: Add early init
New add in v3.
  board: freescale: ls2080aqds: Enable early I2C access for QSPI boot
New add in v3.

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 19 ++
 configs/ls2080aqds_nand_defconfig  |  8 
 configs/ls2080aqds_qspi_defconfig  | 27 ++
 drivers/i2c/i2c_core.c |  5 +++
 drivers/i2c/mxc_i2c.c  | 27 ++
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 include/i2c.h  |  3 ++
 13 files changed, 171 insertions(+), 10 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 07/11] configs: ls2080a: Increase load image len in NAND boot

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 48b1e15..eab410e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -283,7 +283,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index bebbc88..0e54d37 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 02/11] configs: ls2080a_common: Remove duplicate NOR configs

2016-06-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c78aeb5..48b1e15 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -138,13 +138,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aaf..7f245b5 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/5] spi: fsl_qspi: Enable Spansion S25FS-S family flashes

2016-03-15 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The flash type of LS2085AQDS QSPI is S25FS256S.
It has special write any device register command and read any device register
command.
This patch enable support for those commands.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com>
Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/mtd/spi/sf_internal.h |  5 
 drivers/spi/fsl_qspi.c| 58 ++-
 2 files changed, 57 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 007a5a0..da2bb7b 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -127,6 +127,11 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
const void *buf);
 #endif
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+/* Used for Spansion S25FS-S family flash only. */
+#define CMD_SPANSION_RDAR  0x65 /* Read any device register */
+#define CMD_SPANSION_WRAR  0x71 /* Write any device register */
+#endif
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index db7ebee..75cbab2 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -44,6 +44,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SEQID_RDEAR11
 #define SEQID_WREAR12
 #endif
+#define SEQID_WRAR 13
+#define SEQID_RDAR 14
 
 /* QSPI CMD */
 #define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
@@ -63,6 +65,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #defineQSPI_CMD_BRRD   0x16/* Bank register read */
 #defineQSPI_CMD_BRWR   0x17/* Bank register write */
 
+/* Used for Spansion S25FS-S family flash only. */
+#define QSPI_CMD_RDAR  0x65/* Read any device register */
+#define QSPI_CMD_WRAR  0x71/* Write any device register */
+
 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
 #define QSPI_CMD_FAST_READ_4B  0x0c/* Read data bytes (high frequency) */
 #define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
@@ -317,6 +323,33 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 #endif
+
+   /*
+* Read any device register.
+* Used for Spansion S25FS-S family flash only.
+*/
+   lut_base = SEQID_RDAR * 4;
+   qspi_write32(priv->flags, >lut[lut_base],
+OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
+INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+   qspi_write32(priv->flags, >lut[lut_base + 1],
+OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
+OPRND1(1) | PAD1(LUT_PAD1) |
+INSTR1(LUT_READ));
+
+   /*
+* Write any device register.
+* Used for Spansion S25FS-S family flash only.
+*/
+   lut_base = SEQID_WRAR * 4;
+   qspi_write32(priv->flags, >lut[lut_base],
+OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
+INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+   qspi_write32(priv->flags, >lut[lut_base + 1],
+OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+
/* Lock the LUT */
qspi_write32(priv->flags, >lutkey, LUT_KEY_VALUE);
qspi_write32(priv->flags, >lckcr, QSPI_LCKCR_LOCK);
@@ -510,7 +543,6 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 
*rxbuf, u32 len)
qspi_write32(priv->flags, >mcr, mcr_reg);
 }
 
-#ifndef CONFIG_SYS_FSL_QSPI_AHB
 /* If not use AHB read, read data from ip interface */
 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 {
@@ -518,6 +550,12 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 
*rxbuf, u32 len)
u32 mcr_reg, data;
int i, size;
u32 to_or_from;
+   u32 seqid;
+
+   if (priv->cur_seqid == QSPI_CMD_RDAR)
+   seqid = SEQID_RDAR;
+   else
+   seqid = SEQID_FAST_READ;
 
mcr_reg = qspi_read32(priv->flags, >mcr);
qspi_write32(priv->flags, >mcr,
@@ -536,7 +574,7 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 
*rxbuf, u32 len)
RX_BUFFER_SIZE : len;
 
qspi_write32(priv->flags, >ipcr,
-(SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) |
+(seqid << QSPI_IPCR_SEQID_SHIFT) |
 size);
while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
;
@@ -548,

[U-Boot] [PATCH 5/5] armv8/ls1043a: update the node for QSPI support

2016-03-15 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The address value and size value set for QSPI dts node "reg"
property have type of u64 on arm64.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/fsl-ls1043a.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 66b409a..bf1dfe6 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -240,8 +240,9 @@
compatible = "fsl,vf610-qspi";
#address-cells = <1>;
#size-cells = <0>;
-   reg = <0x155 0x1>,
-   <0x4000 0x400>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/4] spi: fsl_qspi: Fix issues on arm64

2016-03-15 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The address value and size value get from dts "reg" property have type
of u64 on arm64.
If we assign those values to "u32" variables, driver can't work correctly.
Converting the type of those variables to fdt_xxx_t.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com>
Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/spi/fsl_qspi.c | 46 +++---
 1 file changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index cb8d929..96fb909 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -92,9 +92,9 @@ DECLARE_GLOBAL_DATA_PTR;
 struct fsl_qspi_platdata {
u32 flags;
u32 speed_hz;
-   u32 reg_base;
-   u32 amba_base;
-   u32 amba_total_size;
+   fdt_addr_t reg_base;
+   fdt_addr_t amba_base;
+   fdt_size_t amba_total_size;
u32 flash_num;
u32 num_chipselect;
 };
@@ -940,8 +940,13 @@ static int fsl_qspi_probe(struct udevice *bus)
priv->flags = plat->flags;
 
priv->speed_hz = plat->speed_hz;
-   priv->amba_base[0] = plat->amba_base;
-   priv->amba_total_size = plat->amba_total_size;
+   /*
+* QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
+* AMBA memory zone should be located on the 0~4GB space
+* even on a 64bits cpu.
+*/
+   priv->amba_base[0] = (u32)plat->amba_base;
+   priv->amba_total_size = (u32)plat->amba_total_size;
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
 
@@ -984,10 +989,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 {
-   struct reg_data {
-   u32 addr;
-   u32 size;
-   } regs_data[2];
+   struct fdt_resource res_regs, res_mem;
struct fsl_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
@@ -996,10 +998,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice 
*bus)
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 
-   ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
-  sizeof(regs_data)/sizeof(u32));
+   ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+"QuadSPI", _regs);
+   if (ret) {
+   debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+   return -ENOMEM;
+   }
+   ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+"QuadSPI-memory", _mem);
if (ret) {
-   debug("Error: can't get base addresses (ret = %d)!\n", ret);
+   debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
return -ENOMEM;
}
 
@@ -1017,16 +1025,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice 
*bus)
plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
  FSL_QSPI_MAX_CHIPSELECT_NUM);
 
-   plat->reg_base = regs_data[0].addr;
-   plat->amba_base = regs_data[1].addr;
-   plat->amba_total_size = regs_data[1].size;
+   plat->reg_base = res_regs.start;
+   plat->amba_base = res_mem.start;
+   plat->amba_total_size = res_mem.end - res_mem.start + 1;
plat->flash_num = flash_num;
 
-   debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
+   debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, 
endianess=%s\n",
  __func__,
- plat->reg_base,
- plat->amba_base,
- plat->amba_total_size,
+ (u64)plat->reg_base,
+ (u64)plat->amba_base,
+ (u64)plat->amba_total_size,
  plat->speed_hz,
  plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
  );
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/5] spi: fsl_qspi: Assign AMBA mem according CS num in dts

2016-03-15 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

QSPI controller automatic enable the chipselect signal according the dest
AMBA memory address. Now we distribute the AMBA memory zone averagely to
every chipselect slave device according chipselect numbers got from dts
node.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com>
Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/spi/fsl_qspi.c | 55 +++---
 1 file changed, 43 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 96fb909..db7ebee 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -927,10 +927,11 @@ static int fsl_qspi_child_pre_probe(struct udevice *dev)
 
 static int fsl_qspi_probe(struct udevice *bus)
 {
-   u32 total_size;
+   u32 amba_size_per_chip;
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
+   int i;
 
dm_spi_bus = bus->uclass_priv;
 
@@ -956,7 +957,22 @@ static int fsl_qspi_probe(struct udevice *bus)
qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 
-   total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
+   /*
+* Assign AMBA memory zone for every chipselect
+* QuadSPI has two channels, every channel has two chipselects.
+* If the property 'num-cs' in dts is 2, the AMBA memory will be divided
+* into two parts and assign to every channel. This indicate that every
+* channel only has one valid chipselect.
+* If the property 'num-cs' in dts is 4, the AMBA memory will be divided
+* into four parts and assign to every chipselect.
+* Every channel will has two valid chipselects.
+*/
+   amba_size_per_chip = priv->amba_total_size >>
+(priv->num_chipselect >> 1);
+   for (i = 1 ; i < priv->num_chipselect ; i++)
+   priv->amba_base[i] =
+   amba_size_per_chip + priv->amba_base[i - 1];
+
/*
 * Any read access to non-implemented addresses will provide
 * undefined results.
@@ -967,14 +983,30 @@ static int fsl_qspi_probe(struct udevice *bus)
 * setting the size of these devices to 0.  This would ensure
 * that the complete memory map is assigned to only one flash device.
 */
-   qspi_write32(priv->flags, >regs->sfa1ad,
-FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-   qspi_write32(priv->flags, >regs->sfa2ad,
-FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-   qspi_write32(priv->flags, >regs->sfb1ad,
-total_size | priv->amba_base[0]);
-   qspi_write32(priv->flags, >regs->sfb2ad,
-total_size | priv->amba_base[0]);
+   qspi_write32(priv->flags, >regs->sfa1ad, priv->amba_base[1]);
+   switch (priv->num_chipselect) {
+   case 2:
+   qspi_write32(priv->flags, >regs->sfa2ad,
+priv->amba_base[1]);
+   qspi_write32(priv->flags, >regs->sfb1ad,
+priv->amba_base[1] + amba_size_per_chip);
+   qspi_write32(priv->flags, >regs->sfb2ad,
+priv->amba_base[1] + amba_size_per_chip);
+   break;
+   case 4:
+   qspi_write32(priv->flags, >regs->sfa2ad,
+priv->amba_base[2]);
+   qspi_write32(priv->flags, >regs->sfb1ad,
+priv->amba_base[3]);
+   qspi_write32(priv->flags, >regs->sfb2ad,
+priv->amba_base[3] + amba_size_per_chip);
+   break;
+   default:
+   debug("Error: Unsupported chipselect number %u!\n",
+ priv->num_chipselect);
+   qspi_module_disable(priv, 1);
+   return -EINVAL;
+   }
 
qspi_set_lut(priv);
 
@@ -1063,8 +1095,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
bus = dev->parent;
priv = dev_get_priv(bus);
 
-   priv->cur_amba_base =
-   priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs;
+   priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
qspi_module_disable(priv, 0);
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 4/5] sf: Disable 4-KB erase command for SPANSION S25FS-S family

2016-03-15 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The S25FS-S family physical sectors may be configured as a hybrid
combination of eight 4-kB parameter sectors at the top or bottom
of the address space with all but one of the remaining sectors
being uniform size.
The default status of the flash is in this hybrid architecture.
The parameter sectors and the uniform sectors have different erase
commands.
This patch disable the hybrid sector architecture then the flash will
has uniform sector size and uniform erase command.
This configuration is temporary, the flash will revert to hybrid
architecture after power on reset.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/mtd/spi/spi_flash.c | 72 +
 1 file changed, 72 insertions(+)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 2ae2e3c..01457de 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -970,6 +970,43 @@ int spi_flash_decode_fdt(const void *blob, struct 
spi_flash *flash)
 }
 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+{
+   u8 cmd[4];
+   u32 offset = 0x84; /* CR3V register offset */
+   u8 cr3v;
+   int ret;
+
+   cmd[0] = CMD_SPANSION_RDAR;
+   cmd[1] = offset >> 16;
+   cmd[2] = offset >> 8;
+   cmd[3] = offset >> 0;
+
+   ret = spi_flash_cmd_read(spi, cmd, 4, , 1);
+   if (ret)
+   return -EIO;
+   /* CR3V bit3: 4-KB Erase */
+   if (cr3v & 0x8)
+   return 0;
+
+   cmd[0] = CMD_SPANSION_WRAR;
+   cr3v |= 0x8;
+   ret = spi_flash_cmd_write(spi, cmd, 4, , 1);
+   if (ret)
+   return -EIO;
+
+   cmd[0] = CMD_SPANSION_RDAR;
+   ret = spi_flash_cmd_read(spi, cmd, 4, , 1);
+   if (ret)
+   return -EIO;
+   if (!(cr3v & 0x8))
+   return -EFAULT;
+
+   return 0;
+}
+#endif
+
 int spi_flash_scan(struct spi_flash *flash)
 {
struct spi_slave *spi = flash->spi;
@@ -1020,6 +1057,41 @@ int spi_flash_scan(struct spi_flash *flash)
return -EPROTONOSUPPORT;
}
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+   /*
+* The S25FS-S family physical sectors may be configured as a
+* hybrid combination of eight 4-kB parameter sectors
+* at the top or bottom of the address space with all
+* but one of the remaining sectors being uniform size.
+* The Parameter Sector Erase commands (20h or 21h) must
+* be used to erase the 4-kB parameter sectors individually.
+* The Sector (uniform sector) Erase commands (D8h or DCh)
+* must be used to erase any of the remaining
+* sectors, including the portion of highest or lowest address
+* sector that is not overlaid by the parameter sectors.
+* The uniform sector erase command has no effect on parameter sectors.
+*/
+   if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+   int ret;
+   u8 id[6];
+
+   /* Read the ID codes again, 6 bytes */
+   ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+   if (ret)
+   return -EIO;
+
+   ret = memcmp(id, idcode, 5);
+   if (ret)
+   return -EIO;
+
+   /* 0x81: S25FS-S family 0x80: S25FL-S family */
+   if (id[5] == 0x81) {
+   ret = spansion_s25fss_disable_4KB_erase(spi);
+   if (ret)
+   return ret;
+   }
+   }
+#endif
/* Flash powers up read-only, so clear BP# bits */
if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
-- 
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[U-Boot] [PATCH 0/5] Add QSPI support for LS2080A

2016-03-15 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

There is the spansion S25FS-S family flash: s25fs256s1
on LS2080QDS QSPI.

Yuan Yao (5):
  spi: fsl_qspi: Fix issues on arm64
  spi: fsl_qspi: Assign AMBA mem according CS num in dts
  spi: fsl_qspi: Enable Spansion S25FS-S family flashes
  sf: Disable 4-KB erase command for SPANSION S25FS-S family
  armv8/ls1043a: update the node for QSPI support

 arch/arm/dts/fsl-ls1043a.dtsi |   5 +-
 drivers/mtd/spi/sf_internal.h |   5 ++
 drivers/mtd/spi/spi_flash.c   |  72 +++
 drivers/spi/fsl_qspi.c| 159 --
 4 files changed, 202 insertions(+), 39 deletions(-)

-- 
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[U-Boot] [PATCH 0/5] Add QSPI support for LS2080A

2016-03-15 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

There is the spansion S25FS-S family flash: s25fs256s1
on LS2080QDS QSPI.

Haikun Wang (3):
  spi: fsl_qspi: Fix issues on arm64
  spi: fsl_qspi: Assign AMBA mem according CS num in dts
  spi: fsl_qspi: Enable Spansion S25FS-S family flashes

Yuan Yao (2):
  sf: Disable 4-KB erase command for SPANSION S25FS-S family
  armv8/ls1043a: update the node for QSPI support

 arch/arm/dts/fsl-ls1043a.dtsi |   5 +-
 drivers/mtd/spi/sf_internal.h |   5 ++
 drivers/mtd/spi/spi_flash.c   |  72 +++
 drivers/spi/fsl_qspi.c| 159 --
 4 files changed, 202 insertions(+), 39 deletions(-)

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 11/11] freescale: cmd: qixis: tidy up the duplicated code

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 board/freescale/common/qixis.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..de9daeb 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -211,8 +211,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_NAND);
set_rcw_src(QIXIS_RCW_SRC_NAND);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -222,8 +221,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -233,8 +231,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD_QSPI);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -244,8 +241,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_QSPI);
set_rcw_src(QIXIS_RCW_SRC_QSPI);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 10/11] board/ls2080qds: add the procedure to deply QSPI image.

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 board/freescale/ls2080aqds/README | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/board/freescale/ls2080aqds/README 
b/board/freescale/ls2080aqds/README
index 6ddad92..21e8c7b 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -227,3 +227,38 @@ DPMAC14 -> PHY4-P1
 DPMAC15 -> PHY4-P2
 DPMAC16 -> PHY4-P3
 
+
+Booting from QSPI
+---
+Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
+The difference between QSPI boot RCW image and NOR boot image is the PBI
+command sequence. Below is the setting for PBI commands for QDS which boot
+on QSPI flash device.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x
+2) CCSR 4-byte write to 0x00e00400, data=0x2001
+The above two commands set bootloc register to 0x_2001 where
+the u-boot code will be running in QSPI flash.
+
+RCW image should be written to the beginning of QSPI flash device.
+Example of using u-boot command
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 0 +
+SF: 65536 bytes @ 0x0 Erased: OK
+=> sf write  0 
+SF: 164 bytes @ 0x0 Written: OK
+
+To get the QSPI image, build u-boot with QSPI config, for example,
+ls2080aqds_qspi_defconfig. The image needed is u-boot-dtb.bin.
+The u-boot image should be written to 0x1.
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 1 +
+SF: 589824 bytes @ 0x1 Erased: OK
+=> sf write  1 
+SF: 580966 bytes @ 0x1 Written: OK
+
+With these two images in QSPI flash device, the board can boot from QSPI.
-- 
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[U-Boot] [PATCH v2 08/11] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 configs/ls2080aqds_nand_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index b7d64f6..3a970b0 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -2,6 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
-- 
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[U-Boot] [PATCH v2 07/11] configs: ls2080a: Increase load image len in NAND boot

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 82af464..8048753 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -305,7 +305,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index ee51348..eaca55c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -240,7 +240,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
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[U-Boot] [PATCH v2 05/11] dm: dts: ls2080aqds: Add QSPI dts node

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 04/11] configs: ls2080aqds: Enable QSPI flash support

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 3edb0b9..3cba10a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -292,11 +292,22 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #endif
 
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
 /*
  * MMC
  */
-- 
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[U-Boot] [PATCH v2 01/11] armv8: ls2080aqds: Select QSPI CLK div via SCFG

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..e5acae8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -101,6 +101,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index aa256a2..6e73829 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -25,6 +25,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -218,6 +219,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 00/11] armv8: ls2080aqds: Enable QSPI boot support

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This series add support for QSPI boot on LS2080AQDS.

Yuan Yao (11):
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  configs: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
  configs: ls2080aqds: Enable QSPI flash support
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
  armv8: ls2080aqds: Enable QSPI boot support
Changed in v2:
 merged the patch:
 0009-armv8-ls2080aqds-Enable-QSPI-boot-support.patch
 0010-ls2080aqds-Enable-support-for-boot-from-QSPI.patch
 0012-LS2080QDS-QSPI-boot-fix-issues.patch
 in this patch.
  board/ls2080qds: add the procedure to deply QSPI image.
New add in v2.
  freescale: cmd: qixis: tidy up the duplicated code

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/common/qixis.c | 12 ++
 board/freescale/ls2080aqds/README  | 35 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 16 
 common/board_f.c   |  6 +--
 configs/ls2080aqds_nand_defconfig  |  9 +
 configs/ls2080aqds_qspi_defconfig  | 10 +
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 13 files changed, 159 insertions(+), 21 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
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[U-Boot] [PATCH v2 02/11] configs: ls2080a_common: Remove duplicate NOR configs

2016-03-06 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 64b82e8..82af464 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -148,13 +148,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 2c2ce7b..6a59afe 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -38,6 +38,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
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[U-Boot] [PATCH 01/12] armv8: ls2080aqds: Select QSPI CLK div via SCFG

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..e5acae8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -101,6 +101,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index aa256a2..6e73829 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -25,6 +25,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -218,6 +219,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 02/12] configs: ls2080a_common: Remove duplicate NOR configs

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 64b82e8..82af464 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -148,13 +148,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 2c2ce7b..6a59afe 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -38,6 +38,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
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[U-Boot] [PATCH 06/12] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

If we want to access QSPI flash when boot from NAND,
we need below board configuration:
Boot Source ISO1ISO2IBOOT
On-board NAND   1   0   0
IFCCARD NAND0   0   1

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 9 +
 include/configs/ls2080aqds.h   | 6 ++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e5acae8..828a53b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -94,6 +94,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR0x12f0
 #define DCFG_RCWSR13   0x130
 #define DCFG_RCWSR13_DSPI  (0 << 8)
+#define DCFG_RCWSR15   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
 #define DCFG_DCSR_PORCR1   0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 6e73829..7e09f11 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -207,6 +207,15 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+   val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+   if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+   QIXIS_WRITE(brdcfg[9],
+   (QIXIS_READ(brdcfg[9]) & 0xf8) |
+FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 3cba10a..ee51348 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -307,6 +307,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPI_FLASH_SPANSION
 #define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM 4
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
 #endif
 /*
  * MMC
-- 
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[U-Boot] [PATCH 10/12] ls2080aqds: Enable support for boot from QSPI

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 513a2e3..064e341 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -183,11 +183,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
 #define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_QSPI   0x0f
 #define QIXIS_RST_CTL_RESET0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_QSPI 0x62
 #defineQIXIS_RST_FORCE_MEM 0x01
 
 #define CONFIG_SYS_CSPR3_EXT   (0x0)
-- 
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[U-Boot] [PATCH 09/12] armv8: ls2080aqds: Enable QSPI boot support

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 configs/ls2080aqds_qspi_defconfig | 10 ++
 include/configs/ls2080a_common.h  |  2 ++
 include/configs/ls2080aqds.h  | 12 +++-
 3 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

diff --git a/configs/ls2080aqds_qspi_defconfig 
b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 000..8f84b23
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_QSPI=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 8048753..c131441 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_ARCH_MISC_INIT
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE   0x8040
 #else
 #define CONFIG_SYS_TEXT_BASE   0x3010
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index eaca55c..513a2e3 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,8 +17,16 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE   0x2001
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE0x2000  /* 8KB */
+#define CONFIG_ENV_OFFSET  0x10/* 1MB */
+#define CONFIG_ENV_SECT_SIZE   0x1
+#endif
 
-#ifdef CONFIG_FSL_QSPI
+#if defined(CONFIG_QSPI_BOOT) || \
+   (defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI))
 #define CONFIG_SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
 #define CONFIG_SYS_CLK_FREQ1
@@ -270,11 +278,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2   CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3   CONFIG_SYS_NAND_FTIM3
 
+#ifndef CONFIG_QSPI_BOOT
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR(CONFIG_SYS_FLASH_BASE + 
0x20)
 #define CONFIG_ENV_SECT_SIZE   0x2
 #define CONFIG_ENV_SIZE0x2000
 #endif
+#endif
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-- 
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[U-Boot] [PATCH 05/12] dm: dts: ls2080aqds: Add QSPI dts node

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
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[U-Boot] [PATCH 11/12] freescale: cmd: qixis: tidy up the duplicated code

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 board/freescale/common/qixis.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..de9daeb 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -211,8 +211,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_NAND);
set_rcw_src(QIXIS_RCW_SRC_NAND);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -222,8 +221,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -233,8 +231,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD_QSPI);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -244,8 +241,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_QSPI);
set_rcw_src(QIXIS_RCW_SRC_QSPI);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
-- 
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[U-Boot] [PATCH 04/12] configs: ls2080aqds: Enable QSPI flash support

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 3edb0b9..3cba10a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -292,11 +292,22 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #endif
 
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
 /*
  * MMC
  */
-- 
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[U-Boot] [PATCH 07/12] configs: ls2080a: Increase load image len in NAND boot

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 82af464..8048753 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -305,7 +305,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index ee51348..eaca55c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -240,7 +240,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
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[U-Boot] [PATCH 12/12] LS2080QDS: QSPI boot: fix issues.

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

This patch is used for fix the bug below:
/***/
"Synchronous Abort" handler, esr 0x86000210
ELR: fff6cfb4
LR:  fff6d3f0
x0 : 0022 x1 : fff78c6f
x2 : ffd0ecb0 x3 : 
x4 : ffd0ecd0 x5 : 
x6 : ffc8 x7 : 3fe0
x8 : 0083ffe0 x9 : 000c
x10: 0084 x11: 000c
x12: 0015 x13: 4000
x14: 0020 x15: 0001
x16: 1800f188 x17: 0001
x18: ffd11d78 x19: ffd0f010
x20: ffd0ed39 x21: fff80935
x22: fff78c6f x23: 0001
x24: ffd0f010 x25: ffd0ed38
x26: fff738e0 x27: fff72460
x28: fff92000 x29: ffd0ebd0

Resetting CPU ...
/***/

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 
 board/freescale/ls2080aqds/ls2080aqds.c| 2 ++
 common/board_f.c   | 6 +++---
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 15ade84..794b764 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -120,6 +120,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PMD_SECT_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
@@ -172,6 +174,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+   { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PMD_SECT_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index 7e09f11..8e174c3 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -80,6 +80,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+   else if (sw == 0xf)
+   puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
diff --git a/common/board_f.c b/common/board_f.c
index 622093a..1af1b4b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -912,9 +912,6 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_MPC5xxx)
prt_mpc5xxx_clks,
 #endif /* CONFIG_MPC5xxx */
-#if defined(CONFIG_DISPLAY_BOARDINFO)
-   show_board_info,
-#endif
INIT_FUNC_WATCHDOG_INIT
 #if defined(CONFIG_MISC_INIT_F)
misc_init_f,
@@ -923,6 +920,9 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
init_func_i2c,
 #endif
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+   show_board_info,
+#endif
 #if defined(CONFIG_HARD_SPI)
init_func_spi,
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 08/12] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 configs/ls2080aqds_nand_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index b7d64f6..3a970b0 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -2,6 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 00/12] Add SPI and QSPI boot for LS2080A

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

Yuan Yao (12):
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  configs: ls2080aqds: Disable IFC NOR & QIXIS when QSPI
  configs: ls2080aqds: Enable QSPI flash support
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
  armv8: ls2080aqds: Enable QSPI boot support
  ls2080aqds: Enable support for boot from QSPI
  freescale: cmd: qixis: tidy up the duplicated code
  LS2080QDS: QSPI boot: fix issues.

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/common/qixis.c | 12 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 16 
 common/board_f.c   |  6 +--
 configs/ls2080aqds_nand_defconfig  |  9 +
 configs/ls2080aqds_qspi_defconfig  | 10 +
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 12 files changed, 124 insertions(+), 21 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 03/12] configs: ls2080aqds: Disable IFC NOR & QIXIS when QSPI

2016-03-02 Thread Yuan Yao 
From: Yuan Yao <yao.y...@nxp.com>

When QSPI is enabled, NOR Flash and QIXIS can’t be accessed through IFC
due to pin muxing.

Enable QIXIS accessing through I2C.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 include/configs/ls2080aqds.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index dab3820..3edb0b9 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,8 +17,18 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_CLK_FREQ1
+#define CONFIG_DDR_CLK_FREQ1
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR   0x66
+#else
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
+#endif
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
 
 #define CONFIG_DDR_SPD
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file

2015-12-04 Thread Yuan Yao 
Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---

 arch/arm/cpu/armv7/ls102xa/Makefile |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +
 board/freescale/ls1021aqds/ls1021aqds.c | 49 +-
 board/freescale/ls1021atwr/ls1021atwr.c | 42 +---
 5 files changed, 83 insertions(+), 87 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile 
b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2311468..0228300 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -8,6 +8,7 @@ obj-y   += cpu.o
 obj-y  += clock.o
 obj-y  += timer.o
 obj-y  += fsl_epu.o
+obj-y  += soc.o
 
 obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
new file mode 100644
index 000..0fdd6d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+unsigned int get_soc_major_rev(void)
+{
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int svr, major;
+
+   svr = in_be32(>svr);
+   major = SVR_MAJ(svr);
+
+   return major;
+}
+
+int arch_soc_init(void)
+{
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+   struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+   unsigned int major;
+
+#ifdef CONFIG_FSL_QSPI
+   out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
+#ifdef CONFIG_FSL_DCU_FB
+   out_be32(>pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+   /* Configure Little endian for SAI, ASRC and SPDIF */
+   out_be32(>endiancr, SCFG_ENDIANCR_LE);
+
+   /*
+* Enable snoop requests and DVM message requests for
+* Slave insterface S4 (A7 core cluster)
+*/
+   out_le32(>slave[4].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+   major = get_soc_major_rev();
+   if (major == SOC_MAJOR_VER_1_0) {
+   /*
+* Set CCI-400 Slave interface S1, S2 Shareable Override
+* Register All transactions are treated as non-shareable
+*/
+   out_le32(>slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+   out_le32(>slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+   /* Workaround for the issue that DDR could not respond to
+* barrier transaction which is generated by executing DSB/ISB
+* instruction. Set CCI-400 control override register to
+* terminate the barrier transaction. After DDR is initialized,
+* allow barrier transaction to DDR again */
+   out_le32(>ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+   }
+
+   return 0;
+}
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h 
b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
new file mode 100644
index 000..f10cb91
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+#endif /* __FSL_LS102XA_SOC_H */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index d889ad5..be3358a 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void)
return ;
 }
 
-unsigned int get_soc_major_rev(void)
-{
-   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-   unsigned int svr, major;
-
-   svr = in_be32(>svr);
-   major = SVR_MAJ(svr);
-
-   return major;
-}
-
 int select_i2c_ch_pca9547(u8 ch)
 {
int ret;
@@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis)
 int board_early_init_f(void)
 {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-   struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-   unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
@@ -205,40 +193,7 @@ int board_early_init_f(void)
init_early_memctl_regs();
 #endif
 
-#ifdef CONFIG_FSL_QSPI
-   out_be32(>qspi_cfg, SCFG_QSPI_CLKS

[U-Boot] [PATCH v2 5/5] move erratum a008336 and a008514 to soc specific file

2015-12-04 Thread Yuan Yao 
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---
Changed in v2:
Update the patch commit message.
---

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +
 drivers/ddr/fsl/fsl_ddr_gen4.c  | 34 --
 2 files changed, 37 insertions(+), 34 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..738b113 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -14,6 +14,41 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a008336(void)
+{
+   u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
+   eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+   out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+   eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+   out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#endif
+}
+
+/*
+ * This erratum requires a register write before being Memory
+ * controller 3 being enabled.
+ */
+static void erratum_a008514(void)
+{
+   u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+   eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+   out_le32(eddrtqcr1, 0x63b20002);
+#endif
+#endif
+}
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
 
@@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void)
erratum_rcw_src();
init_early_memctl_regs();   /* tighten IFC timing */
erratum_a009203();
+   erratum_a008514();
+   erratum_a008336();
 }
 
 #elif defined(CONFIG_LS1043A)
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 1de7b72..2e5fe62 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -48,10 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-   defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-   u32 *eddrtqcr1;
-#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
u32 temp32, mr6;
 #endif
@@ -66,36 +62,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-   defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-   eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-#endif
break;
 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-   defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-   eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-#endif
break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-   defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-   eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
-#endif
break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-   defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-   eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
-#endif
break;
 #endif
default:
@@ -106,20 +86,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if (step == 2)
goto step2;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-   /* A008336 only applies to general DDR controllers */
-   if ((ctrl_num == 0) || (ctrl_num == 1))
-#endif
-   ddr_out32(eddrtqcr1, 0x63b30002);
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-   /* A008514 only applies to DP-DDR controler */
-   if (ctrl_num == 2)
-#endif
-   ddr_out32(eddrtqcr1, 0x63b20002);
-#endif
if (regs->ddr_eor)
ddr_out32(>eor, regs->ddr_eor);
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/5] arm: ls102xa: enable all the snoop signal for masters.

2015-12-04 Thread Yuan Yao 
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---

 arch/arm/cpu/armv7/ls102xa/soc.c  | 8 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++
 2 files changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 0fdd6d4..6036473 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -62,5 +62,13 @@ int arch_soc_init(void)
out_le32(>ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
}
 
+   /* Enable all the snoop signal for various masters */
+   out_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+   SCFG_SNPCNFGCR_DCU_RD_WR |
+   SCFG_SNPCNFGCR_SATA_RD_WR |
+   SCFG_SNPCNFGCR_USB3_RD_WR |
+   SCFG_SNPCNFGCR_DBG_RD_WR |
+   SCFG_SNPCNFGCR_EDMA_SNP);
+
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 1bcdf04..0527576 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -150,6 +150,12 @@ struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE1_CLK125  0x0800
 #define SCFG_PIXCLKCR_PXCKEN   0x8000
 #define SCFG_QSPI_CLKSEL   0xc010
+#define SCFG_SNPCNFGCR_SEC_RD_WR   0xc000
+#define SCFG_SNPCNFGCR_DCU_RD_WR   0x0300
+#define SCFG_SNPCNFGCR_SATA_RD_WR  0x00c0
+#define SCFG_SNPCNFGCR_USB3_RD_WR  0x0030
+#define SCFG_SNPCNFGCR_DBG_RD_WR   0x000c
+#define SCFG_SNPCNFGCR_EDMA_SNP0x0002
 #define SCFG_ENDIANCR_LE   0x8000
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.

2015-12-04 Thread Yuan Yao 
Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---

 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -40,8 +40,14 @@ int arch_soc_init(void)
 
/*
 * Enable snoop requests and DVM message requests for
-* Slave insterface S4 (A7 core cluster)
+* All the slave insterfaces.
 */
+   out_le32(>slave[0].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+   out_le32(>slave[1].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+   out_le32(>slave[2].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
out_le32(>slave[4].snoop_ctrl,
 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 0/5] arm: ls1021a: merge SoC specific code in a separate file

2015-12-04 Thread Yuan Yao 
Yuan Yao(5):
arm: ls1021a: merge SoC specific code in a separate file
arm: ls102xa: enable all the snoop signal for masters.
ls102xa: Enable snoop and DVM message requests.

armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Changed in v2:
Update the write value to 63b2_0042h;
move erratum a008336 and a008514 to soc specific file
Changed in v2:
Update the patch commit message.
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[U-Boot] [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

2015-12-04 Thread Yuan Yao 
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---
Changed in v2:
Update the write value to 63b2_0042h;
---

 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 97ba6d5..79ae883 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -76,5 +76,15 @@ int arch_soc_init(void)
SCFG_SNPCNFGCR_DBG_RD_WR |
SCFG_SNPCNFGCR_EDMA_SNP);
 
+   /*
+* Memory controller require a register write before being enabled.
+* Affects: DDR
+* Register: EDDRTQCFG
+* Description: Memory controller performance is not optimal with
+*  default internal target queue register values.
+* Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
+*/
+   out_be32(>eddrtqcfg, 0x63b20042);
+
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 0527576..c584c9f 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -228,7 +228,7 @@ struct ccsr_scfg {
u32 scfgrevcr;
u32 coresrencr;
u32 pex2pmrdsr;
-   u32 ddrc1cr;
+   u32 eddrtqcfg;
u32 ddrc2cr;
u32 ddrc3cr;
u32 ddrc4cr;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/5] arm: ls102xa: enable all the snoop signal for masters.

2015-12-04 Thread Yuan Yao 
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---

 arch/arm/cpu/armv7/ls102xa/soc.c  | 8 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++
 2 files changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 0fdd6d4..6036473 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -62,5 +62,13 @@ int arch_soc_init(void)
out_le32(>ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
}
 
+   /* Enable all the snoop signal for various masters */
+   out_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+   SCFG_SNPCNFGCR_DCU_RD_WR |
+   SCFG_SNPCNFGCR_SATA_RD_WR |
+   SCFG_SNPCNFGCR_USB3_RD_WR |
+   SCFG_SNPCNFGCR_DBG_RD_WR |
+   SCFG_SNPCNFGCR_EDMA_SNP);
+
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 1bcdf04..0527576 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -150,6 +150,12 @@ struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE1_CLK125  0x0800
 #define SCFG_PIXCLKCR_PXCKEN   0x8000
 #define SCFG_QSPI_CLKSEL   0xc010
+#define SCFG_SNPCNFGCR_SEC_RD_WR   0xc000
+#define SCFG_SNPCNFGCR_DCU_RD_WR   0x0300
+#define SCFG_SNPCNFGCR_SATA_RD_WR  0x00c0
+#define SCFG_SNPCNFGCR_USB3_RD_WR  0x0030
+#define SCFG_SNPCNFGCR_DBG_RD_WR   0x000c
+#define SCFG_SNPCNFGCR_EDMA_SNP0x0002
 #define SCFG_ENDIANCR_LE   0x8000
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v3 0/5] arm: ls1021a: merge SoC specific code in a separate file

2015-12-04 Thread Yuan Yao 
arm: ls1021a: merge SoC specific code in a separate file
arm: ls102xa: enable all the snoop signal for masters.
ls102xa: Enable snoop and DVM message requests.
armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Changed in v2:
Update the write value to 63b2_0042h;

move erratum a008336 and a008514 to soc specific file
Changed in v3:
Fix a typo issue.
In function "erratum_a008514"
"#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR" should be
"#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR"
Changed in v2:
Update the patch commit message.
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[U-Boot] [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file

2015-12-04 Thread Yuan Yao 
Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---

 arch/arm/cpu/armv7/ls102xa/Makefile |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +
 board/freescale/ls1021aqds/ls1021aqds.c | 49 +-
 board/freescale/ls1021atwr/ls1021atwr.c | 42 +---
 5 files changed, 83 insertions(+), 87 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile 
b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2311468..0228300 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -8,6 +8,7 @@ obj-y   += cpu.o
 obj-y  += clock.o
 obj-y  += timer.o
 obj-y  += fsl_epu.o
+obj-y  += soc.o
 
 obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
new file mode 100644
index 000..0fdd6d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+unsigned int get_soc_major_rev(void)
+{
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int svr, major;
+
+   svr = in_be32(>svr);
+   major = SVR_MAJ(svr);
+
+   return major;
+}
+
+int arch_soc_init(void)
+{
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+   struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+   unsigned int major;
+
+#ifdef CONFIG_FSL_QSPI
+   out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
+#ifdef CONFIG_FSL_DCU_FB
+   out_be32(>pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+   /* Configure Little endian for SAI, ASRC and SPDIF */
+   out_be32(>endiancr, SCFG_ENDIANCR_LE);
+
+   /*
+* Enable snoop requests and DVM message requests for
+* Slave insterface S4 (A7 core cluster)
+*/
+   out_le32(>slave[4].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+   major = get_soc_major_rev();
+   if (major == SOC_MAJOR_VER_1_0) {
+   /*
+* Set CCI-400 Slave interface S1, S2 Shareable Override
+* Register All transactions are treated as non-shareable
+*/
+   out_le32(>slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+   out_le32(>slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+   /* Workaround for the issue that DDR could not respond to
+* barrier transaction which is generated by executing DSB/ISB
+* instruction. Set CCI-400 control override register to
+* terminate the barrier transaction. After DDR is initialized,
+* allow barrier transaction to DDR again */
+   out_le32(>ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+   }
+
+   return 0;
+}
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h 
b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
new file mode 100644
index 000..f10cb91
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+#endif /* __FSL_LS102XA_SOC_H */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index d889ad5..be3358a 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void)
return ;
 }
 
-unsigned int get_soc_major_rev(void)
-{
-   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-   unsigned int svr, major;
-
-   svr = in_be32(>svr);
-   major = SVR_MAJ(svr);
-
-   return major;
-}
-
 int select_i2c_ch_pca9547(u8 ch)
 {
int ret;
@@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis)
 int board_early_init_f(void)
 {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-   struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-   unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
@@ -205,40 +193,7 @@ int board_early_init_f(void)
init_early_memctl_regs();
 #endif
 
-#ifdef CONFIG_FSL_QSPI
-   out_be32(>qspi_cfg, SCFG_QSPI_CLKS

[U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.

2015-12-04 Thread Yuan Yao 
Signed-off-by: Yuan Yao <yao.y...@freescale.com>
---

 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -40,8 +40,14 @@ int arch_soc_init(void)
 
/*
 * Enable snoop requests and DVM message requests for
-* Slave insterface S4 (A7 core cluster)
+* All the slave insterfaces.
 */
+   out_le32(>slave[0].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+   out_le32(>slave[1].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+   out_le32(>slave[2].snoop_ctrl,
+CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
out_le32(>slave[4].snoop_ctrl,
 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
-- 
2.1.0.27.g96db324

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