[U-Boot] [PATCH v2] armv8: fsl-lsch2: add workaround for erratum A-010635

[yuantian.tang]

From: Tang Yuantian 

Read DMA operations causes CRC error on armv8 chassis 2 platforms
due to the erratum A-010635.
In order to support sata on these platforms, ECC needs to be disabled. 

Signed-off-by: Tang Yuantian 
---
v2:
  - refine the commit message

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 9489f85..b54a937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -233,10 +233,8 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
-#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2] armv8: fsl-lsch2: add workaround for erratum A-010635

[yuantian.tang]

From: Tang Yuantian 

Read DMA operations causes CRC error on armv8 chassis 2 platforms
due to the erratum A-010635.
In order to support sata on these platforms, ECC needs to be disabled. 

Signed-off-by: Tang Yuantian 
---
v2:
  - refine the commit message

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 9489f85..b54a937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -233,10 +233,8 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
-#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: fsl-lsch2: disable ECC for sata on armv8 chassis 2 platforms

[yuantian.tang]

From: Tang Yuantian 

The Read DMA operations get early termination indication from the
controller. This issue is observed as CRC error in the status
registers. The issue is due to address collision at address 0 in
the dual port memory. The read is a dummy read to flush out the
header, but due to collision the controller logs the mbit error
reported by the ECC check logic. This results in the early termination
of the Read DMA operation by the controller. The issue happens to
all the interface speeds(GEN1/2/3) for all the products.

In order to enable SATA, ECC needs to be disabled by writing  the data
0x8000 to the address 0x20140520.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 9489f85..b54a937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -233,10 +233,8 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
-#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb nodes in dts

[yuantian.tang]

From: Tang Yuantian 

The LS1046A processor has three integrated USB 3.0 controllers
(USB1, USB2, and USB3) that allow direct connection to the USB
ports with appropriate protection circuitry and power supplies.
USB1 and USB2 ports are powered by a NX5P2190UK device, which
supplies 5v power at up to 1.2 A. The power enable and
power-fault-detect pins are connected to the LS1046A processor
via CPLD for individual port management.

Signed-off-by: Tang Yuantian 
---
 arch/arm/dts/fsl-ls1046a.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index aaf0ae9..408e81e 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -217,6 +217,27 @@
status = "disabled";
};
 
+   usb0: usb@2f0 {
+   compatible = "fsl,layerscape-dwc3";
+   reg = <0x0 0x2f0 0x0 0x1>;
+   interrupts = <0 60 4>;
+   dr_mode = "host";
+   };
+
+   usb1: usb@300 {
+   compatible = "fsl,layerscape-dwc3";
+   reg = <0x0 0x300 0x0 0x1>;
+   interrupts = <0 61 4>;
+   dr_mode = "host";
+   };
+
+   usb2: usb@310 {
+   compatible = "fsl,layerscape-dwc3";
+   reg = <0x0 0x310 0x0 0x1>;
+   interrupts = <0 63 4>;
+   dr_mode = "host";
+   };
+
pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8   /* dbi registers */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: ls1046a: enable usb in defconfig

[yuantian.tang]

From: Tang Yuantian 

Signed-off-by: Tang Yuantian 
---
 configs/ls1046aqds_defconfig | 2 ++
 configs/ls1046aqds_lpuart_defconfig  | 2 ++
 configs/ls1046aqds_nand_defconfig| 2 ++
 configs/ls1046aqds_qspi_defconfig| 2 ++
 configs/ls1046aqds_sdcard_ifc_defconfig  | 2 ++
 configs/ls1046aqds_sdcard_qspi_defconfig | 2 ++
 configs/ls1046ardb_emmc_defconfig| 2 ++
 configs/ls1046ardb_qspi_defconfig| 2 ++
 configs/ls1046ardb_sdcard_defconfig  | 2 ++
 9 files changed, 18 insertions(+)

diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 5af91b6..15c29c2 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -31,3 +31,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046aqds_lpuart_defconfig 
b/configs/ls1046aqds_lpuart_defconfig
index 83ed0e0..e9808e9 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -27,3 +27,5 @@ CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046aqds_nand_defconfig 
b/configs/ls1046aqds_nand_defconfig
index 27b733c..6b18832 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -36,3 +36,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046aqds_qspi_defconfig 
b/configs/ls1046aqds_qspi_defconfig
index 809fb3b..cdd187a 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -34,3 +34,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig 
b/configs/ls1046aqds_sdcard_ifc_defconfig
index 2f90e4f..488990a 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -36,3 +36,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig 
b/configs/ls1046aqds_sdcard_qspi_defconfig
index 175b2bf..800cb2c 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -38,3 +38,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046ardb_emmc_defconfig 
b/configs/ls1046ardb_emmc_defconfig
index 0b29796..7b50fc7 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -33,3 +33,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046ardb_qspi_defconfig 
b/configs/ls1046ardb_qspi_defconfig
index cc7dfa1..41d6984 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -31,3 +31,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/ls1046ardb_sdcard_defconfig 
b/configs/ls1046ardb_sdcard_defconfig
index d11792e..9e6d23b 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -33,3 +33,5 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2] armv8: ls1046aqds: added usb feature support

[yuantian.tang]

From: Tang Yuantian 

The LS1046AQDS processor has three integrated USB 3.0 controllers
(USB1, USB2, and USB3) that allow direct connection to the USB
ports with appropriate protection circuitry and power supplies.
USB1 and USB2 ports are powered by a NX5P2190UK device, which
supplies 5v power at up to 1.2 A. The power enable and
power-fault-detect pins are connected to the LS1046A processor
via CPLD for individual port management.

Signed-off-by: Tang Yuantian 
---
v2:
  - fix compiling warning.

 include/configs/ls1046aqds.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 3618a06..b995cd2 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -135,6 +135,18 @@ unsigned long get_board_ddr_clk(void);
 #define CFG_LPUART_EN  0x2
 #endif
 
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_HCD
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS  2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: ls1046a: enable usb in defconfig

[yuantian.tang]

From: Tang Yuantian 

Signed-off-by: Tang Yuantian 
---
 configs/ls1046aqds_defconfig | 6 ++
 configs/ls1046aqds_lpuart_defconfig  | 6 ++
 configs/ls1046aqds_nand_defconfig| 6 ++
 configs/ls1046aqds_qspi_defconfig| 6 ++
 configs/ls1046aqds_sdcard_ifc_defconfig  | 6 ++
 configs/ls1046aqds_sdcard_qspi_defconfig | 6 ++
 configs/ls1046ardb_emmc_defconfig| 6 ++
 configs/ls1046ardb_qspi_defconfig| 6 ++
 configs/ls1046ardb_sdcard_defconfig  | 6 ++
 9 files changed, 54 insertions(+)

diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 2cc1a0b..f194b65 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -20,9 +20,15 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_lpuart_defconfig 
b/configs/ls1046aqds_lpuart_defconfig
index 25bb5f9..11446ac 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -21,6 +21,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_SPI=y
@@ -28,3 +29,8 @@ CONFIG_SPI_FLASH=y
 CONFIG_FSL_DSPI=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_nand_defconfig 
b/configs/ls1046aqds_nand_defconfig
index 74fcd4a..7d86bfd 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -24,9 +24,15 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_qspi_defconfig 
b/configs/ls1046aqds_qspi_defconfig
index c8a68fa..08a9e85 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -22,6 +22,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
@@ -29,3 +30,8 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig 
b/configs/ls1046aqds_sdcard_ifc_defconfig
index fe9ad0e..69280bd 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -24,9 +24,15 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig 
b/configs/ls1046aqds_sdcard_qspi_defconfig
index 1700082..c7295aa 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -25,6 +25,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
@@ -32,3 +33,8 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_emmc_defconfig 
b/configs/ls1046ardb_emmc_defconfig
index fd21959..e3c21e3 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -21,9 +21,15 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_qspi_defconfig 
b/configs/ls1046ardb_qspi_defconfig
index fa17373..1081853 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -18,6 +18,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
@@ -25,3 +26,8 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_sdcard_defconfig 

[U-Boot] [PATCH] armv8: ls1046aqds: added usb feature support

[yuantian.tang]

From: Tang Yuantian 

The LS1046AQDS processor has three integrated USB 3.0 controllers
(USB1, USB2, and USB3) that allow direct connection to the USB
ports with appropriate protection circuitry and power supplies.
USB1 and USB2 ports are powered by a NX5P2190UK device, which
supplies 5v power at up to 1.2 A. The power enable and
power-fault-detect pins are connected to the LS1046A processor
via CPLD for individual port management.

Signed-off-by: Tang Yuantian 
---
 include/configs/ls1046aqds.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 29e0aa5..53a1ffb 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -135,6 +135,14 @@ unsigned long get_board_ddr_clk(void);
 #define CFG_LPUART_EN  0x2
 #endif
 
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: ls1012: Enable CONFIG_DM_USB in defconfigs

[yuantian.tang]

From: Tang Yuantian 

Enables driver model flag CONFIG_DM_USB for LS1012A platform
in defconfigs.

Signed-off-by: Tang Yuantian 
---
 configs/ls1012afrdm_qspi_defconfig | 1 +
 configs/ls1012aqds_qspi_defconfig  | 1 +
 configs/ls1012ardb_qspi_defconfig  | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/ls1012afrdm_qspi_defconfig 
b/configs/ls1012afrdm_qspi_defconfig
index c83b2eb..9276abc 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -31,6 +31,7 @@ CONFIG_NETDEVICES=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012aqds_qspi_defconfig 
b/configs/ls1012aqds_qspi_defconfig
index 27bccd1..0393450 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -35,6 +35,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/ls1012ardb_qspi_defconfig 
b/configs/ls1012ardb_qspi_defconfig
index 459682d..333cc30 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -35,6 +35,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] armv8: ls1012: added usb nodes in dts

[yuantian.tang]

From: Tang Yuantian 

The LS1012A processor has two integrated USB controllers.
One is USB2.0 controller, the other is USB3.0 controller that
allow direct connection to the USB ports with appropriate
protection circuitry and power supplies.

Signed-off-by: Tang Yuantian 
---
 arch/arm/dts/fsl-ls1012a.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 024527e..c3bba12 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -103,5 +103,19 @@
status = "disabled";
};
 
+   usb0: usb2@860 {
+   compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+   reg = <0x0 0x860 0x0 0x1000>;
+   interrupts = <0 139 0x4>;
+   dr_mode = "host";
+   fsl,usb-erratum-a005697;
+   };
+
+   usb1: usb3@2f0 {
+   compatible = "fsl,layerscape-dwc3";
+   reg = <0x0 0x2f0 0x0 0x1>;
+   interrupts = <0 61 0x4>;
+   dr_mode = "host";
+   };
};
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb feature support

[yuantian.tang]

From: Tang Yuantian 

The LS1046A processor has three integrated USB 3.0 controllers
(USB1, USB2, and USB3) that allow direct connection to the USB
ports with appropriate protection circuitry and power supplies.
USB1 and USB2 ports are powered by a NX5P2190UK device, which
supplies 5v power at up to 1.2 A. The power enable and
power-fault-detect pins are connected to the LS1046A processor
via CPLD for individual port management.

Signed-off-by: Tang Yuantian 
---
 arch/arm/dts/fsl-ls1046a.dtsi | 22 ++
 include/configs/ls1046ardb.h  |  8 
 include/linux/usb/xhci-fsl.h  |  2 +-
 3 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 359a9d1..ee3180e 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -216,5 +216,27 @@
big-endian;
status = "disabled";
};
+
+   usb0: usb@2f0 {
+   compatible = "fsl,layerscape-dwc3";
+   reg = <0x0 0x2f0 0x0 0x1>;
+   interrupts = <0 60 4>;
+   dr_mode = "host";
+   };
+
+   usb1: usb@300 {
+   compatible = "fsl,layerscape-dwc3";
+   reg = <0x0 0x300 0x0 0x1>;
+   interrupts = <0 61 4>;
+   dr_mode = "host";
+   };
+
+   usb2: usb@310 {
+   compatible = "fsl,layerscape-dwc3";
+   reg = <0x0 0x310 0x0 0x1>;
+   interrupts = <0 63 4>;
+   dr_mode = "host";
+   };
+
};
 };
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 2fe8fc1..d363d1f 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -211,6 +211,14 @@
 #define CONFIG_SPI_FLASH_BAR
 #endif
 
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 15cac40..1fa3161 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -62,7 +62,7 @@ struct fsl_xhci {
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write

[yuantian.tang]

From: Tang Yuantian 

By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions.  This patch enable it in the
sata axicc register.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c42387..80fdca5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -213,10 +213,12 @@ int sata_init(void)
ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+   out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+   out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(0);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] sata: fix sata command can not being executed bug

[yuantian.tang]

From: Tang Yuantian 

Commit d97dc8a0 separated the non-command code into its own file
which caused variable sata_curr_device can not be set to a correct
value.

Before commit d97dc8a0, variable sata_curr_device can be set
correctly in sata_initialize().
After commit d97dc8a0, sata_initialize() is moved out to its own file.
Accordingly, variable sata_curr_device is removed from sata_initialize()
too. This caused sata_curr_device never gets a chance to be set properly
which prevent other commands from being executed.

This patch sets variable sata_curr_device properly.

Fixes: d97dc8a0 (dm: sata: Separate the non-command code into its
 own file)

Signed-off-by: Tang Yuantian 
---
v3:
  - refine the commit message
v2:
  - refined this patch and updated the commit title and message

 cmd/sata.c| 9 ++---
 common/sata.c | 8 +---
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/cmd/sata.c b/cmd/sata.c
index d18b523..f56622a 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -32,9 +32,12 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
}
 
/* If the user has not yet run `sata init`, do it now */
-   if (sata_curr_device == -1)
-   if (sata_initialize())
-   return 1;
+   if (sata_curr_device == -1) {
+   rc = sata_initialize();
+   if (rc == -1)
+   return rc;
+   sata_curr_device = rc;
+   }
 
switch (argc) {
case 0:
diff --git a/common/sata.c b/common/sata.c
index 88f08c9..42ff5c7 100644
--- a/common/sata.c
+++ b/common/sata.c
@@ -51,7 +51,7 @@ static unsigned long sata_bwrite(struct blk_desc *block_dev, 
lbaint_t start,
 
 int __sata_initialize(void)
 {
-   int rc;
+   int rc, ret = -1;
int i;
 
for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
@@ -71,12 +71,14 @@ int __sata_initialize(void)
if (!rc) {
rc = scan_sata(i);
if (!rc && sata_dev_desc[i].lba > 0 &&
-   sata_dev_desc[i].blksz > 0)
+   sata_dev_desc[i].blksz > 0) {
part_init(_dev_desc[i]);
+   ret = i;
+   }
}
}
 
-   return rc;
+   return ret;
 }
 int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2] sata: Fixes:d97dc8a0(Separate the non-command code into its own file)

[yuantian.tang]

From: Tang Yuantian 

Commit d97dc8a0 separated the non-command code into its own file
which caused variable sata_curr_device can not be set to a correct
value.

Before commit d97dc8a0, variable sata_curr_device can be set
correctly in sata_initialize().
After commit d97dc8a0, sata_initialize() is moved out to its own file.
Accordingly, sata_curr_device is removed from sata_initialize() too.
This caused sata_curr_device never gets a chance to be set properly
which prevent other command from being executed.

This patch sets variable sata_curr_device properly.

Signed-off-by: Tang Yuantian 
---
v2:
  - refined this patch and updated the commit title and message

 cmd/sata.c| 9 ++---
 common/sata.c | 8 +---
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/cmd/sata.c b/cmd/sata.c
index d18b523..f56622a 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -32,9 +32,12 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
}
 
/* If the user has not yet run `sata init`, do it now */
-   if (sata_curr_device == -1)
-   if (sata_initialize())
-   return 1;
+   if (sata_curr_device == -1) {
+   rc = sata_initialize();
+   if (rc == -1)
+   return rc;
+   sata_curr_device = rc;
+   }
 
switch (argc) {
case 0:
diff --git a/common/sata.c b/common/sata.c
index 88f08c9..42ff5c7 100644
--- a/common/sata.c
+++ b/common/sata.c
@@ -51,7 +51,7 @@ static unsigned long sata_bwrite(struct blk_desc *block_dev, 
lbaint_t start,
 
 int __sata_initialize(void)
 {
-   int rc;
+   int rc, ret = -1;
int i;
 
for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
@@ -71,12 +71,14 @@ int __sata_initialize(void)
if (!rc) {
rc = scan_sata(i);
if (!rc && sata_dev_desc[i].lba > 0 &&
-   sata_dev_desc[i].blksz > 0)
+   sata_dev_desc[i].blksz > 0) {
part_init(_dev_desc[i]);
+   ret = i;
+   }
}
}
 
-   return rc;
+   return ret;
 }
 int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] sata: fix sata command not being executed bug

[yuantian.tang]

From: Tang Yuantian 

Variable sata_curr_device is used to indicate if
there is a available sata disk on board.

Previously, sata_curr_device is set in sata_initialize().
Now, sata_initialize() is separated from other sata commands.
Accordingly, sata_curr_device is removed from sata_initialize() too.
This caused sata_curr_device never gets a chance to be set.
If it can't be set a proper value, other sata command will never get
a change to execute.

This patch sets variable sata_curr_device properly.

Signed-off-by: Tang Yuantian 
---
 cmd/sata.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/cmd/sata.c b/cmd/sata.c
index d18b523..71c785f 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -20,6 +20,7 @@ static int sata_curr_device = -1;
 static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
int rc = 0;
+   int i;
 
if (argc == 2 && strcmp(argv[1], "stop") == 0)
return sata_stop();
@@ -32,9 +33,15 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
}
 
/* If the user has not yet run `sata init`, do it now */
-   if (sata_curr_device == -1)
-   if (sata_initialize())
-   return 1;
+   if (sata_curr_device == -1) {
+   rc = sata_initialize();
+   for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
+   if (sata_dev_desc[i].lba > 0)
+   sata_curr_device = i;
+   }
+   if (sata_curr_device == -1)
+   return -1;
+   }
 
switch (argc) {
case 0:
-- 
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[U-Boot] [PATCH 1/2] armv8: fsl-lsch2: adjust sata parameter

[yuantian.tang]

From: Tang Yuantian 

The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 2 --
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..6333122 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -223,8 +223,6 @@ int sata_init(void)
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-   out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
-   out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
 
ahci_init((void __iomem *)CONFIG_SYS_SATA);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 8d4a7ad..d5fe0ce 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -60,8 +60,6 @@ struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
-#define AHCI_PORT_PHY_2_CFG0x28184d1f
-#define AHCI_PORT_PHY_3_CFG0x0e081509
 #define AHCI_PORT_TRANS_CFG0x0829
 
 /* AHCI (sata) register map */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: fsl-lsch2: enable snoopable sata read and write

[yuantian.tang]

From: Tang Yuantian 

By default the SATA IP on the ls1043a/ls1046a SoCs does not generating
coherent/snoopable transactions.  This patch enable it in the SCFG_SNPCNFGCR
register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA controller
nodes.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 5 -
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6333122..fe13782 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -224,6 +224,7 @@ int sata_init(void)
 
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+   out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(0);
@@ -310,7 +311,9 @@ void fsl_lsch2_early_init_f(void)
 #endif
/* Make SEC reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-SCFG_SNPCNFGCR_SECWRSNP);
+SCFG_SNPCNFGCR_SECWRSNP |
+SCFG_SNPCNFGCR_SATARDSNP |
+SCFG_SNPCNFGCR_SATAWRSNP);
 
/*
 * Enable snoop requests and DVM message requests for
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 95a4293..2d307cc 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -335,6 +335,8 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
+#define SCFG_SNPCNFGCR_SATARDSNP   0x0080
+#define SCFG_SNPCNFGCR_SATAWRSNP   0x0040
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index d5fe0ce..f29fd9f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -61,6 +61,7 @@ struct cpu_type {
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
 #define AHCI_PORT_TRANS_CFG0x0829
+#define AHCI_PORT_AXICC_CFG0x3fff
 
 /* AHCI (sata) register map */
 struct ccsr_ahci {
-- 
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[U-Boot] [PATCH] ahci: flush dcache before issuing command

[yuantian.tang]

From: Tang Yuantian 

Ensure data the following sata command used is flushed out of dcache
and written to physical memory or timeout error may happen.

Signed-off-by: Tang Yuantian 
---
 drivers/block/ahci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index d29642b..e3e783a 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -1061,6 +1061,7 @@ static int ata_io_flush(u8 port)
 
memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
ahci_fill_cmd_slot(pp, cmd_fis_len);
+   ahci_dcache_flush_sata_cmd(pp);
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
 
if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
-- 
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[U-Boot] [PATCH] arm: ls1021a: Adjust sata register default values

[Yuantian.Tang]

From: Tang Yuantian 

Updated the default sata register values to enhance the
performance and stability.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c 
b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
index deeb674..144f2c3 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -11,11 +11,11 @@
 
 /* port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
-#define AHCI_PORT_PHY_2_CFG0x28183411
-#define AHCI_PORT_PHY_3_CFG0x0e081004
-#define AHCI_PORT_PHY_4_CFG0x00480811
-#define AHCI_PORT_PHY_5_CFG0x192c96a4
-#define AHCI_PORT_TRANS_CFG0x0825
+#define AHCI_PORT_PHY_2_CFG0x28183414
+#define AHCI_PORT_PHY_3_CFG0x0e080e06
+#define AHCI_PORT_PHY_4_CFG0x064a080b
+#define AHCI_PORT_PHY_5_CFG0x2aa86470
+#define AHCI_PORT_TRANS_CFG0x0829
 
 #define SATA_ECC_REG_ADDR  0x20220520
 #define SATA_ECC_DISABLE   0x0002
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6] arm: Add sata support on Layerscape ARMv8 board

[Yuantian.Tang]

From: Tang Yuantian 

Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian 
---
v6:
- update rx watermark from 0x25 to 0x29 to improve
compatibility
v5:
- re-organize the code
v4:
- rebase to lastest git tree
- add another ARMv8 platform which is ls1043aqds
v3:
- rename ls2085a to ls2080a
- rebase to the latest git tree
- replace the magic number with micro variable
v2:
- rebase to the latest git tree

 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  4 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 
 include/configs/ls1043aqds.h   | 17 +
 include/configs/ls2080aqds.h   | 18 +
 include/configs/ls2080ardb.h   | 18 +
 6 files changed, 131 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..574ffc4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,6 +6,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
 }
 
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci;
+
+   ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 #elif defined(CONFIG_LS1043A)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ahci_init((void __iomem *)CONFIG_SYS_SATA);
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+#ifdef CONFIG_SCSI_AHCI_PLAT
+   sata_init();
+#endif
+
return 0;
 }
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index cd96604..91f3ce8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -69,6 +69,10 @@
 #define TZASC_REGION_ATTRIBUTES_0(x)   ((TZASC1_BASE + (x * 0x1)) + 0x110)
 #define TZASC_REGION_ID_ACCESS_0(x)((TZASC1_BASE + (x * 0x1)) + 0x114)
 
+/* SATA */
+#define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR + 
0x0220)
+#define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR + 
0x0221)
+
 /* PCIe */
 #define CONFIG_SYS_PCIE1_ADDR  (CONFIG_SYS_IMMR + 0x240)
 #define CONFIG_SYS_PCIE2_ADDR  (CONFIG_SYS_IMMR + 0x250)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 504c1f9..1565592 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -51,6 +51,37 @@ struct cpu_type {
 #define SVR_SOC_VER(svr)   (((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1))
 
+/* ahci port register default value */
+#define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY_2_CFG0x28184d1f
+#define AHCI_PORT_PHY_3_CFG0x0e081509
+#define AHCI_PORT_TRANS_CFG0x0829
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 axicc;  /* AXI cache control */
+   u32 paxic;  /* port AXI config */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status */
+   u32 plc;/* port link config */
+   

[U-Boot] [PATCH v5] arm: Add sata support on Layerscape ARMv8 board

[Yuantian.Tang]

From: Tang Yuantian 

Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian 
---
v5:
- re-organize the code
v4:
- rebase to lastest git tree
- add another ARMv8 platform which is ls1043aqds
v3:
- rename ls2085a to ls2080a
- rebase to the latest git tree
- replace the magic number with micro variable
v2:
- rebase to the latest git tree

 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  4 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 
 include/configs/ls1043aqds.h   | 17 +
 include/configs/ls2080aqds.h   | 18 +
 include/configs/ls2080ardb.h   | 18 +
 6 files changed, 131 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..574ffc4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,6 +6,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
 }
 
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci;
+
+   ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 #elif defined(CONFIG_LS1043A)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ahci_init((void __iomem *)CONFIG_SYS_SATA);
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+#ifdef CONFIG_SCSI_AHCI_PLAT
+   sata_init();
+#endif
+
return 0;
 }
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index cd96604..91f3ce8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -69,6 +69,10 @@
 #define TZASC_REGION_ATTRIBUTES_0(x)   ((TZASC1_BASE + (x * 0x1)) + 0x110)
 #define TZASC_REGION_ID_ACCESS_0(x)((TZASC1_BASE + (x * 0x1)) + 0x114)
 
+/* SATA */
+#define AHCI_BASE_ADDR1(CONFIG_SYS_IMMR + 
0x0220)
+#define AHCI_BASE_ADDR2(CONFIG_SYS_IMMR + 
0x0221)
+
 /* PCIe */
 #define CONFIG_SYS_PCIE1_ADDR  (CONFIG_SYS_IMMR + 0x240)
 #define CONFIG_SYS_PCIE2_ADDR  (CONFIG_SYS_IMMR + 0x250)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 504c1f9..83186d6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -51,6 +51,37 @@ struct cpu_type {
 #define SVR_SOC_VER(svr)   (((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1))
 
+/* ahci port register default value */
+#define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY_2_CFG0x28184d1f
+#define AHCI_PORT_PHY_3_CFG0x0e081509
+#define AHCI_PORT_TRANS_CFG0x0825
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 axicc;  /* AXI cache control */
+   u32 paxic;  /* port AXI config */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status */
+   u32 plc;/* port link config */
+   u32 plc1;   /* port link config1 */
+   u32 plc2;   /* port link config2 */

[U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board

[Yuantian.Tang]

From: Tang Yuantian 

Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian 
---
v4:
- rebase to lastest git tree
- add another ARMv8 platform which is ls1043aqds
v3:
- rename ls2085a to ls2080a
- rebase to the latest git tree
- replace the magic number with micro variable
v2:
- rebase to the latest git tree

 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 43 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31 
 include/configs/ls1043aqds.h  | 17 +
 4 files changed, 109 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..574ffc4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,6 +6,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
 }
 
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci;
+
+   ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 #elif defined(CONFIG_LS1043A)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ahci_init((void __iomem *)CONFIG_SYS_SATA);
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+#ifdef CONFIG_SCSI_AHCI_PLAT
+   sata_init();
+#endif
+
return 0;
 }
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b5a2d28..be3acc3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -54,6 +54,24 @@
 
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA1   (CONFIG_SYS_IMMR + 0x0220)
+#define CONFIG_SYS_SATA2   (CONFIG_SYS_IMMR + 0x0221)
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+   CONFIG_SYS_SCSI_MAX_LUN)
+
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE  0x0600
 #define GICR_BASE  0x0610
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 504c1f9..83186d6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -51,6 +51,37 @@ struct cpu_type {
 #define SVR_SOC_VER(svr)   (((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)(!((svr >> 8) & 0x1))
 
+/* ahci port register default value */
+#define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY_2_CFG0x28184d1f
+#define AHCI_PORT_PHY_3_CFG0x0e081509
+#define AHCI_PORT_TRANS_CFG0x0825
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 axicc;  /* AXI cache control */
+   u32 paxic;  /* port AXI config */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status 

[U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- rebase to latest git tree
- use micro SATA_ECC_REG_ADDR instead of hard coding 

 arch/arm/include/asm/arch-ls102xa/config.h| 15 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +
 board/freescale/ls1021aqds/ls1021aqds.c   | 61 +++
 board/freescale/ls1021atwr/ls1021atwr.c   | 61 +++
 4 files changed, 161 insertions(+)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index c55cdef..a4a5d84 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,6 +79,21 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
 CONFIG_SYS_PCIE2_VIRT_ADDR)
 
+/* SATA */
+#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220)
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+   CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_ERRATUM_A008407
+
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index d34044a..211fe1d 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -397,4 +397,28 @@ struct ccsr_cci400 {
u8 res_e004[0x1 - 0xe004];
 };
 
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 paxic;  /* port AXI config */
+   u32 axicc;  /* AXI cache control */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status */
+   u32 plc;/* port link config */
+   u32 plc1;   /* port link config1 */
+   u32 plc2;   /* port link config2 */
+   u32 pls;/* port link status */
+   u32 pls1;   /* port link status1 */
+   u32 pcmdc;  /* port CMD config */
+   u32 ppcs;   /* port phy control status */
+   u32 pberr;  /* port 0/1 BIST error */
+   u32 cmds;   /* port 0/1 CMD status error */
+};
 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index d6ef6ba..1b26ed3 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -18,6 +18,8 @@
 #include fsl_ifc.h
 #include fsl_sec.h
 #include spl.h
+#include ahci.h
+#include scsi.h
 
 #include ../common/sleep.h
 #include ../common/qixis.h
@@ -54,6 +56,52 @@ enum {
GE1_CLK125,
 };
 
+static void ls1021a_sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+#define SATA_ECC_REG_ADDR  0x20220520
+   unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
+#endif
+
+   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
+   out_le32(ccsr_ahci-pp2c, 0x28183411);
+   out_le32(ccsr_ahci-pp3c, 0x0e081004);
+   out_le32(ccsr_ahci-pp4c, 0x00480811);
+   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
+   out_le32(ccsr_ahci-ptc, 0x0825);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+   out_le32(ecc_reg, 0x0002);
+#endif
+}
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+static int ls1021a_sata_start(void)
+{
+   struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+   u32 cfg;
+   int rc = -1;
+
+   cfg = in_be32(gur-rcwsr[4])  RCWSR4_SRDS1_PRTCL_MASK;
+   cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
+
+   if (cfg != 0x30  cfg != 0x70) {
+   printf(SATA disabled: serdes protocol doesn't support\n);
+   return rc;
+   }
+
+   rc = ahci_init((void __iomem *)AHCI_BASE_ADDR);
+   if (rc)
+   return rc;
+
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_LS102XA_NS_ACCESS
 static struct 

[U-Boot] [PATCH v2] arm/ls2085a: Add sata support on qds and rdb board

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Freescale ARM-based Layerscape LS2085A contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2085aqds and ls2085ardb boards.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- rebase to the latest git tree

 arch/arm/cpu/armv8/fsl-lsch3/soc.c| 41 +++
 arch/arm/include/asm/arch-fsl-lsch3/config.h  | 20 +++
 arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 25 ++
 arch/arm/include/asm/arch-fsl-lsch3/soc.h |  2 +-
 board/freescale/ls2085aqds/ls2085aqds.c   | 11 ++
 board/freescale/ls2085ardb/ls2085ardb.c   | 11 ++
 6 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c 
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 2538001..0e6f07b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -11,6 +11,9 @@
 #include asm/arch-fsl-lsch3/soc.h
 #include asm/io.h
 #include asm/global_data.h
+#include asm/arch-fsl-lsch3/immap_lsch3.h
+#include ahci.h
+#include scsi.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,12 +73,50 @@ static void erratum_a009203(void)
 #endif
 }
 
+void ls2085a_sata_init(void)
+{
+   struct ccsr_ahci __iomem *ahci_base;
+
+   ahci_base = (void __iomem *)CONFIG_SYS_SATA2;
+   out_le32(ahci_base-ppcfg, 0xa003fffe);
+
+   ahci_base = (void __iomem *)CONFIG_SYS_SATA1;
+   out_le32(ahci_base-ppcfg, 0xa003fffe);
+}
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int ls2085a_sata_start(void)
+{
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 cfg;
+   int rc = -1;
+
+   cfg = in_le32(gur-rcwsr[28])  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+   cfg = FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+   if ((cfg != 0x41)  (cfg != 0x42)  (cfg != 0x43) 
+   (cfg != 0x44)  (cfg != 0x49)  (cfg != 0x4A)) {
+   printf(SATA disabled: serdes protocol doesn't support\n);
+   return rc;
+   }
+
+   rc = ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+   if (rc)
+   return rc;
+
+   scsi_scan(0);
+
+   return 0;
+}
+#endif
+
 void fsl_lsch3_early_init_f(void)
 {
erratum_a008751();
erratum_rcw_src();
init_early_memctl_regs();   /* tighten IFC timing */
erratum_a009203();
+   ls2085a_sata_init();
 }
 
 #ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h 
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index a4576dd..ba983f5 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -64,6 +64,26 @@
 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x0102)
 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x0103)
 
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1   (CONFIG_SYS_IMMR + 0x0220)
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2   (CONFIG_SYS_IMMR + 0x0221)
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+   CONFIG_SYS_SCSI_MAX_LUN)
+
 #define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR  (CONFIG_SYS_IMMR + 0x0210)
 #define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR  (CONFIG_SYS_IMMR + 0x0211)
 
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index d6bee60..a9a0447 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -180,4 +180,29 @@ struct ccsr_reset {
u32 ip_rev1;/* 0xbf8 */
u32 ip_rev2;/* 0xbfc */
 };
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 paxic;  /* port AXI config */
+   u32 axicc;  /* AXI cache control */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status */
+   u32 plc;/* port link config */
+   u32 plc1;   /* port link config1 */
+   u32 plc2;   /* port link config2 */
+   u32 pls;/* 

[U-Boot] [PATCH] layerscape: sata: Add layerscape sata support

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Freescale ARM-based Layerscape SoCs contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds some basic SATA APIs which would be called by
specific board.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/common/Makefile  |  6 +
 board/freescale/common/ls_sata.c | 52 
 board/freescale/common/ls_sata.h | 39 ++
 3 files changed, 97 insertions(+)
 create mode 100644 board/freescale/common/ls_sata.c
 create mode 100644 board/freescale/common/ls_sata.h

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 87d0578..8508005 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -43,6 +43,12 @@ else
 obj-$(CONFIG_DEEP_SLEEP)   += mpc85xx_sleep.o
 endif
 
+ifdef CONFIG_ARM
+ifdef CONFIG_SATA1
+obj-y += ls_sata.o
+endif
+endif
+
 obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
 
 obj-$(CONFIG_MPC8541CDS)   += cds_pci_ft.o
diff --git a/board/freescale/common/ls_sata.c b/board/freescale/common/ls_sata.c
new file mode 100644
index 000..2aab939
--- /dev/null
+++ b/board/freescale/common/ls_sata.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include ahci.h
+#include scsi.h
+
+#include ls_sata.h
+
+void ls_sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+   unsigned int __iomem *dcfg_ecc = (void *)0x20220520;
+   out_le32(dcfg_ecc, 0x0002);
+#endif
+
+#ifdef CONFIG_SATA2
+   ccsr_ahci = (void __iomem *)CONFIG_SYS_SATA2;
+   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
+#endif
+
+#ifdef CONFIG_SATA1
+   ccsr_ahci = (void __iomem *)CONFIG_SYS_SATA1;
+   out_le32(ccsr_ahci-ppcfg, 0xa003fffe);
+#ifdef CONFIG_LS102XA
+   out_le32(ccsr_ahci-pp2c, 0x28183411);
+   out_le32(ccsr_ahci-pp3c, 0x0e081004);
+   out_le32(ccsr_ahci-pp4c, 0x00480811);
+   out_le32(ccsr_ahci-pp5c, 0x192c96a4);
+   out_le32(ccsr_ahci-ptc, 0x0825);
+#endif
+#endif
+}
+
+int ls_sata_start(void)
+{
+   int rc;
+
+   rc = ahci_init((void *)CONFIG_SYS_SATA1);
+   if (rc)
+   return rc;
+
+   scsi_scan(0);
+
+   return 0;
+}
diff --git a/board/freescale/common/ls_sata.h b/board/freescale/common/ls_sata.h
new file mode 100644
index 000..a69854c
--- /dev/null
+++ b/board/freescale/common/ls_sata.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS_SATA_H
+#define __LS_SATA_H
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 paxic;  /* port AXI config */
+   u32 axicc;  /* AXI cache control */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status */
+   u32 plc;/* port link config */
+   u32 plc1;   /* port link config1 */
+   u32 plc2;   /* port link config2 */
+   u32 pls;/* port link status */
+   u32 pls1;   /* port link status1 */
+   u32 pcmdc;  /* port CMD config */
+   u32 ppcs;   /* port phy control status */
+   u32 pberr;  /* port 0/1 BIST error */
+   u32 cmds;   /* port 0/1 CMD status error */
+};
+
+void ls_sata_init(void);
+
+int ls_sata_start(void);
+
+#endif
-- 
2.1.0.27.g96db324

___
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[U-Boot] [PATCH v3] ahci: Fix compiling warnings under 64bit platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

When compling under 64bit platforms, there are lots of warnings,
like:

drivers/block/ahci.c:114:18: warning: cast to pointer from integer
 of different size [-Wint-to-pointer-cast]
  u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
  ^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
 of different size [-Wpointer-to-int-cast]
   probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);

..

Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v3:
- fix warnings this patch caused on drivers/block/dwc_ahsata.c
- take case of tbl_addr_hi when work under 64bit mode
v2:
- refined some type casts

 drivers/block/ahci.c   | 64 +-
 drivers/block/dwc_ahsata.c | 13 ++
 include/ahci.h |  8 +++---
 3 files changed, 47 insertions(+), 38 deletions(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 4fb846a..a57f674 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -43,13 +43,13 @@ u16 *ataid[AHCI_MAX_PORTS];
 #define WAIT_MS_FLUSH  5000
 #define WAIT_MS_LINKUP 200
 
-static inline u32 ahci_port_base(u32 base, u32 port)
+static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
 {
return base + 0x100 + (port * 0x80);
 }
 
 
-static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
+static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
unsigned int port_idx)
 {
base = ahci_port_base(base, port_idx);
@@ -61,7 +61,7 @@ static void ahci_setup_port(struct ahci_ioports *port, 
unsigned long base,
 
 #define msleep(a) udelay(a * 1000)
 
-static void ahci_dcache_flush_range(unsigned begin, unsigned len)
+static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
 {
const unsigned long start = begin;
const unsigned long end = start + len;
@@ -75,7 +75,7 @@ static void ahci_dcache_flush_range(unsigned begin, unsigned 
len)
  * controller is invalidated from dcache; next access comes from
  * physical RAM.
  */
-static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
+static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long 
len)
 {
const unsigned long start = begin;
const unsigned long end = start + len;
@@ -94,7 +94,7 @@ static void ahci_dcache_flush_sata_cmd(struct ahci_ioports 
*pp)
AHCI_PORT_PRIV_DMA_SZ);
 }
 
-static int waiting_for_cmd_completed(volatile u8 *offset,
+static int waiting_for_cmd_completed(void __iomem *offset,
 int timeout_msec,
 u32 sign)
 {
@@ -111,7 +111,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, 
u8 port)
 {
u32 tmp;
int j = 0;
-   u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
+   void __iomem *port_mmio = probe_ent-port[port].port_mmio;
 
/*
 * Bring up SATA link.
@@ -131,7 +131,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, 
u8 port)
 
 #ifdef CONFIG_SUNXI_AHCI
 /* The sunxi AHCI controller requires this undocumented setup */
-static void sunxi_dma_init(volatile u8 *port_mmio)
+static void sunxi_dma_init(void __iomem *port_mmio)
 {
clrsetbits_le32(port_mmio + PORT_P0DMACR, 0xff00, 0x4400);
 }
@@ -171,10 +171,10 @@ static int ahci_host_init(struct ahci_probe_ent 
*probe_ent)
u16 tmp16;
unsigned short vendor;
 #endif
-   volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
+   void __iomem *mmio = probe_ent-mmio_base;
u32 tmp, cap_save, cmd;
int i, j, ret;
-   volatile u8 *port_mmio;
+   void __iomem *port_mmio;
u32 port_map;
 
debug(ahci_host_init: start\n);
@@ -215,9 +215,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
for (i = 0; i  probe_ent-n_ports; i++) {
if (!(port_map  (1  i)))
continue;
-   probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);
+   probe_ent-port[i].port_mmio = ahci_port_base(mmio, i);
port_mmio = (u8 *) probe_ent-port[i].port_mmio;
-   ahci_setup_port(probe_ent-port[i], (unsigned long)mmio, i);
+   ahci_setup_port(probe_ent-port[i], mmio, i);
 
/* make sure port is not active */
tmp = readl(port_mmio + PORT_CMD);
@@ -329,7 +329,7 @@ static void ahci_print_info(struct ahci_probe_ent 
*probe_ent)
pci_dev_t pdev = probe_ent-dev;
u16 cc;
 #endif
-   volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
+   void __iomem *mmio = probe_ent-mmio_base;
u32 vers, cap, cap2, impl, speed;
const char *speed_s;
const char 

[U-Boot] [PATCH v2] ahci: Fix compiling warnings under 64bit platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

When compling under 64bit platforms, there are lots of warnings,
like:

drivers/block/ahci.c:114:18: warning: cast to pointer from integer
 of different size [-Wint-to-pointer-cast]
  u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
  ^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
 of different size [-Wpointer-to-int-cast]
   probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);

..

Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- refined some type casts

 drivers/block/ahci.c | 57 +++-
 include/ahci.h   |  8 
 2 files changed, 34 insertions(+), 31 deletions(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 4fb846a..2f76af5 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -43,13 +43,13 @@ u16 *ataid[AHCI_MAX_PORTS];
 #define WAIT_MS_FLUSH  5000
 #define WAIT_MS_LINKUP 200
 
-static inline u32 ahci_port_base(u32 base, u32 port)
+static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
 {
return base + 0x100 + (port * 0x80);
 }
 
 
-static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
+static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
unsigned int port_idx)
 {
base = ahci_port_base(base, port_idx);
@@ -61,7 +61,7 @@ static void ahci_setup_port(struct ahci_ioports *port, 
unsigned long base,
 
 #define msleep(a) udelay(a * 1000)
 
-static void ahci_dcache_flush_range(unsigned begin, unsigned len)
+static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
 {
const unsigned long start = begin;
const unsigned long end = start + len;
@@ -75,7 +75,7 @@ static void ahci_dcache_flush_range(unsigned begin, unsigned 
len)
  * controller is invalidated from dcache; next access comes from
  * physical RAM.
  */
-static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
+static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long 
len)
 {
const unsigned long start = begin;
const unsigned long end = start + len;
@@ -94,7 +94,7 @@ static void ahci_dcache_flush_sata_cmd(struct ahci_ioports 
*pp)
AHCI_PORT_PRIV_DMA_SZ);
 }
 
-static int waiting_for_cmd_completed(volatile u8 *offset,
+static int waiting_for_cmd_completed(void __iomem *offset,
 int timeout_msec,
 u32 sign)
 {
@@ -111,7 +111,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, 
u8 port)
 {
u32 tmp;
int j = 0;
-   u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
+   void __iomem *port_mmio = probe_ent-port[port].port_mmio;
 
/*
 * Bring up SATA link.
@@ -131,7 +131,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, 
u8 port)
 
 #ifdef CONFIG_SUNXI_AHCI
 /* The sunxi AHCI controller requires this undocumented setup */
-static void sunxi_dma_init(volatile u8 *port_mmio)
+static void sunxi_dma_init(void __iomem *port_mmio)
 {
clrsetbits_le32(port_mmio + PORT_P0DMACR, 0xff00, 0x4400);
 }
@@ -171,10 +171,10 @@ static int ahci_host_init(struct ahci_probe_ent 
*probe_ent)
u16 tmp16;
unsigned short vendor;
 #endif
-   volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
+   void __iomem *mmio = probe_ent-mmio_base;
u32 tmp, cap_save, cmd;
int i, j, ret;
-   volatile u8 *port_mmio;
+   void __iomem *port_mmio;
u32 port_map;
 
debug(ahci_host_init: start\n);
@@ -215,9 +215,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
for (i = 0; i  probe_ent-n_ports; i++) {
if (!(port_map  (1  i)))
continue;
-   probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);
+   probe_ent-port[i].port_mmio = ahci_port_base(mmio, i);
port_mmio = (u8 *) probe_ent-port[i].port_mmio;
-   ahci_setup_port(probe_ent-port[i], (unsigned long)mmio, i);
+   ahci_setup_port(probe_ent-port[i], mmio, i);
 
/* make sure port is not active */
tmp = readl(port_mmio + PORT_CMD);
@@ -329,7 +329,7 @@ static void ahci_print_info(struct ahci_probe_ent 
*probe_ent)
pci_dev_t pdev = probe_ent-dev;
u16 cc;
 #endif
-   volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
+   void __iomem *mmio = probe_ent-mmio_base;
u32 vers, cap, cap2, impl, speed;
const char *speed_s;
const char *scc_s;
@@ -462,7 +462,7 @@ static int ahci_fill_sg(u8 port, unsigned char *buf, int 
buf_len)
 
for (i = 0; i  sg_count; i++) {
ahci_sg-addr =
-   

[U-Boot] [PATCH] ahci: Fix compiling warnings under 64bit platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

When compling under 64bit platforms, there are lots of warnings,
like:

drivers/block/ahci.c:114:18: warning: cast to pointer from integer
 of different size [-Wint-to-pointer-cast]
  u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
  ^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
 of different size [-Wpointer-to-int-cast]
   probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);

..

Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 drivers/block/ahci.c | 46 --
 include/ahci.h   |  6 +++---
 2 files changed, 27 insertions(+), 25 deletions(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 4fb846a..090beed 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -43,13 +43,13 @@ u16 *ataid[AHCI_MAX_PORTS];
 #define WAIT_MS_FLUSH  5000
 #define WAIT_MS_LINKUP 200
 
-static inline u32 ahci_port_base(u32 base, u32 port)
+static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
 {
return base + 0x100 + (port * 0x80);
 }
 
 
-static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
+static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
unsigned int port_idx)
 {
base = ahci_port_base(base, port_idx);
@@ -61,7 +61,7 @@ static void ahci_setup_port(struct ahci_ioports *port, 
unsigned long base,
 
 #define msleep(a) udelay(a * 1000)
 
-static void ahci_dcache_flush_range(unsigned begin, unsigned len)
+static void ahci_dcache_flush_range(unsigned long begin, unsigned len)
 {
const unsigned long start = begin;
const unsigned long end = start + len;
@@ -75,7 +75,7 @@ static void ahci_dcache_flush_range(unsigned begin, unsigned 
len)
  * controller is invalidated from dcache; next access comes from
  * physical RAM.
  */
-static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
+static void ahci_dcache_invalidate_range(unsigned long begin, unsigned len)
 {
const unsigned long start = begin;
const unsigned long end = start + len;
@@ -111,7 +111,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, 
u8 port)
 {
u32 tmp;
int j = 0;
-   u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;
+   void __iomem *port_mmio = probe_ent-port[port].port_mmio;
 
/*
 * Bring up SATA link.
@@ -171,10 +171,10 @@ static int ahci_host_init(struct ahci_probe_ent 
*probe_ent)
u16 tmp16;
unsigned short vendor;
 #endif
-   volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
+   void __iomem *mmio = probe_ent-mmio_base;
u32 tmp, cap_save, cmd;
int i, j, ret;
-   volatile u8 *port_mmio;
+   void __iomem *port_mmio;
u32 port_map;
 
debug(ahci_host_init: start\n);
@@ -215,9 +215,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
for (i = 0; i  probe_ent-n_ports; i++) {
if (!(port_map  (1  i)))
continue;
-   probe_ent-port[i].port_mmio = ahci_port_base((u32) mmio, i);
+   probe_ent-port[i].port_mmio = ahci_port_base(mmio, i);
port_mmio = (u8 *) probe_ent-port[i].port_mmio;
-   ahci_setup_port(probe_ent-port[i], (unsigned long)mmio, i);
+   ahci_setup_port(probe_ent-port[i], mmio, i);
 
/* make sure port is not active */
tmp = readl(port_mmio + PORT_CMD);
@@ -462,7 +462,7 @@ static int ahci_fill_sg(u8 port, unsigned char *buf, int 
buf_len)
 
for (i = 0; i  sg_count; i++) {
ahci_sg-addr =
-   cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
+   cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
ahci_sg-addr_hi = 0;
ahci_sg-flags_size = cpu_to_le32(0x3f 
  (buf_len  MAX_DATA_BYTE_COUNT
@@ -501,7 +501,7 @@ static void ahci_set_feature(u8 port)
fis[3] = SETFEATURES_XFER;
fis[12] = __ilog2(probe_ent-udma_mask + 1) + 0x40 - 0x01;
 
-   memcpy((unsigned char *)pp-cmd_tbl, fis, sizeof(fis));
+   memcpy((void *)(unsigned long)pp-cmd_tbl, fis, sizeof(fis));
ahci_fill_cmd_slot(pp, cmd_fis_len);
ahci_dcache_flush_sata_cmd(pp);
writel(1, port_mmio + PORT_CMD_ISSUE);
@@ -532,9 +532,9 @@ static int wait_spinup(volatile u8 *port_mmio)
 static int ahci_port_start(u8 port)
 {
struct ahci_ioports *pp = (probe_ent-port[port]);
-   volatile u8 *port_mmio = (volatile u8 *)pp-port_mmio;
+   void __iomem *port_mmio = pp-port_mmio;
u32 port_status;
-   u32 mem;
+   void __iomem *mem;
 
debug(Enter start port: %d\n, port);
port_status = 

[U-Boot] [PATCH] ls1021atwr: added deep sleep support in uboot

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 ++
 board/freescale/ls1021atwr/ls1021atwr.c   | 68 ++-
 include/configs/ls1021atwr.h  |  7 ++-
 3 files changed, 75 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index a8122c1..bbd5955 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -370,6 +370,10 @@ struct ccsr_serdes {
 #define DDR_DDR_ZQ_CNTL0x89080600
 #define DDR_CS0_CONFIG_2   0
 #define DDR_SDRAM_CFG_MEM_EN   0x8000
+#define SDRAM_CFG2_D_INIT  0x0010
+#define DDR_CDR2_VREF_TRAIN_EN 0x0080
+#define SDRAM_CFG2_FRC_SR  0x8000
+#define SDRAM_CFG_BI   0x0001
 
 /* DDR memory controller registers */
 struct ccsr_ddr {
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index ed5bd27..2c8d6d1 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -21,6 +21,7 @@
 #include tsec.h
 #include fsl_sec.h
 #include spl.h
+#include ../common/sleep.h
 #ifdef CONFIG_U_QE
 #include ../../../drivers/qe/qe.h
 #endif
@@ -147,6 +148,7 @@ unsigned int get_soc_major_rev(void)
 void ddrmc_init(void)
 {
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+   u32 temp_sdram_cfg;
 
out_be32(ddr-sdram_cfg, DDR_SDRAM_CFG);
 
@@ -160,7 +162,22 @@ void ddrmc_init(void)
out_be32(ddr-timing_cfg_4, DDR_TIMING_CFG_4);
out_be32(ddr-timing_cfg_5, DDR_TIMING_CFG_5);
 
-   out_be32(ddr-sdram_cfg_2,  DDR_SDRAM_CFG_2);
+#ifdef CONFIG_DEEP_SLEEP
+   if (is_warm_boot()) {
+   out_be32(ddr-sdram_cfg_2,
+DDR_SDRAM_CFG_2  ~SDRAM_CFG2_D_INIT);
+   out_be32(ddr-init_addr, CONFIG_SYS_SDRAM_BASE);
+   out_be32(ddr-init_ext_addr, (1  31));
+
+   /* DRAM VRef will not be trained */
+   out_be32(ddr-ddr_cdr2,
+DDR_DDR_CDR2  ~DDR_CDR2_VREF_TRAIN_EN);
+   } else
+#endif
+   {
+   out_be32(ddr-sdram_cfg_2, DDR_SDRAM_CFG_2);
+   out_be32(ddr-ddr_cdr2, DDR_DDR_CDR2);
+   }
 
out_be32(ddr-sdram_mode, DDR_SDRAM_MODE);
out_be32(ddr-sdram_mode_2, DDR_SDRAM_MODE_2);
@@ -173,14 +190,35 @@ void ddrmc_init(void)
out_be32(ddr-ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 
out_be32(ddr-ddr_cdr1, DDR_DDR_CDR1);
-   out_be32(ddr-ddr_cdr2, DDR_DDR_CDR2);
 
out_be32(ddr-sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
out_be32(ddr-ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 
out_be32(ddr-cs0_config_2, DDR_CS0_CONFIG_2);
udelay(1);
-   out_be32(ddr-sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
+
+#ifdef CONFIG_DEEP_SLEEP
+   if (is_warm_boot()) {
+   /* enter self-refresh */
+   temp_sdram_cfg = in_be32(ddr-sdram_cfg_2);
+   temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+   out_be32(ddr-sdram_cfg_2, temp_sdram_cfg);
+
+   temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+   } else
+#endif
+   temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN  ~SDRAM_CFG_BI);
+
+   out_be32(ddr-sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+   if (is_warm_boot()) {
+   /* exit self-refresh */
+   temp_sdram_cfg = in_be32(ddr-sdram_cfg_2);
+   temp_sdram_cfg = ~SDRAM_CFG2_FRC_SR;
+   out_be32(ddr-sdram_cfg_2, temp_sdram_cfg);
+   }
+#endif
 }
 
 int dram_init(void)
@@ -190,6 +228,11 @@ int dram_init(void)
 #endif
 
gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP)  !defined(CONFIG_SPL_BUILD)
+   fsl_dp_resume();
+#endif
+
return 0;
 }
 
@@ -384,6 +427,11 @@ int board_early_init_f(void)
out_le32(cci-slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
}
 
+#if defined(CONFIG_DEEP_SLEEP)
+   if (is_warm_boot())
+   fsl_dp_disable_console();
+#endif
+
return 0;
 }
 
@@ -395,6 +443,11 @@ void board_init_f(ulong dummy)
 
get_clocks();
 
+#if defined(CONFIG_DEEP_SLEEP)
+   if (is_warm_boot())
+   fsl_dp_disable_console();
+#endif
+
preloader_console_init();
 
dram_init();
@@ -563,6 +616,15 @@ int misc_init_r(void)
 }
 #endif
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LS102XA_NS_ACCESS
+   enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
ft_cpu_setup(blob, bd);
diff --git a/include/configs/ls1021atwr.h 

[U-Boot] [PATCH] fsl/sata: Replace sprintf() with snprintf()

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Function 'sprintf' does not check buffer boundaries but outputs
to the buffer of fixed size which could cause buffer overflow.
Use a safer function to replace it.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 drivers/block/fsl_sata.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index 71d7cec..e720c3e 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -113,7 +113,7 @@ int init_sata(int dev)
/* Save the private struct to block device struct */
sata_dev_desc[dev].priv = (void *)sata;
 
-   sprintf(sata-name, SATA%d, dev);
+   snprintf(sata-name, 7, SATA%d, dev);
 
/* Set the controller register base address to device struct */
reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] fsl/sata: Replace sprintf() with snprintf()

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Function 'sprintf' does not check buffer boundaries but outputs
to the buffer of fixed size which could potentially cause buffer
overflow. Use a safer function to replace it.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 drivers/block/fsl_sata.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index 71d7cec..735708a 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -113,7 +113,7 @@ int init_sata(int dev)
/* Save the private struct to block device struct */
sata_dev_desc[dev].priv = (void *)sata;
 
-   sprintf(sata-name, SATA%d, dev);
+   snprintf(sata-name, 12, SATA%d, dev);
 
/* Set the controller register base address to device struct */
reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] fsl/deepsleep: avoid the DDR restore from being optimized out

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Function dp_ddr_restore is to restore the first 128-byte space
of DDR. However those codes may be optimized out by compiler
since the destination address is at 0x0. In order to avoid
compiler optimization, we restore the space from high address,
which is not at 0x0, to low address.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/common/mpc85xx_sleep.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/common/mpc85xx_sleep.c 
b/board/freescale/common/mpc85xx_sleep.c
index 9e4132c..e9cbd51 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -43,16 +43,16 @@ void fsl_dp_disable_console(void)
  */
 static void dp_ddr_restore(void)
 {
-   volatile u64 *src, *dst;
+   u64 *src, *dst;
int i;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
 
/* get the address of ddr date from SPARECR3 */
-   src = (u64 *)in_be32(scfg-sparecr[2]);
-   dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+   src = (u64 *)(in_be32(scfg-sparecr[2]) + DDR_BUFF_LEN - 8);
+   dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
 
for (i = 0; i  DDR_BUFF_LEN / 8; i++)
-   *dst++ = *src++;
+   *dst-- = *src--;
 
flush_dcache();
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] ahci: Fix a wrong parameter pass

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

In stead of user_buffer_size, transfer_size should be used to pass to
ahci_device_data_io(). transfer_size is the length that we want the
low level function to transfer each time.
If we use user_buffer_size which is the totally data length as parameter,
low level function will actually create many SGs to transfer as many data
as possible each time. That will produce many redundant data transfer.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 drivers/block/ahci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index c908fab..88b90e0 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -785,7 +785,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
 
/* Read/Write from ahci */
if (ahci_device_data_io(pccb-target, (u8 *) fis, sizeof(fis),
-   user_buffer, user_buffer_size,
+   user_buffer, transfer_size,
is_write)) {
debug(scsi_ahci: SCSI %s10 command failure.\n,
  is_write ? WRITE : READ);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] fsl/sleep: updated the deep sleep framework for QorIQ platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/common/Makefile|  6 +++
 board/freescale/common/arm_sleep.c | 95 ++
 board/freescale/common/mpc85xx_sleep.c | 88 +++
 board/freescale/common/sleep.h | 21 
 drivers/ddr/fsl/arm_ddr_gen3.c | 45 +---
 drivers/ddr/fsl/fsl_ddr_gen4.c | 44 ++--
 drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 67 +---
 include/fsl_ddr_sdram.h| 12 +++--
 8 files changed, 322 insertions(+), 56 deletions(-)
 create mode 100644 board/freescale/common/arm_sleep.c
 create mode 100644 board/freescale/common/mpc85xx_sleep.c
 create mode 100644 board/freescale/common/sleep.h

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 32b5a3b..d1b6e3c 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -36,6 +36,12 @@ endif
 
 obj-$(CONFIG_FSL_DIU_CH7301)   += diu_ch7301.o
 
+ifdef CONFIG_ARM
+obj-$(CONFIG_DEEP_SLEEP)   += arm_sleep.o
+else
+obj-$(CONFIG_DEEP_SLEEP)   += mpc85xx_sleep.o
+endif
+
 obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
 
 obj-$(CONFIG_MPC8541CDS)   += cds_pci_ft.o
diff --git a/board/freescale/common/arm_sleep.c 
b/board/freescale/common/arm_sleep.c
new file mode 100644
index 000..8edf878
--- /dev/null
+++ b/board/freescale/common/arm_sleep.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
+#error  Deep sleep needs non-secure mode support. 
+#else
+#include asm/secure.h
+#endif
+#include asm/armv7.h
+#include asm/cache.h
+
+#if defined(CONFIG_LS102XA)
+#include asm/arch/immap_ls102xa.h
+#endif
+
+#include sleep.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+   if (in_be32(gur-crstsr)  DCFG_CCSR_CRSTSR_WDRFR)
+   return 1;
+
+   return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+   gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+   u64 *src, *dst;
+   int i;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   /* get the address of ddr date from SPARECR3 */
+   src = (u64 *)in_le32(scfg-sparecr[2]);
+   dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+   for (i = 0; i  DDR_BUFF_LEN / 8; i++)
+   *dst++ = *src++;
+
+   flush_dcache_all();
+}
+
+static void dp_resume_prepare(void)
+{
+   dp_ddr_restore();
+   board_sleep_prepare();
+   armv7_init_nonsec();
+   cleanup_before_linux();
+}
+
+int fsl_dp_resume(void)
+{
+   u32 start_addr;
+   void (*kernel_resume)(void);
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   if (!is_warm_boot())
+   return 0;
+
+   dp_resume_prepare();
+
+   /* Get the entry address and jump to kernel */
+   start_addr = in_le32(scfg-sparecr[1]);
+   debug(Entry address is 0x%08x\n, start_addr);
+   kernel_resume = (void (*)(void))start_addr;
+   secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+   return 0;
+}
diff --git a/board/freescale/common/mpc85xx_sleep.c 
b/board/freescale/common/mpc85xx_sleep.c
new file mode 100644
index 000..f924e7f
--- /dev/null
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/immap_85xx.h
+#include sleep.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+   if (in_be32(gur-scrtsr[0])  DCFG_CCSR_CRSTSR_WDRFR)
+   return 1;
+
+   return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+   gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR 

[U-Boot] [PATCH] mpc85xx/t104xrdb: convert deep sleep to generic board interface

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

A new interface is introduced to support generic board structure.
Converts it to use new interface.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/t104xrdb/ddr.c  | 19 +++
 board/freescale/t104xrdb/spl.c  | 19 +++
 board/freescale/t104xrdb/t104xrdb.c | 24 +++-
 include/configs/T104xRDB.h  |  3 +++
 4 files changed, 36 insertions(+), 29 deletions(-)

diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 2c331ee..5aa11b1 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -11,6 +11,7 @@
 #include fsl_ddr_sdram.h
 #include fsl_ddr_dimm_params.h
 #include asm/fsl_law.h
+#include asm/mpc85xx_gpio.h
 #include ddr.h
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -109,6 +110,19 @@ found:
popts-ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 }
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+   void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+   /* does not provide HW signals for power management */
+   clrbits_8(cpld_base + 0x17, 0x40);
+   /* Disable MCKE isolation */
+   gpio_set_value(2, 0);
+   udelay(1);
+}
+#endif
+
 phys_size_t initdram(int board_type)
 {
phys_size_t dram_size;
@@ -124,5 +138,10 @@ phys_size_t initdram(int board_type)
 #else
dram_size =  fsl_ddr_sdram_size();
 #endif
+
+#if defined(CONFIG_DEEP_SLEEP)  !defined(CONFIG_SPL_BUILD)
+   fsl_dp_resume();
+#endif
+
return dram_size;
 }
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 3822a37..b248f3b 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -11,7 +11,7 @@
 #include mmc.h
 #include fsl_esdhc.h
 #include spi_flash.h
-#include asm/mpc85xx_gpio.h
+#include ../common/sleep.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -58,8 +58,8 @@ void board_init_f(ulong bootflag)
 
 #ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
-   if (in_be32(gur-scrtsr[0])  (1  3))
-   gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+   if (is_warm_boot())
+   fsl_dp_disable_console();
 #endif
/* compiler optimization barrier needed for GCC = 3.4 */
__asm__ __volatile__( : : : memory);
@@ -126,16 +126,3 @@ void board_init_r(gd_t *gd, ulong dest_addr)
nand_boot();
 #endif
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-   void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
-
-   /* does not provide HW signals for power management */
-   clrbits_8(cpld_base + 0x17, 0x40);
-   /* Disable MCKE isolation */
-   gpio_set_value(2, 0);
-   udelay(1);
-}
-#endif
diff --git a/board/freescale/t104xrdb/t104xrdb.c 
b/board/freescale/t104xrdb/t104xrdb.c
index ddb669f..abca297 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -17,8 +17,7 @@
 #include asm/fsl_portals.h
 #include asm/fsl_liodn.h
 #include fm_eth.h
-#include asm/mpc85xx_gpio.h
-
+#include ../common/sleep.h
 #include t104xrdb.h
 #include cpld.h
 
@@ -44,6 +43,16 @@ int checkboard(void)
return 0;
 }
 
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+   if (is_warm_boot())
+   fsl_dp_disable_console();
+#endif
+
+   return 0;
+}
+
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE
@@ -111,14 +120,3 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
 #endif
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-   /* does not provide HW signals for power management */
-   CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status)  ~0x40));
-   /* Disable MCKE isolation */
-   gpio_set_value(2, 0);
-   udelay(1);
-}
-#endif
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 2bb86e4..36ac66d 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -100,7 +100,10 @@
 
 /* support deep sleep */
 #define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
+#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_SILENT_CONSOLE
+#endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE   0xeff4
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3] powerpc: add deep sleep support for generic board

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Deep sleep for generic board is not supported on PowerPC.
This patch make deep sleep work for both non-generic
board and generic board on PowerPC platforms.
For ARM-based QorIQ platforms, deep sleep has been
already supported.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 README  |  2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c |  2 +-
 arch/powerpc/cpu/mpc85xx/fdt.c  |  2 +-
 arch/powerpc/lib/board.c| 24 ++--
 drivers/ddr/fsl/mpc85xx_ddr_gen3.c  | 37 ++---
 drivers/qe/qe.c |  8 
 6 files changed, 27 insertions(+), 48 deletions(-)

diff --git a/README b/README
index 48061b4..194bdf0 100644
--- a/README
+++ b/README
@@ -442,7 +442,7 @@ The following options need to be configured:
This CONFIG is defined when the CPC is configured as SRAM at the
time of U-boot entry and is required to be re-initialized.
 
-   CONFIG_DEEP_SLEEP
+   CONFIG_FSL_DEEP_SLEEP
Inidcates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index bd397aa..267d366 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -479,7 +479,7 @@ ulong cpu_init_f(void)
 #endif
 
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
-#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_FSL_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(gur-scrtsr[0])  (1  3))
flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 61d7b81..2695941 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -134,7 +134,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
printf(Failed to reserve memory for spin table: %s\n,
fdt_strerror(off));
}
-#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_FSL_DEEP_SLEEP
 #ifdef CONFIG_SPL_MMC_BOOT
off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
CONFIG_SYS_MMC_U_BOOT_SIZE);
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 50eb820..ff49116 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -113,6 +113,9 @@ ulong monitor_flash_len;
 #include bedbug/type.h
 #endif
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 /*
  * Utilities
  */
@@ -343,13 +346,6 @@ void board_init_f(ulong bootflag)
 #ifdef CONFIG_PRAM
ulong reg;
 #endif
-#ifdef CONFIG_DEEP_SLEEP
-   const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
-   u32 start_addr;
-   typedef void (*func_t)(void);
-   func_t kernel_resume;
-#endif
 
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -367,18 +363,10 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0)
hang();
 
-#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_FSL_DEEP_SLEEP
/* Jump to kernel in deep sleep case */
-   if (in_be32(gur-scrtsr[0])  (1  3)) {
-   l2cache_init();
-#if defined(CONFIG_RAMBOOT_PBL)
-   disable_cpc_sram();
-#endif
-   enable_cpc();
-   start_addr = in_be32(scfg-sparecr[1]);
-   kernel_resume = (func_t)start_addr;
-   kernel_resume();
-   }
+   if (is_warm_boot())
+   fsl_dp_resume();
 #endif
 
 #ifdef CONFIG_POST
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c 
b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 4d5572e..194a714 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -10,13 +10,14 @@
 #include asm/io.h
 #include fsl_ddr_sdram.h
 #include asm/processor.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL  4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 #endif
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /*
  * regs has the to-be-set values for DDR controller registers
  * ctrl_num is the DDR controller number
@@ -44,16 +45,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 save1, save2;
 #endif
 
-#ifdef CONFIG_DEEP_SLEEP
-   const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-   bool sleep_flag = 0;
-#endif
-
-#ifdef CONFIG_DEEP_SLEEP
-   if (in_be32(gur-scrtsr[0])  (1  3))
-   sleep_flag = 1;
-#endif
-
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -130,8 +121,8 @@ void fsl_ddr_set_memctl_regs(const 

[U-Boot] [PATCH] powerpc/t104xrdb: add deep sleep support

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Added deep sleep support on T104xRDB platforms.
Support both SD/SPI boot and NOR boot.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/t104xrdb/spl.c  | 41 +++--
 board/freescale/t104xrdb/t104xrdb.c | 60 +++--
 include/configs/T104xRDB.h  |  2 +-
 3 files changed, 85 insertions(+), 18 deletions(-)

diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index e394b12..5b39ffa 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -15,6 +15,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1  3)
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+   if (in_be32(gur-scrtsr[0])  DCFG_CCSR_CRSTSR_WDRFR)
+   return 1;
+
+   return 0;
+}
+
+void fsl_dp_mem_setup(void)
+{
+   void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+   /* does not provide HW signals for power management */
+   clrbits_8(cpld_base + 0x17, 0x40);
+   /* Disable MCKE isolation */
+   gpio_set_value(2, 0);
+   udelay(1);
+}
+#endif
+
 phys_size_t get_effective_memsize(void)
 {
return CONFIG_SYS_L3_SIZE;
@@ -62,9 +86,9 @@ void board_init_f(ulong bootflag)
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
 
-#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_FSL_DEEP_SLEEP
/* disable the console if boot from deep sleep */
-   if (in_be32(gur-scrtsr[0])  (1  3))
+   if (is_warm_boot())
gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
 #endif
/* compiler optimization barrier needed for GCC = 3.4 */
@@ -132,16 +156,3 @@ void board_init_r(gd_t *gd, ulong dest_addr)
nand_boot();
 #endif
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-   void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
-
-   /* does not provide HW signals for power management */
-   clrbits_8(cpld_base + 0x17, 0x40);
-   /* Disable MCKE isolation */
-   gpio_set_value(2, 0);
-   udelay(1);
-}
-#endif
diff --git a/board/freescale/t104xrdb/t104xrdb.c 
b/board/freescale/t104xrdb/t104xrdb.c
index a5e5fff..8b41380 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -106,8 +106,20 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 }
 
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1  3)
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+   if (in_be32(gur-scrtsr[0])  DCFG_CCSR_CRSTSR_WDRFR)
+   return 1;
+
+   return 0;
+}
+
+void fsl_dp_mem_setup(void)
 {
/* does not provide HW signals for power management */
CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status)  ~0x40));
@@ -115,4 +127,48 @@ void board_mem_sleep_setup(void)
gpio_set_value(2, 0);
udelay(1);
 }
+
+void fsl_dp_ddr_restore(void)
+{
+#define DDR_BUFF_LEN   128
+   volatile u64 *src, *dst;
+   int i;
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+   if (!is_warm_boot())
+   return;
+
+   /* get the address of ddr date from SPARECR3 */
+   src = (u64 *)in_be32(scfg-sparecr[2]);
+   dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+   for (i = 0; i  DDR_BUFF_LEN / 8; i++)
+   *dst++ = *src++;
+}
+
+int fsl_dp_resume(void)
+{
+   u32 start_addr;
+   void (*kernel_resume)(void);
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+   if (!is_warm_boot())
+   return 0;
+
+   fsl_dp_ddr_restore();
+
+   l2cache_init();
+#if defined(CONFIG_RAMBOOT_PBL)
+   disable_cpc_sram();
+#endif
+   enable_cpc();
+
+   /* Get the entry address and jump to kernel */
+   start_addr = in_be32(scfg-sparecr[1]);
+   debug(Entry address is 0x%08x\n, start_addr);
+   kernel_resume = (void (*)(void))start_addr;
+   kernel_resume();
+
+   return 0;
+}
 #endif
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 1f5d39e..62dbfc4 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -99,7 +99,7 @@
 #define CONFIG_MP  /* support multiple processors */
 
 /* support deep sleep */
-#define CONFIG_DEEP_SLEEP
+#define CONFIG_FSL_DEEP_SLEEP
 #define CONFIG_SILENT_CONSOLE
 
 #ifndef CONFIG_SYS_TEXT_BASE
-- 
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[U-Boot] [PATCH 3/3] powerpc/t102xrdb: add deep sleep support

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Added deep sleep support on T102xRDB platforms.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/t102xrdb/t102xrdb.c | 66 +
 include/configs/T102xRDB.h  |  2 +-
 2 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/board/freescale/t102xrdb/t102xrdb.c 
b/board/freescale/t102xrdb/t102xrdb.c
index 8fb426e..7f8c3b0 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -149,3 +149,69 @@ void board_mem_sleep_setup(void)
udelay(1);
 }
 #endif
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1  3)
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+   if (in_be32(gur-scrtsr[0])  DCFG_CCSR_CRSTSR_WDRFR)
+   return 1;
+
+   return 0;
+}
+
+void fsl_dp_mem_setup(void)
+{
+   /* does not provide HW signals for power management */
+   CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status)  ~0x40));
+   /* Disable MCKE isolation */
+   gpio_set_value(2, 0);
+   udelay(1);
+}
+
+void fsl_dp_ddr_restore(void)
+{
+#define DDR_BUFF_LEN   128
+   volatile u64 *src, *dst;
+   int i;
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+   if (!is_warm_boot())
+   return;
+
+   /* get the address of ddr date from SPARECR3 */
+   src = (u64 *)in_be32(scfg-sparecr[2]);
+   dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+   for (i = 0; i  DDR_BUFF_LEN / 8; i++)
+   *dst++ = *src++;
+}
+
+int fsl_dp_resume(void)
+{
+   u32 start_addr;
+   void (*kernel_resume)(void);
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+   if (!is_warm_boot())
+   return 0;
+
+   fsl_dp_ddr_restore();
+
+   l2cache_init();
+#if defined(CONFIG_RAMBOOT_PBL)
+   disable_cpc_sram();
+#endif
+   enable_cpc();
+
+   /* Get the entry address and jump to kernel */
+   start_addr = in_be32(scfg-sparecr[1]);
+   debug(Entry address is 0x%08x\n, start_addr);
+   kernel_resume = (void (*)(void))start_addr;
+   kernel_resume();
+
+   return 0;
+}
+#endif
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index e575784..42a0240 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -35,7 +35,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* support deep sleep */
-#define CONFIG_DEEP_SLEEP
+#define CONFIG_FSL_DEEP_SLEEP
 #define CONFIG_SILENT_CONSOLE
 
 #ifdef CONFIG_RAMBOOT_PBL
-- 
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[U-Boot] [PATCH] mpc85xx/p1022ds: convert to generic board

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 include/configs/P1022DS.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 54e2569..de0613f 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -11,6 +11,9 @@
 
 #include ../board/freescale/common/ics307_clk.h
 
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
 #ifdef CONFIG_36BIT
 #define CONFIG_PHYS_64BIT
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] arm: ls102xa: fixed a bus frequency setting error

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

The bus frequency in SOC node should be clock frequency of platform.
That is not true if it is devided by 2.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 4ce3808..989780d 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -91,7 +91,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
}
 
do_fixup_by_prop_u32(blob, device_type, soc,
-4, bus-frequency, busclk / 2, 1);
+4, bus-frequency, busclk, 1);
 
ft_fixup_enet_phy_connect_type(blob);
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

When Freescale QorIQ SoCs wake up from deep sleep, control is
passed to the primary core that starts executing uboot. After
re-initialized some IP blocks, like DDRC, kernel will take
responsibility to continue to restore environment it leaves before.

This patch adds the deep sleep framework support for all Freescale
QorIQ platforms that use generic_board configuation.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 common/board_f.c   | 10 +
 drivers/ddr/fsl/arm_ddr_gen3.c | 48 +-
 include/fsl_ddr_sdram.h|  2 ++
 include/fsl_sleep.h| 32 
 4 files changed, 87 insertions(+), 5 deletions(-)
 create mode 100644 include/fsl_sleep.h

diff --git a/common/board_f.c b/common/board_f.c
index e6aa298..b736d29 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -56,6 +56,9 @@
 #endif
 #include dm/root.h
 #include linux/compiler.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 
 /*
  * Pointer to initial global data area
@@ -921,6 +924,9 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
init_func_ram,
 #endif
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   fsl_dp_resume,
+#endif
 #ifdef CONFIG_POST
post_init_f,
 #endif
@@ -1027,6 +1033,10 @@ void board_init_f(ulong boot_flags)
gd-flags = boot_flags;
gd-have_console = 0;
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   if (is_warm_boot())
+   gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
if (initcall_run_list(init_sequence_f))
hang();
 
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 59f2fd6..1a9d82b 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -12,6 +12,9 @@
 #include asm/processor.h
 #include fsl_immap.h
 #include fsl_ddr.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL  4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -92,7 +95,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(ddr-timing_cfg_0, regs-timing_cfg_0);
ddr_out32(ddr-timing_cfg_1, regs-timing_cfg_1);
ddr_out32(ddr-timing_cfg_2, regs-timing_cfg_2);
-   ddr_out32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2);
ddr_out32(ddr-sdram_mode, regs-ddr_sdram_mode);
ddr_out32(ddr-sdram_mode_2, regs-ddr_sdram_mode_2);
ddr_out32(ddr-sdram_mode_3, regs-ddr_sdram_mode_3);
@@ -105,8 +107,25 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t 
*regs,
ddr_out32(ddr-sdram_interval, regs-ddr_sdram_interval);
ddr_out32(ddr-sdram_data_init, regs-ddr_data_init);
ddr_out32(ddr-sdram_clk_cntl, regs-ddr_sdram_clk_cntl);
-   ddr_out32(ddr-init_addr, regs-ddr_init_addr);
-   ddr_out32(ddr-init_ext_addr, regs-ddr_init_ext_addr);
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   if (is_warm_boot()) {
+   ddr_out32(ddr-sdram_cfg_2,
+ regs-ddr_sdram_cfg_2  ~SDRAM_CFG2_D_INIT);
+   ddr_out32(ddr-init_addr, CONFIG_SYS_SDRAM_BASE);
+   ddr_out32(ddr-init_ext_addr, (1  31));
+
+   /* DRAM VRef will not be trained */
+   temp_sdram_cfg = ddr_in32(ddr-ddr_cdr2);
+   temp_sdram_cfg = ~DDR_CDR2_VREF_TRAIN_EN;
+   ddr_out32(ddr-ddr_cdr2, temp_sdram_cfg);
+   } else
+#endif
+   {
+   ddr_out32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2);
+   ddr_out32(ddr-init_addr, regs-ddr_init_addr);
+   ddr_out32(ddr-init_ext_addr, regs-ddr_init_ext_addr);
+   ddr_out32(ddr-ddr_cdr2, regs-ddr_cdr2);
+   }
 
ddr_out32(ddr-timing_cfg_4, regs-timing_cfg_4);
ddr_out32(ddr-timing_cfg_5, regs-timing_cfg_5);
@@ -128,7 +147,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(ddr-ddr_sdram_rcw_1, regs-ddr_sdram_rcw_1);
ddr_out32(ddr-ddr_sdram_rcw_2, regs-ddr_sdram_rcw_2);
ddr_out32(ddr-ddr_cdr1, regs-ddr_cdr1);
-   ddr_out32(ddr-ddr_cdr2, regs-ddr_cdr2);
ddr_out32(ddr-err_disable, regs-err_disable);
ddr_out32(ddr-err_int_en, regs-err_int_en);
for (i = 0; i  32; i++) {
@@ -167,8 +185,20 @@ step2:
udelay(500);
asm volatile(dsb sy;isb);
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   if (is_warm_boot()) {
+   /* enter self-refresh */
+   temp_sdram_cfg = ddr_in32(ddr-sdram_cfg_2);
+   temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+   ddr_out32(ddr-sdram_cfg_2, temp_sdram_cfg);
+   /* do board specific memory setup */
+   fsl_dp_mem_setup();
+
+   temp_sdram_cfg = (ddr_in32(ddr-sdram_cfg) | SDRAM_CFG_BI);
+   } else
+#endif
+   temp_sdram_cfg = (in_be32(ddr-sdram_cfg)  ~SDRAM_CFG_BI);
/* Let the 

[U-Boot] [PATCH 3/4] arm: ls102xa: Fixed a register definition error

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

There are 8 SCFG_SPARECR registers in SCFG memory block, not one.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b5db720 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,7 +182,7 @@ struct ccsr_scfg {
u32 etsecmcr;
u32 sdhciovserlcr;
u32 resv14[61];
-   u32 sparecr;
+   u32 sparecr[8];
 };
 
 /* Clocking */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 4/4] arm: ls1021qds: Add deep sleep support

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/ls1021aqds/ddr.c|  7 
 board/freescale/ls1021aqds/ls1021aqds.c | 60 +
 include/configs/ls1021aqds.h|  4 +++
 3 files changed, 71 insertions(+)

diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 5898e33..6dad4cc 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -8,6 +8,9 @@
 #include fsl_ddr_sdram.h
 #include fsl_ddr_dimm_params.h
 #include ddr.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -156,6 +159,10 @@ phys_size_t initdram(int board_type)
puts(Initializing DDRusing SPD\n);
dram_size = fsl_ddr_sdram();
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   fsl_dp_ddr_restore();
+#endif
+
return dram_size;
 }
 
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..e9dce36 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -253,3 +253,63 @@ u16 flash_read16(void *addr)
 
return (((val)  8)  0x00ff) | (((val)  8)  0xff00);
 }
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1  3)
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+   if (in_be32(gur-crstsr)  DCFG_CCSR_CRSTSR_WDRFR)
+   return 1;
+
+   return 0;
+}
+
+void fsl_dp_mem_setup(void)
+{
+   /* does not provide HW signals for power management */
+   QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1])  ~0x2));
+   udelay(1);
+}
+
+void fsl_dp_ddr_restore(void)
+{
+#define DDR_BUFF_LEN   128
+   u64 *src, *dst;
+   int i;
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   if (!is_warm_boot())
+   return;
+
+   /* get the address of ddr date from SPARECR3, little endian */
+   src = (u64 *)in_le32(scfg-sparecr[2]);
+   dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+   for (i = 0; i  DDR_BUFF_LEN / 8; i++)
+   *dst++ = *src++;
+}
+
+int fsl_dp_resume(void)
+{
+   u32 start_addr;
+   void (*kernel_resume)(void);
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   if (!is_warm_boot())
+   return 0;
+
+   enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+   armv7_init_nonsec();
+   cleanup_before_linux();
+
+   /* Get the entry address and jump to kernel */
+   start_addr = in_le32(scfg-sparecr[1]);
+   debug(Entry address is 0x%08x\n, start_addr);
+   kernel_resume = (void (*)(void))start_addr;
+   secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+   return 0;
+}
+#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..448a07e 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -19,6 +19,10 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 
+#define CONFIG_FSL_DEEP_SLEEP
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+#endif
 /*
  * Size of malloc() pool
  */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Defining variable gic_dist_addr as a globe one prevents function
armv7_init_nonsec() from being used before relocation which is
the case in the deep sleep resume process on Freescale QorIQ SoC
platforms.
This patch removes this limitation by adding a extra same meaning
local variable. In this way, no exsiting codes get corrupts.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/arm/cpu/armv7/virt-v7.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 651ca40..e1dfce9 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -75,6 +75,7 @@ int armv7_init_nonsec(void)
 {
unsigned int reg;
unsigned itlinesnr, i;
+   unsigned long gic_base_addr;
 
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
@@ -89,23 +90,24 @@ int armv7_init_nonsec(void)
 * any access to it will trap.
 */
 
-   gic_dist_addr = get_gicd_base_address();
-   if (gic_dist_addr == -1)
+   gic_base_addr = get_gicd_base_address();
+   gic_dist_addr = gic_base_addr;
+   if (gic_base_addr == -1)
return -1;
 
/* enable the GIC distributor */
-   writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
-  gic_dist_addr + GICD_CTLR);
+   writel(readl(gic_base_addr + GICD_CTLR) | 0x03,
+  gic_base_addr + GICD_CTLR);
 
/* TYPER[4:0] contains an encoded number of available interrupts */
-   itlinesnr = readl(gic_dist_addr + GICD_TYPER)  0x1f;
+   itlinesnr = readl(gic_base_addr + GICD_TYPER)  0x1f;
 
/* set all bits in the GIC group registers to one to allow access
 * from non-secure state. The first 32 interrupts are private per
 * CPU and will be set later when enabling the GIC for each core
 */
for (i = 1; i = itlinesnr; i++)
-   writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+   writel((unsigned)-1, gic_base_addr + GICD_IGROUPRn + 4 * i);
 
 #ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

These patches depend on the following patches:
https://patchwork.ozlabs.org/patch/389949/
https://patchwork.ozlabs.org/patch/389950/
https://patchwork.ozlabs.org/patch/389951/
https://patchwork.ozlabs.org/patch/389952/

Tang Yuantian (4):
  Add deep sleep framework support for Freescale QorIQ platforms
  ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation
  arm: ls102xa: Fixed a register definition error
  arm: ls1021qds: Add deep sleep support

 arch/arm/cpu/armv7/virt-v7.c  | 14 +++---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 board/freescale/ls1021aqds/ddr.c  |  7 +++
 board/freescale/ls1021aqds/ls1021aqds.c   | 60 +++
 common/board_f.c  | 10 
 drivers/ddr/fsl/arm_ddr_gen3.c| 48 --
 include/configs/ls1021aqds.h  |  4 ++
 include/fsl_ddr_sdram.h   |  2 +
 include/fsl_sleep.h   | 32 
 9 files changed, 167 insertions(+), 12 deletions(-)
 create mode 100644 include/fsl_sleep.h

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

These patches depend on the following patches:
https://patchwork.ozlabs.org/patch/389949/
https://patchwork.ozlabs.org/patch/389950/
https://patchwork.ozlabs.org/patch/389951/
https://patchwork.ozlabs.org/patch/389952/

Tang Yuantian (4):
  Add deep sleep framework support for Freescale QorIQ platforms
  ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation
  arm: ls102xa: Fixed a register definition error
  arm: ls1021qds: Add deep sleep support

 arch/arm/cpu/armv7/virt-v7.c  | 14 +++---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 board/freescale/ls1021aqds/ddr.c  |  7 +++
 board/freescale/ls1021aqds/ls1021aqds.c   | 60 +++
 common/board_f.c  | 10 
 drivers/ddr/fsl/arm_ddr_gen3.c| 48 --
 include/configs/ls1021aqds.h  |  4 ++
 include/fsl_ddr_sdram.h   |  2 +
 include/fsl_sleep.h   | 32 
 9 files changed, 167 insertions(+), 12 deletions(-)
 create mode 100644 include/fsl_sleep.h

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/4] arm: ls102xa: Fixed a register definition error

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

There are 8 SCFG_SPARECR registers in SCFG memory block, not one.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b5db720 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,7 +182,7 @@ struct ccsr_scfg {
u32 etsecmcr;
u32 sdhciovserlcr;
u32 resv14[61];
-   u32 sparecr;
+   u32 sparecr[8];
 };
 
 /* Clocking */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Defining variable gic_dist_addr as a globe one prevents function
armv7_init_nonsec() from being used before relocation which is
the case in the deep sleep resume process on Freescale QorIQ SoC
platforms.
This patch removes this limitation by adding a extra same meaning
local variable. In this way, no exsiting codes get corrupts.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/arm/cpu/armv7/virt-v7.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 651ca40..e1dfce9 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -75,6 +75,7 @@ int armv7_init_nonsec(void)
 {
unsigned int reg;
unsigned itlinesnr, i;
+   unsigned long gic_base_addr;
 
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
@@ -89,23 +90,24 @@ int armv7_init_nonsec(void)
 * any access to it will trap.
 */
 
-   gic_dist_addr = get_gicd_base_address();
-   if (gic_dist_addr == -1)
+   gic_base_addr = get_gicd_base_address();
+   gic_dist_addr = gic_base_addr;
+   if (gic_base_addr == -1)
return -1;
 
/* enable the GIC distributor */
-   writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
-  gic_dist_addr + GICD_CTLR);
+   writel(readl(gic_base_addr + GICD_CTLR) | 0x03,
+  gic_base_addr + GICD_CTLR);
 
/* TYPER[4:0] contains an encoded number of available interrupts */
-   itlinesnr = readl(gic_dist_addr + GICD_TYPER)  0x1f;
+   itlinesnr = readl(gic_base_addr + GICD_TYPER)  0x1f;
 
/* set all bits in the GIC group registers to one to allow access
 * from non-secure state. The first 32 interrupts are private per
 * CPU and will be set later when enabling the GIC for each core
 */
for (i = 1; i = itlinesnr; i++)
-   writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+   writel((unsigned)-1, gic_base_addr + GICD_IGROUPRn + 4 * i);
 
 #ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 4/4] arm: ls1021qds: Add deep sleep support

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 board/freescale/ls1021aqds/ddr.c|  7 
 board/freescale/ls1021aqds/ls1021aqds.c | 60 +
 include/configs/ls1021aqds.h|  4 +++
 3 files changed, 71 insertions(+)

diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 5898e33..6dad4cc 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -8,6 +8,9 @@
 #include fsl_ddr_sdram.h
 #include fsl_ddr_dimm_params.h
 #include ddr.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -156,6 +159,10 @@ phys_size_t initdram(int board_type)
puts(Initializing DDRusing SPD\n);
dram_size = fsl_ddr_sdram();
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   fsl_dp_ddr_restore();
+#endif
+
return dram_size;
 }
 
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..e9dce36 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -253,3 +253,63 @@ u16 flash_read16(void *addr)
 
return (((val)  8)  0x00ff) | (((val)  8)  0xff00);
 }
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1  3)
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+   if (in_be32(gur-crstsr)  DCFG_CCSR_CRSTSR_WDRFR)
+   return 1;
+
+   return 0;
+}
+
+void fsl_dp_mem_setup(void)
+{
+   /* does not provide HW signals for power management */
+   QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1])  ~0x2));
+   udelay(1);
+}
+
+void fsl_dp_ddr_restore(void)
+{
+#define DDR_BUFF_LEN   128
+   u64 *src, *dst;
+   int i;
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   if (!is_warm_boot())
+   return;
+
+   /* get the address of ddr date from SPARECR3, little endian */
+   src = (u64 *)in_le32(scfg-sparecr[2]);
+   dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+   for (i = 0; i  DDR_BUFF_LEN / 8; i++)
+   *dst++ = *src++;
+}
+
+int fsl_dp_resume(void)
+{
+   u32 start_addr;
+   void (*kernel_resume)(void);
+   struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+   if (!is_warm_boot())
+   return 0;
+
+   enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+   armv7_init_nonsec();
+   cleanup_before_linux();
+
+   /* Get the entry address and jump to kernel */
+   start_addr = in_le32(scfg-sparecr[1]);
+   debug(Entry address is 0x%08x\n, start_addr);
+   kernel_resume = (void (*)(void))start_addr;
+   secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+   return 0;
+}
+#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..448a07e 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -19,6 +19,10 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 
+#define CONFIG_FSL_DEEP_SLEEP
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+#endif
 /*
  * Size of malloc() pool
  */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

When Freescale QorIQ SoCs wake up from deep sleep, control is
passed to the primary core that starts executing uboot. After
re-initialized some IP blocks, like DDRC, kernel will take
responsibility to continue to restore environment it leaves before.

This patch adds the deep sleep framework support for all Freescale
QorIQ platforms that use generic_board configuation.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 common/board_f.c   | 10 +
 drivers/ddr/fsl/arm_ddr_gen3.c | 48 +-
 include/fsl_ddr_sdram.h|  2 ++
 include/fsl_sleep.h| 32 
 4 files changed, 87 insertions(+), 5 deletions(-)
 create mode 100644 include/fsl_sleep.h

diff --git a/common/board_f.c b/common/board_f.c
index e6aa298..b736d29 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -56,6 +56,9 @@
 #endif
 #include dm/root.h
 #include linux/compiler.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 
 /*
  * Pointer to initial global data area
@@ -921,6 +924,9 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
init_func_ram,
 #endif
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   fsl_dp_resume,
+#endif
 #ifdef CONFIG_POST
post_init_f,
 #endif
@@ -1027,6 +1033,10 @@ void board_init_f(ulong boot_flags)
gd-flags = boot_flags;
gd-have_console = 0;
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   if (is_warm_boot())
+   gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
if (initcall_run_list(init_sequence_f))
hang();
 
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 59f2fd6..1a9d82b 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -12,6 +12,9 @@
 #include asm/processor.h
 #include fsl_immap.h
 #include fsl_ddr.h
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include fsl_sleep.h
+#endif
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL  4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -92,7 +95,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(ddr-timing_cfg_0, regs-timing_cfg_0);
ddr_out32(ddr-timing_cfg_1, regs-timing_cfg_1);
ddr_out32(ddr-timing_cfg_2, regs-timing_cfg_2);
-   ddr_out32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2);
ddr_out32(ddr-sdram_mode, regs-ddr_sdram_mode);
ddr_out32(ddr-sdram_mode_2, regs-ddr_sdram_mode_2);
ddr_out32(ddr-sdram_mode_3, regs-ddr_sdram_mode_3);
@@ -105,8 +107,25 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t 
*regs,
ddr_out32(ddr-sdram_interval, regs-ddr_sdram_interval);
ddr_out32(ddr-sdram_data_init, regs-ddr_data_init);
ddr_out32(ddr-sdram_clk_cntl, regs-ddr_sdram_clk_cntl);
-   ddr_out32(ddr-init_addr, regs-ddr_init_addr);
-   ddr_out32(ddr-init_ext_addr, regs-ddr_init_ext_addr);
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   if (is_warm_boot()) {
+   ddr_out32(ddr-sdram_cfg_2,
+ regs-ddr_sdram_cfg_2  ~SDRAM_CFG2_D_INIT);
+   ddr_out32(ddr-init_addr, CONFIG_SYS_SDRAM_BASE);
+   ddr_out32(ddr-init_ext_addr, (1  31));
+
+   /* DRAM VRef will not be trained */
+   temp_sdram_cfg = ddr_in32(ddr-ddr_cdr2);
+   temp_sdram_cfg = ~DDR_CDR2_VREF_TRAIN_EN;
+   ddr_out32(ddr-ddr_cdr2, temp_sdram_cfg);
+   } else
+#endif
+   {
+   ddr_out32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2);
+   ddr_out32(ddr-init_addr, regs-ddr_init_addr);
+   ddr_out32(ddr-init_ext_addr, regs-ddr_init_ext_addr);
+   ddr_out32(ddr-ddr_cdr2, regs-ddr_cdr2);
+   }
 
ddr_out32(ddr-timing_cfg_4, regs-timing_cfg_4);
ddr_out32(ddr-timing_cfg_5, regs-timing_cfg_5);
@@ -128,7 +147,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(ddr-ddr_sdram_rcw_1, regs-ddr_sdram_rcw_1);
ddr_out32(ddr-ddr_sdram_rcw_2, regs-ddr_sdram_rcw_2);
ddr_out32(ddr-ddr_cdr1, regs-ddr_cdr1);
-   ddr_out32(ddr-ddr_cdr2, regs-ddr_cdr2);
ddr_out32(ddr-err_disable, regs-err_disable);
ddr_out32(ddr-err_int_en, regs-err_int_en);
for (i = 0; i  32; i++) {
@@ -167,8 +185,20 @@ step2:
udelay(500);
asm volatile(dsb sy;isb);
 
+#ifdef CONFIG_FSL_DEEP_SLEEP
+   if (is_warm_boot()) {
+   /* enter self-refresh */
+   temp_sdram_cfg = ddr_in32(ddr-sdram_cfg_2);
+   temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+   ddr_out32(ddr-sdram_cfg_2, temp_sdram_cfg);
+   /* do board specific memory setup */
+   fsl_dp_mem_setup();
+
+   temp_sdram_cfg = (ddr_in32(ddr-sdram_cfg) | SDRAM_CFG_BI);
+   } else
+#endif
+   temp_sdram_cfg = (in_be32(ddr-sdram_cfg)  ~SDRAM_CFG_BI);
/* Let the 

[U-Boot] [PATCH 1/2] powerpc/mpc85xx: Make boot flag effective

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

bootflag as a parameter is passed to board_init_f().
But it is not actually used in this function.
Make it effective by assigned it to gd-flags.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/powerpc/lib/board.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 50eb820..62a97a8 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -363,6 +363,8 @@ void board_init_f(ulong bootflag)
memset((void *) gd, 0, sizeof(gd_t));
 #endif
 
+   gd-flags = bootflag;
+
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr)
if ((*init_fnc_ptr) () != 0)
hang();
-- 
1.8.5

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[U-Boot] [PATCH 2/2] powerpc/t104xrdb: support deep sleep in SPI/SD boot

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

Add deep sleep support in SPI/SD boot. The destination address
second stage uboot image is loaded to is changed because
currently this address will be used by kernel which means
we can't reserve it for resume.

Entry point to kernel is still placed in second stage uboot.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
- deep sleep for nand boot is not supported right now due to
  the hardware limitation
- based on 'next' branch.

 arch/powerpc/cpu/mpc85xx/fdt.c | 15 +++
 board/freescale/t104xrdb/spl.c | 19 +++
 include/configs/T104xRDB.h | 18 +-
 3 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3665ec6..3222e26 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -134,6 +134,21 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
printf(Failed to reserve memory for spin table: %s\n,
fdt_strerror(off));
}
+#ifdef CONFIG_DEEP_SLEEP
+#ifdef CONFIG_SPL_MMC_BOOT
+   off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
+   CONFIG_SYS_MMC_U_BOOT_SIZE);
+   if (off  0)
+   printf(Failed to reserve memory for SD deep sleep: %s\n,
+  fdt_strerror(off));
+#elif defined(CONFIG_SPL_SPI_BOOT)
+   off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
+   CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
+   if (off  0)
+   printf(Failed to reserve memory for SPI deep sleep: %s\n,
+  fdt_strerror(off));
+#endif
+#endif
 }
 #endif
 
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index c628c95..3822a37 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -11,6 +11,7 @@
 #include mmc.h
 #include fsl_esdhc.h
 #include spi_flash.h
+#include asm/mpc85xx_gpio.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,6 +56,11 @@ void board_init_f(ulong bootflag)
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
 
+#ifdef CONFIG_DEEP_SLEEP
+   /* disable the console if boot from deep sleep */
+   if (in_be32(gur-scrtsr[0])  (1  3))
+   gd-flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
/* compiler optimization barrier needed for GCC = 3.4 */
__asm__ __volatile__( : : : memory);
 
@@ -120,3 +126,16 @@ void board_init_r(gd_t *gd, ulong dest_addr)
nand_boot();
 #endif
 }
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+   void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+   /* does not provide HW signals for power management */
+   clrbits_8(cpld_base + 0x17, 0x40);
+   /* Disable MCKE isolation */
+   gpio_set_value(2, 0);
+   udelay(1);
+}
+#endif
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index c96f03c..fe42935 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -33,7 +33,7 @@
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_FSL_LAW /* Use common FSL init code */
-#define CONFIG_SYS_TEXT_BASE   0x00201000
+#define CONFIG_SYS_TEXT_BASE   0x30001000
 #define CONFIG_SPL_TEXT_BASE   0xFFFD8000
 #define CONFIG_SPL_PAD_TO  0x4
 #define CONFIG_SPL_MAX_SIZE0x28000
@@ -49,21 +49,21 @@
 #ifdef CONFIG_NAND
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SYS_NAND_U_BOOT_SIZE(768  10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x0020
-#define CONFIG_SYS_NAND_U_BOOT_START   0x0020
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x3000
+#define CONFIG_SYS_NAND_U_BOOT_START   0x3000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256  10)
 #define CONFIG_SYS_LDSCRIPTarch/powerpc/cpu/mpc85xx/u-boot-nand.lds
 #define CONFIG_SPL_NAND_BOOT
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#defineCONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#defineCONFIG_RESET_VECTOR_ADDRESS 0x3FFC
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE   (768  10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST(0x0020)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START  (0x0020)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST(0x3000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START  (0x3000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS   (256  10)
 #define CONFIG_SYS_LDSCRIPTarch/powerpc/cpu/mpc85xx/u-boot.lds
 #ifndef CONFIG_SPL_BUILD
@@ -73,12 +73,12 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#defineCONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#defineCONFIG_RESET_VECTOR_ADDRESS 0x3FFC
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_MMC_MINIMAL
 #define 

[U-Boot] [PATCH 1/2 v2] mpc85xx: Add support for the supplement configuration unit register

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- no change

 arch/powerpc/include/asm/immap_85xx.h | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 9d08321..ad2532a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -3124,4 +3124,26 @@ struct dcsr_dcfg_regs {
 #defineDCSR_DCFG_ECC_DISABLE_USB2  0x4000
u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+   u32 dpslpcr;/* 0x000 Deep Sleep Control register */
+   u32 usb1dpslpcsr;   /* 0x004 USB1 Deep Sleep Control Status 
register */
+   u32 usb2dpslpcsr;   /* 0x008 USB2 Deep Sleep Control Status 
register */
+   u32 fmclkdpslpcr;   /* 0x00c FM Clock Deep Sleep Control register */
+   u32 res1[4];
+   u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control 
register */
+   u32 res2;
+   u32 pixclkcr;   /* 0x028 Pixel Clock Control register */
+   u32 res3[245];
+   u32 qeioclkcr;  /* 0x400 QUICC Engine IO Clock Control register 
*/
+   u32 emiiocr;/* 0x404 EMI MDIO Control Register */
+   u32 sdhciovselcr;   /* 0x408 SDHC IO VSEL Control register */
+   u32 qmifrstcr;  /* 0x40c QMAN Interface Reset Control register 
*/
+   u32 res4[60];
+   u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
+};
 #endif /*__IMMAP_85xx__*/
-- 
1.8.5


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[U-Boot] [PATCH 2/2 v2] mpc85xx/t104x: Add deep sleep framework support

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2: 
- added explaination for CONFIG_DEEP_SLEEP
- fixed some issues

 README |  4 +++
 arch/powerpc/cpu/mpc85xx/asm-offsets.c | 24 ++
 arch/powerpc/cpu/mpc85xx/cpu_init.c|  7 +
 arch/powerpc/cpu/mpc85xx/fdt.c | 25 +++
 arch/powerpc/cpu/mpc85xx/liodn.c   | 27 +++-
 arch/powerpc/cpu/mpc85xx/start.S   | 12 +++
 arch/powerpc/include/asm/global_data.h |  2 ++
 arch/powerpc/lib/board.c   | 57 +++---
 drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 42 ++---
 include/fsl_ddr_sdram.h|  6 
 10 files changed, 190 insertions(+), 16 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/asm-offsets.c

diff --git a/README b/README
index ff49260..0fa646e 100644
--- a/README
+++ b/README
@@ -427,6 +427,10 @@ The following options need to be configured:
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
 
+   CONFIG_DEEP_SLEEP
+   Inidcates this SoC supports deep sleep feature. If deep sleep is
+   supported, core will start to execute uboot when wakes up.
+
 - Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
diff --git a/arch/powerpc/cpu/mpc85xx/asm-offsets.c 
b/arch/powerpc/cpu/mpc85xx/asm-offsets.c
new file mode 100644
index 000..1e422e7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/asm-offsets.c
@@ -0,0 +1,24 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+
+#include linux/kbuild.h
+
+int main(void)
+{
+   DEFINE(GD_FLAGS_OFF, offsetof(struct global_data, flags));
+
+   return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..80ffe5c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -231,6 +231,7 @@ void cpu_init_f (void)
 #ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
+   gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
/*
 * CPU2 errata workaround: A core hang possible while executing
@@ -282,6 +283,12 @@ void cpu_init_f (void)
in_be32(gur-dcsrcr);
 #endif
 
+#ifdef CONFIG_DEEP_SLEEP
+   /* disable the console if boot from deep sleep */
+   if (in_be32(gur-scrtsr[0])  (1  3))
+   gd-flags |= GD_FLG_SILENT |
+   GD_FLG_DEEP_SLEEP | GD_FLG_DISABLE_CONSOLE;
+#endif
 }
 
 /* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 33bc900..4404b0b 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 extern void ft_qe_setup(void *blob);
 extern void ft_fixup_num_cores(void *blob);
 extern void ft_srio_setup(void *blob);
+extern ulong __bss_end;
 
 #ifdef CONFIG_MP
 #include mp.h
@@ -35,6 +36,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#ifdef CONFIG_DEEP_SLEEP
+   ulong len;
+#endif
 
off = fdt_node_offset_by_prop_value(blob, -1, device_type, cpu, 4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +81,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
device_type, cpu, 4);
}
 
+#ifdef CONFIG_DEEP_SLEEP
+   /*
+* reserve the memory space for deep sleep.
+* This space will be re-used next time when boot from deep sleep.
+* The space includes bd_t, gd_t, stack and uboot image.
+* Reserve 1K for stack.
+*/
+   len = sizeof(bd_t) + sizeof(gd_t) + (1  10);
+   /* round up to 4K */
+   len = (len + (4096 - 1))  ~(4096 - 1);
+
+   off = fdt_add_mem_rsv(blob, gd-relocaddr - len,
+   len + ((ulong)__bss_end - gd-relocaddr));
+   if (off  0)
+   printf(Failed to reserve memory for deep sleep: %s\n,
+  

[U-Boot] [PATCH v2] mpc85xx: Fix the offset of register address error

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
P5020, P5040, T4240, B4860.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- updated the commit message.

 arch/powerpc/include/asm/mpc85xx_gpio.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h 
b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 3d11884..87bb4a0 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
 static inline void mpc85xx_gpio_set(unsigned int mask,
unsigned int dir, unsigned int val)
 {
-   ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+   ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 
/* First mask off the unwanted parts of dir and val */
dir = mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
 
 static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
 {
-   ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+   ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 
/* Read the requested values */
return in_be32(gpio-gpdat)  mask;
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/mpc85xx: Fix the I2C bus speed error on p1022

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus speed setting. so, fixed it.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
fix bug: ENGR00274019

 arch/powerpc/cpu/mpc85xx/speed.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 65cc7c0..75c92cc 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -415,7 +415,8 @@ int get_clocks (void)
 * AN2919.
 */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
-   defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
+   defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
+   defined(CONFIG_P1022)
gd-arch.i2c1_clk = sys_info.freq_systembus;
 #elif defined(CONFIG_MPC8544)
/*
-- 
1.8.0


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[U-Boot] [PATCH v3] powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen node

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

For T4/B4, the clockgen node compatible string is updated to version 2.0.
Add clock-frequency setting for this new version.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v3:
- update the compatible string from *-2 to *-2.0
v2:
- fix the codestyle

 arch/powerpc/cpu/mpc85xx/fdt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 24eb978..b1aafac 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -663,6 +663,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, fsl,qoriq-clockgen-1.0,
clock-frequency, CONFIG_SYS_CLK_FREQ, 1);
+   do_fixup_by_compat_u32(blob, fsl,qoriq-clockgen-2.0,
+   clock-frequency, CONFIG_SYS_CLK_FREQ, 1);
 #endif
 
fdt_fixup_memory(blob, (u64)bd-bi_memstart, (u64)bd-bi_memsize);
-- 
1.8.0


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[U-Boot] [PATCH] powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen node

[Yuantian.Tang]

From: Tang Yuantian yuantian.t...@freescale.com

For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.

Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
 arch/powerpc/cpu/mpc85xx/fdt.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 24eb978..cda6ad6 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -663,6 +663,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, fsl,qoriq-clockgen-1.0,
clock-frequency, CONFIG_SYS_CLK_FREQ, 1);
+   do_fixup_by_compat_u32(blob, fsl,qoriq-clockgen-2,
+   clock-frequency, CONFIG_SYS_CLK_FREQ, 1);
 #endif
 
fdt_fixup_memory(blob, (u64)bd-bi_memstart, (u64)bd-bi_memsize);
-- 
1.6.4


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