[U-Boot] [PATCH 32/33] dts: rk3399: change the maximum eMMC clock frequency to 150MHz

[Ziyuan Xu]

The rockchip mmc controllers don't support _the _odd__ divider,
otherwise probably cause unpredictable error.

The driver originally select gpll(594M) as the clock source, and we set
div to 3 at 200MHz. We have to change the maximum eMMC clock frequency
to 150MHz in U-Boot stage, so that the div will be 4.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 arch/arm/dts/rk3399.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index f3d3f53..b2122b6 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -283,7 +283,7 @@
arasan,soc-ctl-syscon = <>;
assigned-clocks = < SCLK_EMMC>;
assigned-clock-rates = <2>;
-   max-frequency = <2>;
+   max-frequency = <15000>;
clocks = < SCLK_EMMC>, < ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "emmc_cardclock";
-- 
2.7.4


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[U-Boot] [PATCH 19/33] mmc: dw_mmc: rockchip: implement tuning with clock phase framework

[Ziyuan Xu]

This algorithm will try 1 degree increment, since there's no way to tell
what resolution the underlying phase code uses. As an added bonus, doing
many tunings yields better results since some tests are run more than
once (ex: if the underlying driver use 45 degree increments, the tuning
code will try the same angle more than once).

It will then construct a list of good phase ranges (even range that
cross 270/0), will pick the biggest range then it will set the
sample_clk to the middle of that range.

Please notice that it tuning only 0-270 degree in U-Boot, but kernel
tuning range is 0-360 degree. Below are two reasons about this:
1. Expect data-related interrupt may miss during 270-360 degree on
rockchip platform, dw_mmc driver will poll for data interrupt until
240 seconds timeout afterwards. And the host controller will be left in
an unpredictable state.
2. The phase of a clock signal is shift by some delay elements on
rockchip platform. And the delay element affected by logic voltage and
temperature in runtime. These factors wouldn't have changed a lot in
U-Boot stage.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/rockchip_dw_mmc.c | 121 ++
 1 file changed, 121 insertions(+)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 2885ef2..474ca1c 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -30,6 +30,7 @@ struct rockchip_mmc_plat {
 
 struct rockchip_dwmmc_priv {
struct clk clk;
+   struct clk sample_clk;
struct dwmci_host host;
int fifo_depth;
bool fifo_mode;
@@ -99,6 +100,123 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct 
udevice *dev)
return 0;
 }
 
+#define NUM_PHASES 270
+#define TUNING_ITERATION_TO_PHASE(i)   (DIV_ROUND_UP((i) * 270, NUM_PHASES))
+
+static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode)
+{
+   int ret = 0;
+   int i;
+   bool v, prev_v = 0, first_v;
+   struct range_t {
+   int start;
+   int end; /* inclusive */
+   };
+   struct range_t *ranges;
+   unsigned int range_count = 0;
+   int longest_range_len = -1;
+   int longest_range = -1;
+   int middle_phase;
+   struct udevice *dev = host->priv;
+   struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
+   struct mmc *mmc = host->mmc;
+
+   if (IS_ERR(>sample_clk))
+   return -EIO;
+
+   ranges = calloc(sizeof(*ranges), NUM_PHASES / 2 + 1);
+   if (!ranges)
+   return -ENOMEM;
+
+   /* Try each phase and extract good ranges */
+   for (i = 0; i < NUM_PHASES; ) {
+   clk_set_phase(>sample_clk, TUNING_ITERATION_TO_PHASE(i));
+
+   v = !mmc_send_tuning(mmc, opcode);
+
+   if (i == 0)
+   first_v = v;
+
+   if ((!prev_v) && v) {
+   range_count++;
+   ranges[range_count - 1].start = i;
+   }
+   if (v) {
+   ranges[range_count - 1].end = i;
+   i++;
+   } else if (i == NUM_PHASES - 1) {
+   /* No extra skipping rules if we're at the end */
+   i++;
+   } else {
+   /*
+* No need to check too close to an invalid
+* one since testing bad phases is slow.  Skip
+* 20 degrees.
+*/
+   i += DIV_ROUND_UP(20 * NUM_PHASES, NUM_PHASES);
+
+   /* Always test the last one */
+   if (i >= NUM_PHASES)
+   i = NUM_PHASES - 1;
+   }
+
+   prev_v = v;
+   }
+
+   if (range_count == 0) {
+   debug("All phases bad!");
+   ret = -EIO;
+   goto free;
+   }
+
+   /* wrap around case, merge the end points */
+   if ((range_count > 1) && first_v && v) {
+   ranges[0].start = ranges[range_count - 1].start;
+   range_count--;
+   }
+
+   if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) {
+   clk_set_phase(>sample_clk,
+ TUNING_ITERATION_TO_PHASE(NUM_PHASES / 2));
+   debug("All phases work, using middle phase.\n");
+   goto free;
+   }
+
+   /* Find the longest range */
+   for (i = 0; i < range_count; i++) {
+   int len = (ranges[i].end - ranges[i].start + 1);
+
+   if (len < 0)
+   len += NUM_PHASES;
+
+   if (longest_range_len < len) {
+   longest_range_len = len;
+   long

[U-Boot] [PATCH 25/33] mmc: sdhci: update host->clock after clock setting

[Ziyuan Xu]

Overwrite host->clock after clock setting to avoid repetitive reset
clock.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/sdhci.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 48bac04..ad86278 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -390,6 +390,9 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
 
clk |= SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+   host->clock = clock;
+
return 0;
 }
 
-- 
2.7.4


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[U-Boot] [PATCH 24/33] mmc: sdhci: rockchip: fix bus width setting

[Ziyuan Xu]

Rockchip sdhci controller capable of 8-bit transfer. The original can
only run at 4 bit mode.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/rockchip_sdhci.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index bdde831..562fb35 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -47,11 +47,26 @@ static int arasan_sdhci_probe(struct udevice *dev)
 
host->name = dev->name;
host->ioaddr = map_sysmem(dtplat->reg[1], dtplat->reg[3]);
+   host->host_caps |= MMC_MODE_8BIT;
max_frequency = dtplat->max_frequency;
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, );
 #else
max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"max-frequency", 0);
+   switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+  "bus-width", 4)) {
+   case 8:
+   host->host_caps |= MMC_MODE_8BIT;
+   break;
+   case 4:
+   host->host_caps |= MMC_MODE_4BIT;
+   break;
+   case 1:
+   break;
+   default:
+   printf("Invalid \"bus-width\" value\n");
+   return -EINVAL;
+   }
ret = clk_get_by_index(dev, 0, );
 #endif
if (!ret) {
-- 
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[U-Boot] [PATCH 22/33] mmc: dw_mmc: rockchip: fix data crc error on ddr52 8bit mode

[Ziyuan Xu]

The clk_divider must be set to 1 on ddr52 8bit mode for rockchip
platform. Otherwise we will get a data crc error during data
transmission.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c  | 2 +-
 drivers/mmc/rockchip_dw_mmc.c | 7 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index e862eb2..dcd7fba 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -344,7 +344,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 
freq)
int timeout = 1;
unsigned long sclk;
 
-   if ((freq == host->clock) || (freq == 0))
+   if (freq == 0)
return 0;
/*
 * If host->get_mmc_clk isn't defined,
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 474ca1c..b2b7f5a 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -43,6 +43,13 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host 
*host, uint freq)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
int ret;
 
+   /*
+* If DDR52 8bit mode(only emmc work in 8bit mode),
+* divider must be set 1
+*/
+   if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8)
+   freq *= 2;
+
ret = clk_set_rate(>clk, freq);
if (ret < 0) {
printf("%s: err=%d\n", __func__, ret);
-- 
2.7.4


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[U-Boot] [PATCH 23/33] mmc: dw_mmc: fix bus width setting

[Ziyuan Xu]

Hosts capable of 8-bit transfers can also do 4 bits.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index dcd7fba..3b89e7a 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -559,8 +559,7 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct 
dwmci_host *host,
cfg->host_caps = host->caps;
 
if (host->buswidth == 8) {
-   cfg->host_caps |= MMC_MODE_8BIT;
-   cfg->host_caps &= ~MMC_MODE_4BIT;
+   cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT;
} else {
cfg->host_caps |= MMC_MODE_4BIT;
cfg->host_caps &= ~MMC_MODE_8BIT;
-- 
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[U-Boot] [PATCH 06/33] mmc: add card_busy to query card status

[Ziyuan Xu]

Card devices get into busy status since host request speed mode
switch, if host controller is able to query whether the device is busy,
try it instead of sending cmd13.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc-uclass.c | 16 
 drivers/mmc/mmc.c| 13 +
 include/mmc.h| 11 +++
 3 files changed, 40 insertions(+)

diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 9c07871..a300a6d 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -38,6 +38,22 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 
struct mmc_data *data)
return dm_mmc_send_cmd(mmc->dev, cmd, data);
 }
 
+bool mmc_card_busy(struct mmc *mmc)
+{
+   struct dm_mmc_ops *ops = mmc_get_ops(mmc->dev);
+
+   if (!ops->card_busy)
+   return -ENOSYS;
+   return ops->card_busy(mmc->dev);
+}
+
+bool mmc_can_card_busy(struct mmc *mmc)
+{
+   struct dm_mmc_ops *ops = mmc_get_ops(mmc->dev);
+
+   return !!ops->card_busy;
+}
+
 int dm_mmc_set_ios(struct udevice *dev)
 {
struct dm_mmc_ops *ops = mmc_get_ops(dev);
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 0b30172..13d8f04 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1156,6 +1156,19 @@ static void mmc_set_ios(struct mmc *mmc)
if (mmc->cfg->ops->set_ios)
mmc->cfg->ops->set_ios(mmc);
 }
+
+static bool mmc_card_busy(struct mmc *mmc)
+{
+   if (!mmc->cfg->ops->card_busy)
+   return -ENOSYS;
+
+   return mmc->cfg->ops->card_busy(mmc);
+}
+
+static bool mmc_can_card_busy(struct mmc *)
+{
+   return !!mmc->cfg->ops->card_busy;
+}
 #endif
 
 void mmc_set_clock(struct mmc *mmc, uint clock)
diff --git a/include/mmc.h b/include/mmc.h
index 060c1f8..9bed935 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -357,6 +357,14 @@ struct dm_mmc_ops {
struct mmc_data *data);
 
/**
+* card_busy() - Query the card device status
+*
+* @dev:Device to update
+* @return true if card device is busy
+*/
+   bool (*card_busy)(struct udevice *dev);
+
+   /**
 * set_ios() - Set the I/O speed/width for an MMC device
 *
 * @dev:Device to update
@@ -390,12 +398,15 @@ int dm_mmc_get_cd(struct udevice *dev);
 int dm_mmc_get_wp(struct udevice *dev);
 
 /* Transition functions for compatibility */
+bool mmc_card_busy(struct mmc *mmc);
+bool mmc_can_card_busy(struct mmc *mmc);
 int mmc_set_ios(struct mmc *mmc);
 int mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
 
 #else
 struct mmc_ops {
+   bool (*card_busy)(struct mmc *mmc);
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
int (*set_ios)(struct mmc *mmc);
-- 
2.7.4


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[U-Boot] [PATCH 33/33] SPL: tiny-printf: add "X" modifier

[Ziyuan Xu]

tiny-printf does not know about the "X" modifier so far, which print
all zero. The mmc driver use '0x%08X' to print command argument and
response.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 lib/tiny-printf.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 0b04813..f1183d5 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -273,6 +273,7 @@ static int _vprintf(struct printf_info *info, const char 
*fmt, va_list va)
}
break;
case 'x':
+   case 'X':
if (islong) {
num = va_arg(va, unsigned long);
div = 1UL << (sizeof(long) * 8 - 4);
-- 
2.7.4


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[U-Boot] [PATCH 01/33] mmc: select the available type from host_caps and card_caps

[Ziyuan Xu]

The original implementation select HS timing by default, add available
type selection for higher speed mode compatibility, such as hs200,
hs400, hs400es.

By the way, we assume that card run at 1.8V or 1.2V I/O when its timing
is ddr52/hs200/hs400(es).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 59 ++-
 include/mmc.h | 16 +++
 2 files changed, 74 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 72fc177..f5b2280 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -546,10 +546,62 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 
value)
 
 }
 
+static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
+{
+   u8 card_type;
+   u32 host_caps, avail_type = 0;
+
+   card_type = ext_csd[EXT_CSD_CARD_TYPE];
+   host_caps = mmc->cfg->host_caps;
+
+   if ((host_caps & MMC_MODE_HS) &&
+   (card_type & EXT_CSD_CARD_TYPE_26))
+   avail_type |= EXT_CSD_CARD_TYPE_26;
+
+   if ((host_caps & MMC_MODE_HS) &&
+   (card_type & EXT_CSD_CARD_TYPE_52))
+   avail_type |= EXT_CSD_CARD_TYPE_52;
+
+   /*
+* For the moment, u-boot doesn't support signal voltage
+* switch, therefor we assume that host support ddr52
+* at 1.8v or 3.3v I/O(1.2v I/O not supported, hs200 and
+* hs400 are the same).
+*/
+   if ((host_caps & MMC_MODE_DDR_52MHz) &&
+   (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V;
+
+   if ((host_caps & MMC_MODE_HS200) &&
+   (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V;
+
+   /*
+* If host can support HS400, it means that host can also
+* support HS200.
+*/
+   if ((host_caps & MMC_MODE_HS400) &&
+   (host_caps & MMC_MODE_8BIT) &&
+   (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V |
+   EXT_CSD_CARD_TYPE_HS400_1_8V;
+
+   if ((host_caps & MMC_MODE_HS400ES) &&
+   (host_caps & MMC_MODE_8BIT) &&
+   ext_csd[EXT_CSD_STROBE_SUPPORT] &&
+   (avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V |
+   EXT_CSD_CARD_TYPE_HS400_1_8V |
+   EXT_CSD_CARD_TYPE_HS400ES;
+
+   return avail_type;
+}
+
 static int mmc_change_freq(struct mmc *mmc)
 {
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
char cardtype;
+   u32 avail_type;
int err;
 
mmc->card_caps = 0;
@@ -569,8 +621,13 @@ static int mmc_change_freq(struct mmc *mmc)
return err;
 
cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
+   avail_type = mmc_select_card_type(mmc, ext_csd);
 
-   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+   if (avail_type & EXT_CSD_CARD_TYPE_HS)
+   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING, 1);
+   else
+   err = -EINVAL;
 
if (err)
return err;
diff --git a/include/mmc.h b/include/mmc.h
index fad12d6..0bae1a1 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -58,6 +58,9 @@
 #define MMC_MODE_8BIT  (1 << 3)
 #define MMC_MODE_SPI   (1 << 4)
 #define MMC_MODE_DDR_52MHz (1 << 5)
+#define MMC_MODE_HS200 (1 << 6)
+#define MMC_MODE_HS400 (1 << 7)
+#define MMC_MODE_HS400ES   (1 << 8)
 
 #define SD_DATA_4BIT   0x0004
 
@@ -182,6 +185,7 @@
 #define EXT_CSD_BOOT_BUS_WIDTH 177
 #define EXT_CSD_PART_CONF  179 /* R/W */
 #define EXT_CSD_BUS_WIDTH  183 /* R/W */
+#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
 #define EXT_CSD_HS_TIMING  185 /* R/W */
 #define EXT_CSD_REV192 /* RO */
 #define EXT_CSD_CARD_TYPE  196 /* RO */
@@ -201,6 +205,18 @@
 
 #define EXT_CSD_CARD_TYPE_26   (1 << 0)/* Card can run at 26MHz */
 #define EXT_CSD_CARD_TYPE_52   (1 << 1)/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_HS   (EXT_CSD_CARD_TYPE_26 | \
+EXT_CSD_CARD_TYPE_52)
+#define EXT_CSD_CARD_TYPE_HS200_1_8V   BIT(4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_HS200_1_2V   BIT(5)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_HS200(EXT_CSD_CARD_TYPE_HS200_1_8V | 
\
+EXT_CSD_CARD_TYPE_HS200_1_2V)
+#define EXT_CSD_CARD_TYPE_HS400_1_8V   BIT(6)  /* Car

[U-Boot] [PATCH 26/33] mmc: sdhci: add support for UHS timing

[Ziyuan Xu]

To support UHS speed mode, controller should enable 1.8V signaling and
select one of UHS modes.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/sdhci.c | 40 
 include/mmc.h   |  1 +
 include/sdhci.h | 17 +
 3 files changed, 58 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index ad86278..8f4a2a1 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -426,6 +426,39 @@ static void sdhci_set_power(struct sdhci_host *host, 
unsigned short power)
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 }
 
+static void sdhci_set_uhs_signaling(struct sdhci_host *host)
+{
+   u16 ctrl_2;
+   u32 timing = host->mmc->timing;
+
+   ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+   /* Select Bus Speed Mode for host */
+   ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+
+   if ((timing != MMC_TIMING_LEGACY) &&
+   (timing != MMC_TIMING_MMC_HS) &&
+   (timing != MMC_TIMING_SD_HS))
+   ctrl_2 |= SDHCI_CTRL_VDD_180;
+
+   if ((timing == MMC_TIMING_MMC_HS200) ||
+   (timing == MMC_TIMING_UHS_SDR104))
+   ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A;
+   else if (timing == MMC_TIMING_UHS_SDR12)
+   ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+   else if (timing == MMC_TIMING_UHS_SDR25)
+   ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+   else if (timing == MMC_TIMING_UHS_SDR50)
+   ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+   else if ((timing == MMC_TIMING_UHS_DDR50) ||
+(timing == MMC_TIMING_MMC_DDR52))
+   ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+   else if (timing == MMC_TIMING_MMC_HS400 ||
+timing == MMC_TIMING_MMC_HS400ES)
+   ctrl_2 |= SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A;
+
+   sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
+
 #ifdef CONFIG_DM_MMC_OPS
 static bool sdhci_card_busy(struct udevice *dev)
 {
@@ -485,6 +518,13 @@ static int sdhci_set_ios(struct mmc *mmc)
 
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 
+   if ((mmc->timing != MMC_TIMING_LEGACY) &&
+   (mmc->timing != MMC_TIMING_MMC_HS) &&
+   (mmc->timing != MMC_TIMING_SD_HS))
+   sdhci_set_power(host, MMC_VDD_165_195_SHIFT);
+
+   sdhci_set_uhs_signaling(host);
+
/* If available, call the driver specific "post" set_ios() function */
if (host->ops && host->ops->set_ios_post)
host->ops->set_ios_post(host);
diff --git a/include/mmc.h b/include/mmc.h
index 05bf39d..b5817f3 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -138,6 +138,7 @@
 
 #define MMC_STATE_PRG  (7 << 9)
 
+#define MMC_VDD_165_195_SHIFT  7
 #define MMC_VDD_165_1950x0080  /* VDD voltage 1.65 - 
1.95 */
 #define MMC_VDD_20_21  0x0100  /* VDD voltage 2.0 ~ 2.1 */
 #define MMC_VDD_21_22  0x0200  /* VDD voltage 2.1 ~ 2.2 */
diff --git a/include/sdhci.h b/include/sdhci.h
index 75432db..449ada1 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -147,6 +147,23 @@
 #define SDHCI_ACMD12_ERR   0x3C
 
 /* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL20x3E
+#define SDHCI_CTRL_UHS_MASK0x0007
+#define SDHCI_CTRL_UHS_SDR12   0x
+#define SDHCI_CTRL_UHS_SDR25   0x0001
+#define SDHCI_CTRL_UHS_SDR50   0x0002
+#define SDHCI_CTRL_UHS_SDR104  0x0003
+#define SDHCI_CTRL_UHS_DDR50   0x0004
+#define SDHCI_CTRL_HS400   0x0005
+#define SDHCI_CTRL_VDD_180 0x0008
+#define SDHCI_CTRL_DRV_TYPE_MASK   0x0030
+#define SDHCI_CTRL_DRV_TYPE_B  0x
+#define SDHCI_CTRL_DRV_TYPE_A  0x0010
+#define SDHCI_CTRL_DRV_TYPE_C  0x0020
+#define SDHCI_CTRL_DRV_TYPE_D  0x0030
+#define SDHCI_CTRL_EXEC_TUNING 0x0040
+#define SDHCI_CTRL_TUNED_CLK   0x0080
+#define SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
 
 #define SDHCI_CAPABILITIES 0x40
 #define  SDHCI_TIMEOUT_CLK_MASK0x003F
-- 
2.7.4


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[U-Boot] [PATCH 10/33] mmc: add support for HS200 mode of eMMC4.5

[Ziyuan Xu]

Add the support of the HS200 mode for eMMC 4.5 devices. The eMMC 4.5
device has support up to 200MHz bus speed, it can speed up the boot speed.

We can enable this feature via MMC_MODE_HS200 if the host controller has
the ability to support HS200 timing. Also the tuning feature required
when the HS200 mode is selected.

By the way, mmc card can only switch to high speed mode in SPL stage.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 395 --
 include/mmc.h |  27 
 2 files changed, 289 insertions(+), 133 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 9aee6ff..bebf8f3 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -318,6 +318,26 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t 
start, lbaint_t blkcnt,
return blkcnt;
 }
 
+void mmc_set_clock(struct mmc *mmc, uint clock)
+{
+   if (clock > mmc->cfg->f_max)
+   clock = mmc->cfg->f_max;
+
+   if (clock < mmc->cfg->f_min)
+   clock = mmc->cfg->f_min;
+
+   mmc->clock = clock;
+
+   mmc_set_ios(mmc);
+}
+
+static void mmc_set_bus_width(struct mmc *mmc, uint width)
+{
+   mmc->bus_width = width;
+
+   mmc_set_ios(mmc);
+}
+
 static void mmc_set_timing(struct mmc *mmc, uint timing)
 {
mmc->timing = timing;
@@ -587,6 +607,181 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 
value)
return __mmc_switch(mmc, set, index, value, true);
 }
 
+static int mmc_select_bus_width(struct mmc *mmc)
+{
+   u32 ext_csd_bits[] = {
+   EXT_CSD_BUS_WIDTH_8,
+   EXT_CSD_BUS_WIDTH_4,
+   };
+   u32 bus_widths[] = {
+   MMC_BUS_WIDTH_8BIT,
+   MMC_BUS_WIDTH_4BIT,
+   };
+   ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+   ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
+   u32 idx, bus_width = 0;
+   int err = 0;
+
+   if (mmc->version < MMC_VERSION_4 ||
+   !(mmc->cfg->host_caps & (MMC_MODE_4BIT | MMC_MODE_8BIT)))
+   return 0;
+
+   err = mmc_send_ext_csd(mmc, ext_csd);
+
+   if (err)
+   return err;
+
+   idx = (mmc->cfg->host_caps & MMC_MODE_8BIT) ? 0 : 1;
+
+   /*
+* Unlike SD, MMC cards dont have a configuration register to notify
+* supported bus width. So bus test command should be run to identify
+* the supported bus width or compare the ext csd values of current
+* bus width and ext csd values of 1 bit mode read earlier.
+*/
+   for (; idx < ARRAY_SIZE(bus_widths); idx++) {
+   /*
+* Host is capable of 8bit transfer, then switch
+* the device to work in 8bit transfer mode. If the
+* mmc switch command returns error then switch to
+* 4bit transfer mode. On success set the corresponding
+* bus width on the host.
+*/
+   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_BUS_WIDTH, ext_csd_bits[idx]);
+   if (err)
+   continue;
+
+   bus_width = bus_widths[idx];
+   mmc_set_bus_width(mmc, bus_width);
+
+   err = mmc_send_ext_csd(mmc, test_csd);
+
+   if (err)
+   continue;
+
+   /* Only compare read only fields */
+   if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] ==
+   test_csd[EXT_CSD_PARTITIONING_SUPPORT]) &&
+   (ext_csd[EXT_CSD_HC_WP_GRP_SIZE] ==
+   test_csd[EXT_CSD_HC_WP_GRP_SIZE]) &&
+   (ext_csd[EXT_CSD_REV] == test_csd[EXT_CSD_REV]) &&
+   (ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] ==
+   test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) &&
+   !memcmp(_csd[EXT_CSD_SEC_CNT],
+   _csd[EXT_CSD_SEC_CNT], 4)) {
+   err = bus_width;
+   break;
+   } else {
+   err = -EBADMSG;
+   }
+   }
+
+   return err;
+}
+
+static const u8 tuning_blk_pattern_4bit[] = {
+   0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
+   0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
+   0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
+   0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
+   0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
+   0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
+   0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
+   0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
+};
+
+static const u8 tuning_blk_pattern_8bit[] = {
+   0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
+   0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
+   0xcc, 0x33, 0x33

[U-Boot] [PATCH 11/33] mmc: rework ddr mode judgement with timing

[Ziyuan Xu]

Since the card device is set the proper timing after speed mode switch
is completed, host driver can get ddr_mode from timing parameter. So
drop the antiquated ddr_mode.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 cmd/mmc.c | 2 +-
 drivers/mmc/dw_mmc.c  | 2 +-
 drivers/mmc/fsl_esdhc.c   | 4 ++--
 drivers/mmc/mmc.c | 3 +--
 drivers/mmc/uniphier-sd.c | 4 ++--
 drivers/mmc/xenon_sdhci.c | 6 +++---
 include/mmc.h | 1 -
 7 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/cmd/mmc.c b/cmd/mmc.c
index f83032e..ef05fa5 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -38,7 +38,7 @@ static void print_mmcinfo(struct mmc *mmc)
print_size(mmc->capacity, "\n");
 
printf("Bus Width: %d-bit%s\n", mmc->bus_width,
-   mmc->ddr_mode ? " DDR" : "");
+   mmc_card_ddr(mmc) ? " DDR" : "");
 
puts("Erase Group Size: ");
print_size(((u64)mmc->erase_grp_size) << 9, "\n");
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index baf2280..7e9ffc2 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -432,7 +432,7 @@ static int dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_CTYPE, ctype);
 
regs = dwmci_readl(host, DWMCI_UHS_REG);
-   if (mmc->ddr_mode)
+   if (mmc_card_ddr(mmc))
regs |= DWMCI_DDR_MODE;
else
regs &= ~DWMCI_DDR_MODE;
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index f3c6358..5a6942e 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -400,7 +400,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
 #if defined(CONFIG_FSL_USDHC)
esdhc_write32(>mixctrl,
(esdhc_read32(>mixctrl) & 0xFF80) | (xfertyp & 0x7F)
-   | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
+   | (mmc_card_ddr(mmc) ? XFERTYP_DDREN : 0));
esdhc_write32(>xfertyp, xfertyp & 0x);
 #else
esdhc_write32(>xfertyp, xfertyp);
@@ -541,7 +541,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
if ((sdhc_clk / (div * pre_div)) <= clock)
break;
 
-   pre_div >>= mmc->ddr_mode ? 2 : 1;
+   pre_div >>= mmc_card_ddr(mmc) ? 2 : 1;
div -= 1;
 
clk = (pre_div << 8) | (div << 4);
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index bebf8f3..d47cfe6 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -210,7 +210,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
 {
struct mmc_cmd cmd;
 
-   if (mmc->ddr_mode)
+   if (mmc_card_ddr(mmc))
return 0;
 
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
@@ -1926,7 +1926,6 @@ int mmc_start_init(struct mmc *mmc)
if (err)
return err;
 #endif
-   mmc->ddr_mode = 0;
mmc_set_bus_width(mmc, 1);
mmc_set_clock(mmc, 1);
mmc_set_timing(mmc, MMC_TIMING_LEGACY);
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 7f20ef1..ac7359b 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -532,7 +532,7 @@ static void uniphier_sd_set_ddr_mode(struct 
uniphier_sd_priv *priv,
u32 tmp;
 
tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
-   if (mmc->ddr_mode)
+   if (mmc_card_ddr(mmc))
tmp |= UNIPHIER_SD_IF_MODE_DDR;
else
tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
@@ -599,7 +599,7 @@ static int uniphier_sd_set_ios(struct udevice *dev)
int ret;
 
dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
-   mmc->clock, mmc->ddr_mode, mmc->bus_width);
+   mmc->clock, mmc_card_ddr(mmc), mmc->bus_width);
 
ret = uniphier_sd_set_bus_width(priv, mmc);
if (ret)
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index f0a33c1..7685e15 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -237,7 +237,7 @@ static void xenon_mmc_phy_set(struct sdhci_host *host)
sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
 
var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
-   if (host->mmc->ddr_mode) {
+   if (mmc_card_ddr(host->mmc)) {
var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
} else {
var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
@@ -329,7 +329,7 @@ static void xenon_sdhci_set_ios_post(struct sdhci_host 
*host)
if (IS_SD(host->mmc)) {
/* SD/SDIO */
if (pwr_18v) {
-   if (host->mmc->ddr_mode)
+   if (mmc_card_ddr(host->mmc))
priv->timing = MMC_TIMIN

[U-Boot] [PATCH 15/33] rockchip: clk: rk3288: fix mmc clock setting

[Ziyuan Xu]

Mmc clock automatically divide 2 in internal.

Before this:
gpll = 594MHz, clock = 148.5MHz
div = 594/148.5-1 = 3
output clock is 99MHz

After this:
gpll = 594MHz, clock = 148.5MHz
div = 297+148.5-1/148.5 = 2
output clock is 148.5Mhz

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3288.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3288.c 
b/drivers/clk/rockchip/clk_rk3288.c
index fc369dd..b924a3b 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -535,7 +535,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, 
uint gclk_rate,
}
 
src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
-   return DIV_TO_RATE(src_rate, div);
+   return DIV_TO_RATE(src_rate, div) / 2;
 }
 
 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
@@ -545,10 +545,10 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, 
uint gclk_rate,
int mux;
 
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
-   src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+   src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
 
if (src_clk_div > 0x3f) {
-   src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
+   src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
mux = EMMC_PLL_SELECT_24MHZ;
assert((int)EMMC_PLL_SELECT_24MHZ ==
   (int)MMC0_PLL_SELECT_24MHZ);
-- 
2.7.4


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[U-Boot] [PATCH 31/33] mmc: add support for HS400 mode of eMMC5.0

[Ziyuan Xu]

This patch adds HS400 mode support for eMMC5.0 device. HS400 mode is
high speed DDR interface timing from HS200. Clock frequency is up to
200MHz and only 8-bit bus width is supported. In addition, tuning
process of HS200 is required to synchronize the command response on the
CMD line because CMD input timing for HS400 mode is the same as HS200
mode.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 48 ++--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c1f54c3..71c9cfa 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -855,6 +855,45 @@ static int mmc_select_hs200(struct mmc *mmc)
 }
 #endif
 
+static int mmc_select_hs400(struct mmc *mmc)
+{
+   int ret;
+
+   /* Switch card to HS mode */
+   ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+  EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, false);
+   if (ret)
+   return ret;
+
+   /* Set host controller to HS timing */
+   mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
+
+   /* Reduce frequency to HS frequency */
+   mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
+
+   ret = mmc_send_status(mmc, 1000);
+   if (ret)
+   return ret;
+
+   /* Switch card to DDR */
+   ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_BUS_WIDTH,
+EXT_CSD_DDR_BUS_WIDTH_8);
+   if (ret)
+   return ret;
+
+   /* Switch card to HS400 */
+   ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+  EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400, false);
+   if (ret)
+   return ret;
+
+   /* Set host controller to HS400 timing and frequency */
+   mmc_set_timing(mmc, MMC_TIMING_MMC_HS400);
+
+   return ret;
+}
+
 static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
 {
u8 card_type;
@@ -960,9 +999,14 @@ static int mmc_change_freq(struct mmc *mmc)
 
mmc_set_bus_speed(mmc, avail_type);
 
-   if (mmc_card_hs200(mmc))
+   if (mmc_card_hs200(mmc)) {
err = mmc_hs200_tuning(mmc);
-   else if (!mmc_card_hs400es(mmc)) {
+   if (avail_type & EXT_CSD_CARD_TYPE_HS400 &&
+   mmc->bus_width == MMC_BUS_WIDTH_8BIT) {
+   err = mmc_select_hs400(mmc);
+   mmc_set_bus_speed(mmc, avail_type);
+   }
+   } else if (!mmc_card_hs400es(mmc)) {
err = mmc_select_bus_width(mmc) > 0 ? 0 : err;
if (!err && avail_type & EXT_CSD_CARD_TYPE_DDR_52)
err = mmc_select_hs_ddr(mmc);
-- 
2.7.4


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[U-Boot] [PATCH 29/33] mmc: sdhci: rockchip: add phy support

[Ziyuan Xu]

This patch gets phy phandle from dt-binding, and power
cycle/re-configure phy whilst changing card clock.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/rockchip_sdhci.c | 147 +++
 1 file changed, 147 insertions(+)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 562fb35..5b6b262 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -6,6 +6,7 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -28,11 +29,151 @@ struct rockchip_sdhc_plat {
struct mmc mmc;
 };
 
+struct rockchip_emmc_phy {
+   u32 emmcphy_con[7];
+   u32 reserved;
+   u32 emmcphy_status;
+};
+
 struct rockchip_sdhc {
struct sdhci_host host;
void *base;
+   struct rockchip_emmc_phy *phy;
 };
 
+#define PHYCTRL_CALDONE_MASK   0x1
+#define PHYCTRL_CALDONE_SHIFT  0x6
+#define PHYCTRL_CALDONE_DONE   0x1
+
+#define PHYCTRL_DLLRDY_MASK0x1
+#define PHYCTRL_DLLRDY_SHIFT   0x5
+#define PHYCTRL_DLLRDY_DONE0x1
+
+#define PHYCTRL_FREQSEL_200M0x0
+#define PHYCTRL_FREQSEL_50M 0x1
+#define PHYCTRL_FREQSEL_100M0x2
+#define PHYCTRL_FREQSEL_150M0x3
+
+#define KHz(1000)
+#define MHz(1000 * KHz)
+
+static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
+{
+   u32 caldone, dllrdy, freqsel;
+   uint start;
+
+   writel(RK_CLRSETBITS(7 << 4, 0), >emmcphy_con[6]);
+   writel(RK_CLRSETBITS(1 << 11, 1 << 11), >emmcphy_con[0]);
+   writel(RK_CLRSETBITS(0xf << 7, 4 << 7), >emmcphy_con[0]);
+
+   /*
+* According to the user manual, calpad calibration
+* cycle takes more than 2us without the minimal recommended
+* value, so we may need a little margin here
+*/
+   udelay(3);
+   writel(RK_CLRSETBITS(1, 1), >emmcphy_con[6]);
+
+   /*
+* According to the user manual, it asks driver to
+* wait 5us for calpad busy trimming
+*/
+   udelay(5);
+   caldone = readl(>emmcphy_status);
+   caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
+   if (caldone != PHYCTRL_CALDONE_DONE) {
+   debug("%s: caldone timeout.\n", __func__);
+   return;
+   }
+
+   /* Set the frequency of the DLL operation */
+   if (clock < 75 * MHz)
+   freqsel = PHYCTRL_FREQSEL_50M;
+   else if (clock < 125 * MHz)
+   freqsel = PHYCTRL_FREQSEL_100M;
+   else if (clock < 175 * MHz)
+   freqsel = PHYCTRL_FREQSEL_150M;
+   else
+   freqsel = PHYCTRL_FREQSEL_200M;
+
+   /* Set the frequency of the DLL operation */
+   writel(RK_CLRSETBITS(3 << 12, freqsel << 12), >emmcphy_con[0]);
+   writel(RK_CLRSETBITS(1 << 1, 1 << 1), >emmcphy_con[6]);
+
+   start = get_timer(0);
+
+   do {
+   udelay(1);
+   dllrdy = readl(>emmcphy_status);
+   dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
+   if (dllrdy == PHYCTRL_DLLRDY_DONE)
+   break;
+   } while (get_timer(start) < 5);
+
+   if (dllrdy != PHYCTRL_DLLRDY_DONE)
+   debug("%s: dllrdy timeout.\n", __func__);
+}
+
+static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
+{
+   writel(RK_CLRSETBITS(1, 0), >emmcphy_con[6]);
+   writel(RK_CLRSETBITS(1 << 1, 0), >emmcphy_con[6]);
+}
+
+static int arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+   struct rockchip_sdhc *priv =
+   container_of(host, struct rockchip_sdhc, host);
+   int cycle_phy = host->clock != clock &&
+   clock > EMMC_MIN_FREQ;
+
+   if (cycle_phy)
+   rk3399_emmc_phy_power_off(priv->phy);
+
+   sdhci_set_clock(host, clock);
+
+   if (cycle_phy)
+   rk3399_emmc_phy_power_on(priv->phy, clock);
+
+   return 0;
+}
+
+static struct sdhci_ops arasan_sdhci_ops = {
+   .set_clock  = arasan_sdhci_set_clock,
+};
+
+static int arasan_get_phy(struct udevice *dev)
+{
+   struct rockchip_sdhc *priv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   priv->phy = (struct rockchip_emmc_phy *)0xff77f780;
+#else
+   int phy_node, grf_node;
+   fdt_addr_t grf_base, grf_phy_offset;
+
+   phy_node = fdtdec_lookup_phandle(gd->fdt_blob,
+dev_of_offset(dev), "phys");
+   if (phy_node <= 0) {
+   debug("Not found emmc phy device\n");
+   return -ENODEV;
+   }
+
+   grf_node = fdt_parent_offset(gd->fdt_blob, 

[U-Boot] [PATCH 16/33] rockchip: clk: rk3288: add support for the clock phase

[Ziyuan Xu]

This patch adds phase adjustment for mmc clock(ciu_sample), which is
used to select the optimal sampling point of a data input.

The phase shift is achieved through 255 delay elements(40-80
picoseconds),  and calculate the number of delay element via clock
frequency.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3288.c | 124 ++
 1 file changed, 124 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c 
b/drivers/clk/rockchip/clk_rk3288.c
index b924a3b..3279e01 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -514,6 +514,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, 
uint gclk_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
+   case SCLK_EMMC_SAMPLE:
con = readl(>cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
@@ -669,7 +670,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
case HCLK_SDMMC:
case HCLK_SDIO0:
case SCLK_EMMC:
+   case SCLK_EMMC_SAMPLE:
case SCLK_SDMMC:
+   case SCLK_SDMMC_SAMPLE:
case SCLK_SDIO0:
new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
break;
@@ -784,9 +787,130 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong 
rate)
return new_rate;
 }
 
+#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
+#define ROCKCHIP_MMC_DEGREE_MASK   0x3
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET   2
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
+
+#define PSECS_PER_SEC 1LL
+/*
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 
57.8deg.
+ */
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+
+int rockchip_mmc_get_phase(struct clk *clk)
+{
+   struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+   struct rk3288_cru *cru = priv->cru;
+   u32 raw_value, delay_num;
+   u16 degrees = 0;
+   ulong rate;
+
+   rate = rk3288_clk_get_rate(clk);
+
+   if (rate < 0)
+   return rate;
+
+   if (clk->id == SCLK_EMMC_SAMPLE)
+   raw_value = readl(>cru_emmc_con[1]);
+   else
+   raw_value = readl(>cru_sdmmc_con[1]);
+
+   degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
+
+   if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
+   /* degrees/delaynum * 1 */
+   unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
+   36 * (rate / 100);
+
+   delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
+   delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
+   degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1);
+   }
+
+   return degrees % 360;
+}
+
+int rockchip_mmc_set_phase(struct clk *clk, u32 degrees)
+{
+   struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+   struct rk3288_cru *cru = priv->cru;
+   u8 nineties, remainder, delay_num;
+   u32 raw_value, delay;
+   ulong rate;
+
+   rate = rk3288_clk_get_rate(clk);
+
+   if (rate < 0)
+   return rate;
+
+   nineties = degrees / 90;
+   remainder = (degrees % 90);
+
+   /*
+* Convert to delay; do a little extra work to make sure we
+* don't overflow 32-bit / 64-bit numbers.
+*/
+   delay = 1000; /* PSECS_PER_SEC / 1 / 10 */
+   delay *= remainder;
+   delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *
+   (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
+
+   delay_num = (u8)min_t(u32, delay, 255);
+
+   raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
+   raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
+   raw_value |= nineties;
+
+   if (clk->id == SCLK_EMMC_SAMPLE)
+   writel(raw_value | 0x, >cru_emmc_con[1]);
+   else
+   writel(raw_value | 0x, >cru_sdmmc_con[1]);
+
+   debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n",
+ degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk));
+
+   return 0;
+}
+
+static int rk3288_clk_get_phase(struct clk *clk)
+{
+   int ret;
+
+   switch (clk->id) {
+   case SCLK_EMMC_SAMPLE:
+   case SCLK_SDMMC_SAMPLE:
+   ret = rockchip_mmc_get_phase(clk);
+   break;
+   default:
+   return -ENOENT;
+   }
+
+   return ret;
+}
+
+static int rk3288_clk_set_phase(struct clk *clk, int degrees)
+{
+   int ret;
+
+   switch (clk->id) {
+   case SCLK_EMMC_SAMPLE:
+   case SCLK_SDMMC_SAMPLE:
+

[U-Boot] [PATCH 21/33] mmc: add DDR52 support for eMMC card

[Ziyuan Xu]

4.41+ eMMC card devices can run at 52MHz on DDR 8-bit mode, it can
improve write/read performance. Host driver can set MMC_MODE_DDR_52Mhz
to enable this feature.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 953ffd8..c1f54c3 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -795,6 +795,27 @@ static int mmc_select_hs(struct mmc *mmc)
return ret;
 }
 
+static int mmc_select_hs_ddr(struct mmc *mmc)
+{
+   u32 ext_csd_bits;
+   int err = 0;
+
+   if (mmc->bus_width == MMC_BUS_WIDTH_1BIT)
+   return 0;
+
+   ext_csd_bits = (mmc->bus_width == MMC_BUS_WIDTH_8BIT) ?
+   EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4;
+
+   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_BUS_WIDTH, ext_csd_bits);
+   if (err)
+   return err;
+
+   mmc_set_timing(mmc, MMC_TIMING_MMC_DDR52);
+
+   return 0;
+}
+
 #ifndef CONFIG_SPL_BUILD
 static int mmc_select_hs200(struct mmc *mmc)
 {
@@ -941,8 +962,11 @@ static int mmc_change_freq(struct mmc *mmc)
 
if (mmc_card_hs200(mmc))
err = mmc_hs200_tuning(mmc);
-   else
+   else if (!mmc_card_hs400es(mmc)) {
err = mmc_select_bus_width(mmc) > 0 ? 0 : err;
+   if (!err && avail_type & EXT_CSD_CARD_TYPE_DDR_52)
+   err = mmc_select_hs_ddr(mmc);
+   }
 
return err;
 }
-- 
2.7.4


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[U-Boot] [PATCH 27/33] mmc: sdhci: rename set_clock callback

[Ziyuan Xu]

In fact, the original name is unsuitable for its behavior. It's better
to rename to set_clock_ext.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/s5p_sdhci.c | 4 ++--
 drivers/mmc/sdhci.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 640ea02..b8d3ded 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -73,14 +73,14 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host 
*host)
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
 }
 
-static void s5p_set_clock(struct sdhci_host *host, u32 div)
+static void s5p_set_clock_ext(struct sdhci_host *host, u32 div)
 {
/* ToDo : Use the Clock Framework */
set_mmc_clk(host->index, div);
 }
 
 static const struct sdhci_ops s5p_sdhci_ops = {
-   .set_clock  = _set_clock,
+   .set_clock_ext  = _set_clock_ext,
.set_control_reg = _sdhci_set_control_reg,
 };
 
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 8f4a2a1..5c6dbdc 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -366,8 +366,8 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
div >>= 1;
}
 
-   if (host->ops && host->ops->set_clock)
-   host->ops->set_clock(host, div);
+   if (host->ops && host->ops->set_clock_ext)
+   host->ops->set_clock_ext(host, div);
 
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
-- 
2.7.4


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[U-Boot] [PATCH 14/33] clk: introduce clk_phase get/set function & callback

[Ziyuan Xu]

A common operation for a clock signal generator is to shift the phase of
that signal. This patch introduces a new function to the clk.h API to
dynamically adjust the phase of a clock signal. Additionally this patch
introduces support for the new function in the clock framework via the
.set_phase & .get_phase callback in struct clk_ops.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/clk-uclass.c | 20 
 include/clk-uclass.h | 17 +
 include/clk.h| 20 
 3 files changed, 57 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 6fcfd69..47628b1 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -165,6 +165,26 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
return ops->set_rate(clk, rate);
 }
 
+int clk_get_phase(struct clk *clk)
+{
+   struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+   if (!ops->get_phase)
+   return -ENOSYS;
+
+   return ops->get_phase(clk);
+}
+
+int clk_set_phase(struct clk *clk, int degrees)
+{
+   struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+   if (!ops->set_phase)
+   return -ENOSYS;
+
+   return ops->set_phase(clk, degrees);
+}
+
 int clk_enable(struct clk *clk)
 {
struct clk_ops *ops = clk_dev_ops(clk->dev);
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index 07c1065..0e56daa 100644
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -77,6 +77,23 @@ struct clk_ops {
 */
ulong (*set_rate)(struct clk *clk, ulong rate);
/**
+* clk_get_phase() - Get the phase shift of a clock signal.
+*
+* @clk:The clock to manipulate.
+* @return the phase shift of a clock node in degrees,
+*  otherwise returns -ve error code.
+*/
+   int (*get_phase)(struct clk *clk);
+
+   /**
+* clk_set_rate() - Adjust the phase shift of a clock signal.
+*
+* @clk:The clock to manipulate.
+* @degrees:Numberof degrees the signal is shifted.
+* @return 0 on success, or -ve error code.
+*/
+   int (*set_phase)(struct clk *clk, int degrees);
+   /**
 * enable() - Enable a clock.
 *
 * @clk:The clock to manipulate.
diff --git a/include/clk.h b/include/clk.h
index 5a5c2ff..1858fef 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -157,6 +157,26 @@ ulong clk_get_rate(struct clk *clk);
 ulong clk_set_rate(struct clk *clk, ulong rate);
 
 /**
+ * clk_get_phase() - Get the phase shift of a clock signal.
+ *
+ * @clk:   A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @return the phase shift of a clock node in degrees, otherwise returns
+ * -ve error code.
+ */
+int clk_get_phase(struct clk *clk);
+
+/**
+ * clk_set_rate() - Adjust the phase shift of a clock signal.
+ *
+ * @clk:   A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @degrees:   Numberof degrees the signal is shifted.
+ * @return 0 on success, or -ve error code.
+ */
+int clk_set_phase(struct clk *clk, int degrees);
+
+/**
  * clk_enable() - Enable (turn on) a clock.
  *
  * @clk:   A clock struct that was previously successfully requested by
-- 
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[U-Boot] [PATCH 28/33] mmc: sdhci: export sdhci_set_clock()

[Ziyuan Xu]

For arasan-rk3399-sdhci controller, we should make sure the phy is in
poweroff status before we configure the clock stuff. So that we need to
export it for phy configuration.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/sdhci.c | 16 +++-
 include/sdhci.h |  5 -
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 5c6dbdc..b9cd13a 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -301,9 +301,8 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
return -ECOMM;
 }
 
-static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
+int sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 {
-   struct sdhci_host *host = mmc->priv;
unsigned int div, clk = 0, timeout;
 
/* Wait max 20 ms */
@@ -319,12 +318,10 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
timeout--;
udelay(100);
}
-
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 
if (clock == 0)
return 0;
-
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
/*
 * Check if the Host Controller supports Programmable Clock
@@ -365,7 +362,6 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
}
div >>= 1;
}
-
if (host->ops && host->ops->set_clock_ext)
host->ops->set_clock_ext(host, div);
 
@@ -387,12 +383,10 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int 
clock)
timeout--;
udelay(1000);
}
-
clk |= SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 
host->clock = clock;
-
return 0;
 }
 
@@ -490,8 +484,12 @@ static int sdhci_set_ios(struct mmc *mmc)
if (host->ops && host->ops->set_control_reg)
host->ops->set_control_reg(host);
 
-   if (mmc->clock != host->clock)
-   sdhci_set_clock(mmc, mmc->clock);
+   if (mmc->clock != host->clock) {
+   if (host->ops && host->ops->set_clock)
+   host->ops->set_clock(host, mmc->clock);
+   else
+   sdhci_set_clock(host, mmc->clock);
+   }
 
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
diff --git a/include/sdhci.h b/include/sdhci.h
index 449ada1..da21194 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -254,7 +254,8 @@ struct sdhci_ops {
int (*get_cd)(struct sdhci_host *host);
void(*set_control_reg)(struct sdhci_host *host);
void(*set_ios_post)(struct sdhci_host *host);
-   void(*set_clock)(struct sdhci_host *host, u32 div);
+   int (*set_clock)(struct sdhci_host *host, unsigned int clock);
+   void(*set_clock_ext)(struct sdhci_host *host, u32 div);
 };
 
 struct sdhci_host {
@@ -279,6 +280,8 @@ struct sdhci_host {
struct mmc_config cfg;
 };
 
+int sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
+
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 
 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
-- 
2.7.4


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[U-Boot] [PATCH 30/33] mmc: sdhci: add the support for tuning

[Ziyuan Xu]

MMC framework has already implemented hs200 mode for eMMC devices,
moreover the standard SDHC3.0 controller support tuning. We can set the
corresponding flag in host->host_cpas.

Host driver issue tuning command repeatedly until the host controller
resets Execute Tuning to 0. Host controller resets Execute Tuning to 0
when tuning is completed or tuning is not completed within 40 times.
Host driver can abort this loop by 40 times CMD19/CMD21 issue or 150ms
time-out. If tuning is completed successfully, driver set Sampling Clock
Select to 1 and this means the host contorller start to use tuned
sampling clcok. If tuning is failed, host controller keeps Sampling
Clock Select to 0.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/sdhci.c | 116 +++-
 1 file changed, 115 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index b9cd13a..e346820 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -158,7 +158,10 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
-   mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
+   mask = SDHCI_CMD_INHIBIT;
+
+   if (data)
+   mask |= SDHCI_DATA_INHIBIT;
 
/* We shouldn't wait for data inihibit for stop commands, even
   though they might use busy signaling */
@@ -200,6 +203,13 @@ static int sdhci_send_command(struct mmc *mmc, struct 
mmc_cmd *cmd,
if (data)
flags |= SDHCI_CMD_DATA;
 
+   if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK ||
+   cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) {
+   mask &= ~SDHCI_INT_RESPONSE;
+   mask |= SDHCI_INT_DATA_AVAIL;
+   flags |= SDHCI_CMD_DATA;
+   }
+
/* Set Transfer mode regarding to data flag */
if (data != 0) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
@@ -559,6 +569,108 @@ static int sdhci_init(struct mmc *mmc)
return 0;
 }
 
+static int sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
+{
+   struct mmc_cmd cmd;
+
+   cmd.cmdidx = opcode;
+   cmd.resp_type = MMC_RSP_R1;
+   cmd.cmdarg = 0;
+   /*
+* In response to CMD19, the card sends 64 bytes of tuning
+* block to the Host Controller. So we set the block size
+* to 64 here.
+*/
+   if (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
+   host->mmc->bus_width == MMC_BUS_WIDTH_8BIT)
+   sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
+   else
+   sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
+
+   /*
+* The tuning block is sent by the card to the host controller.
+* So we set the TRNS_READ bit in the Transfer Mode register.
+* This also takes care of setting DMA Enable and Multi Block
+* Select in the same register to 0.
+*/
+   sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+#ifdef CONFIG_DM_MMC_OPS
+   return sdhci_send_command(host->mmc->dev, , NULL);
+#else
+   return sdhci_send_command(host->mmc, , NULL);
+#endif
+}
+
+#define MAX_TUNING_LOOP 40
+static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
+{
+   int i;
+   int ret;
+
+   /*
+* Issue opcode repeatedly till Execute Tuning is set to 0 or the number
+* of loops reaches 40 times.
+*/
+   for (i = 0; i < MAX_TUNING_LOOP; i++) {
+   u16 ctrl;
+
+   ret = sdhci_send_tuning(host, opcode);
+
+   if (ret)
+   return ret;
+
+   ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+   if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
+   if (ctrl & SDHCI_CTRL_TUNED_CLK)
+   /* Tuning successfully */
+   return 0;
+   break;
+   }
+   }
+
+   return -ETIMEDOUT;
+}
+
+#ifdef CONFIG_DM_MMC_OPS
+static int sdhci_execute_tuning(struct udevice *dev, u32 opcode)
+{
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int sdhci_execute_tuning(struct mmc *mmc, u32 opcode)
+{
+#endif
+   struct sdhci_host *host = mmc->priv;
+   u16 ctrl;
+
+   /*
+* The Host Controller needs tuning in case of SDR104 and DDR50
+* mode, and for SDR50 mode when Use Tuning for SDR50 is set in
+* the Capabilities register.
+* If the Host Controller supports the HS200 mode then the
+* tuning function has to be executed.
+*/
+   switch (mmc->timing) {
+   /* HS400 tuning is done in HS200 mode */
+   case MMC_TIMING_MMC_HS400:
+   return -EINVAL;
+   case MMC_TIMING_MMC_HS20

[U-Boot] [PATCH 20/33] mmc: dw_mmc: reset controller after data error

[Ziyuan Xu]

Per dw_mmc databook, it's recommend that reset the host contoller if
some data-related error occurre during tuning progress.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index c05288c..e862eb2 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -97,7 +97,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
 {
int ret = 0;
u32 timeout = 24;
-   u32 mask, size, i, len = 0;
+   u32 status, ctrl, mask, size, i, len = 0;
u32 *buf = NULL;
ulong start = get_timer(0);
u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
@@ -114,6 +114,23 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
/* Error during data transfer. */
if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
debug("%s: DATA ERROR!\n", __func__);
+
+   dwmci_wait_reset(host, DWMCI_RESET_ALL);
+   dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
+DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+
+   do {
+   status = dwmci_readl(host, DWMCI_CMD);
+   if (timeout-- < 0)
+   ret = -ETIMEDOUT;
+   } while (status & DWMCI_CMD_START);
+
+   if (!host->fifo_mode) {
+   ctrl = dwmci_readl(host, DWMCI_BMOD);
+   ctrl |= DWMCI_BMOD_IDMAC_RESET;
+   dwmci_writel(host, DWMCI_BMOD, ctrl);
+   }
+
ret = -EINVAL;
break;
}
-- 
2.7.4


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[U-Boot] [PATCH 17/33] rockchip: clk: rk3399: fix emmc clock setting

[Ziyuan Xu]

Before this:
gpll = 594MHz, set_clock = 200MHz
div = 594/200 = 2
real clock is 297MHz

After this:
gpll = 594MHz, clock = 148.5MHz
div = 594+200-1/200 = 3
real clock is 198Mhz

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3399.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 026ed4d..3656f02 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -794,7 +794,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
break;
case SCLK_EMMC:
/* Select aclk_emmc source from GPLL */
-   src_clk_div = GPLL_HZ / aclk_emmc;
+   src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
assert(src_clk_div - 1 < 31);
 
rk_clrsetreg(>clksel_con[21],
@@ -803,7 +803,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 
/* Select clk_emmc source from GPLL too */
-   src_clk_div = GPLL_HZ / set_rate;
+   src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
assert(src_clk_div - 1 < 127);
 
rk_clrsetreg(>clksel_con[22],
-- 
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[U-Boot] [PATCH 02/33] mmc: add set_timing entry for timing selection

[Ziyuan Xu]

Some controller should do some configuration according to the selected
timing.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c |  7 +++
 include/mmc.h | 49 +
 2 files changed, 56 insertions(+)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f5b2280..1b3652a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -318,6 +318,12 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t 
start, lbaint_t blkcnt,
return blkcnt;
 }
 
+static void mmc_set_timing(struct mmc *mmc, uint timing)
+{
+   mmc->timing = timing;
+   mmc_set_ios(mmc);
+}
+
 static int mmc_go_idle(struct mmc *mmc)
 {
struct mmc_cmd cmd;
@@ -1734,6 +1740,7 @@ int mmc_start_init(struct mmc *mmc)
mmc->ddr_mode = 0;
mmc_set_bus_width(mmc, 1);
mmc_set_clock(mmc, 1);
+   mmc_set_timing(mmc, MMC_TIMING_LEGACY);
 
/* Reset the Card */
err = mmc_go_idle(mmc);
diff --git a/include/mmc.h b/include/mmc.h
index 0bae1a1..68b6790 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -434,6 +434,21 @@ struct mmc {
uint has_init;
int high_capacity;
uint bus_width;
+   uint timing;
+
+#define MMC_TIMING_LEGACY  0
+#define MMC_TIMING_MMC_HS  1
+#define MMC_TIMING_SD_HS   2
+#define MMC_TIMING_UHS_SDR12   3
+#define MMC_TIMING_UHS_SDR25   4
+#define MMC_TIMING_UHS_SDR50   5
+#define MMC_TIMING_UHS_SDR104  6
+#define MMC_TIMING_UHS_DDR50   7
+#define MMC_TIMING_MMC_DDR52   8
+#define MMC_TIMING_MMC_HS200   9
+#define MMC_TIMING_MMC_HS400   10
+#define MMC_TIMING_MMC_HS400ES 11
+
uint clock;
uint card_caps;
uint ocr;
@@ -493,6 +508,40 @@ enum mmc_hwpart_conf_mode {
MMC_HWPART_CONF_COMPLETE,
 };
 
+static inline bool mmc_card_hs(struct mmc *mmc)
+{
+   return (mmc->timing == MMC_TIMING_MMC_HS) ||
+   (mmc->timing == MMC_TIMING_SD_HS);
+}
+
+static inline bool mmc_card_ddr(struct mmc *mmc)
+{
+   return (mmc->timing == MMC_TIMING_UHS_DDR50) ||
+   (mmc->timing == MMC_TIMING_MMC_DDR52) ||
+   (mmc->timing == MMC_TIMING_MMC_HS400) ||
+   (mmc->timing == MMC_TIMING_MMC_HS400ES);
+}
+
+static inline bool mmc_card_hs200(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_HS200;
+}
+
+static inline bool mmc_card_ddr52(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_DDR52;
+}
+
+static inline bool mmc_card_hs400(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_HS400;
+}
+
+static inline bool mmc_card_hs400es(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_HS400ES;
+}
+
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 
 /**
-- 
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[U-Boot] [PATCH 12/33] mmc: remove tran_speed from struct mmc

[Ziyuan Xu]

The clock element is updated by mmc_set_clock every time, it denotes the
current transfer speed.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 cmd/mmc.c |  2 +-
 drivers/mmc/mmc.c | 10 +-
 drivers/mmc/xenon_sdhci.c |  2 +-
 include/mmc.h |  1 -
 4 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/cmd/mmc.c b/cmd/mmc.c
index ef05fa5..6ead27a 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -23,7 +23,7 @@ static void print_mmcinfo(struct mmc *mmc)
(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
 
-   printf("Tran Speed: %d\n", mmc->tran_speed);
+   printf("Tran Speed: %d\n", mmc->clock);
printf("Rd Block Len: %d\n", mmc->read_bl_len);
 
printf("%s version %d.%d", IS_SD(mmc) ? "SD" : "MMC",
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d47cfe6..953ffd8 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1449,7 +1449,7 @@ static bool mmc_can_card_busy(struct mmc *)
 static int mmc_startup(struct mmc *mmc)
 {
int err, i;
-   uint mult, freq;
+   uint mult, freq, tran_speed;
u64 cmult, csize, capacity;
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
@@ -1545,7 +1545,7 @@ static int mmc_startup(struct mmc *mmc)
freq = fbase[(cmd.response[0] & 0x7)];
mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
 
-   mmc->tran_speed = freq * mult;
+   tran_speed = freq * mult;
 
mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
@@ -1792,11 +1792,11 @@ static int mmc_startup(struct mmc *mmc)
return err;
 
if (mmc->card_caps & MMC_MODE_HS)
-   mmc->tran_speed = 5000;
+   tran_speed = 5000;
else
-   mmc->tran_speed = 2500;
+   tran_speed = 2500;
 
-   mmc_set_clock(mmc, mmc->tran_speed);
+   mmc_set_clock(mmc, tran_speed);
}
 
/* Fix the block length for DDR mode */
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 7685e15..f18dc8f 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -318,7 +318,7 @@ static void xenon_mask_cmd_conflict_err(struct sdhci_host 
*host)
 static void xenon_sdhci_set_ios_post(struct sdhci_host *host)
 {
struct xenon_sdhci_priv *priv = host->mmc->priv;
-   uint speed = host->mmc->tran_speed;
+   uint speed = host->mmc->clock;
int pwr_18v = 0;
 
if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
diff --git a/include/mmc.h b/include/mmc.h
index bde8b37..05bf39d 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -504,7 +504,6 @@ struct mmc {
u8 part_attr;
u8 wr_rel_set;
char part_config;
-   uint tran_speed;
uint read_bl_len;
uint write_bl_len;
uint erase_grp_size;/* in 512-byte sectors */
-- 
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[U-Boot] [PATCH 18/33] mmc: dw_mmc: add the support for the tuning scheme

[Ziyuan Xu]

For the HS200/HS400/SDR104, tuning is needed to determine the optimal
sampling point. Actual tuning procedure is provided by specific host
controller driver.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c | 18 ++
 include/dwmmc.h  |  1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7e9ffc2..c05288c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -404,6 +404,22 @@ static bool dwmci_card_busy(struct mmc *mmc)
 }
 
 #ifdef CONFIG_DM_MMC_OPS
+static int dwmci_execute_tuning(struct udevice *dev, u32 opcode)
+{
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode)
+{
+#endif
+   struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+
+   if (!host->execute_tuning)
+   return -EIO;
+
+   return host->execute_tuning(host, opcode);
+}
+
+#ifdef CONFIG_DM_MMC_OPS
 static int dwmci_set_ios(struct udevice *dev)
 {
struct mmc *mmc = mmc_get_mmc_dev(dev);
@@ -498,6 +514,7 @@ const struct dm_mmc_ops dm_dwmci_ops = {
.card_busy  = dwmci_card_busy,
.send_cmd   = dwmci_send_cmd,
.set_ios= dwmci_set_ios,
+   .execute_tuning = dwmci_execute_tuning,
 };
 
 #else
@@ -506,6 +523,7 @@ static const struct mmc_ops dwmci_ops = {
.send_cmd   = dwmci_send_cmd,
.set_ios= dwmci_set_ios,
.init   = dwmci_init,
+   .execute_tuning = dwmci_execute_tuning,
 };
 #endif
 
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 4dda009..95be7c2 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -180,6 +180,7 @@ struct dwmci_host {
 * @freq:   Frequency the host is trying to achieve
 */
unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
+   int (*execute_tuning)(struct dwmci_host *host, u32 opcode);
 #ifndef CONFIG_BLK
struct mmc_config cfg;
 #endif
-- 
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[U-Boot] [PATCH 07/33] mmc: dw_mmc: implement card_busy detection

[Ziyuan Xu]

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 700f764..baf2280 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -384,6 +384,26 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 
freq)
 }
 
 #ifdef CONFIG_DM_MMC_OPS
+static bool dwmci_card_busy(struct udevice *dev)
+{
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static bool dwmci_card_busy(struct mmc *mmc)
+{
+#endif
+   u32 status;
+   struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+
+   /*
+* Check the busy bit which is low when DAT[3:0]
+* (the data lines) are 
+*/
+   status = dwmci_readl(host, DWMCI_STATUS);
+
+   return !!(status & DWMCI_BUSY);
+}
+
+#ifdef CONFIG_DM_MMC_OPS
 static int dwmci_set_ios(struct udevice *dev)
 {
struct mmc *mmc = mmc_get_mmc_dev(dev);
@@ -475,12 +495,14 @@ int dwmci_probe(struct udevice *dev)
 }
 
 const struct dm_mmc_ops dm_dwmci_ops = {
+   .card_busy  = dwmci_card_busy,
.send_cmd   = dwmci_send_cmd,
.set_ios= dwmci_set_ios,
 };
 
 #else
 static const struct mmc_ops dwmci_ops = {
+   .card_busy  = dwmci_card_busy,
.send_cmd   = dwmci_send_cmd,
.set_ios= dwmci_set_ios,
.init   = dwmci_init,
-- 
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[U-Boot] [PATCH 04/33] mmc: rework high speed mode selection

[Ziyuan Xu]

Select timing parameter for the host since HS mode switch is completed.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 16 ++--
 include/mmc.h |  6 ++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1b3652a..0b30172 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -552,6 +552,19 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 
 }
 
+static int mmc_select_hs(struct mmc *mmc)
+{
+   int ret;
+
+   ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS);
+
+   if (!ret)
+   mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
+
+   return ret;
+}
+
 static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
 {
u8 card_type;
@@ -630,8 +643,7 @@ static int mmc_change_freq(struct mmc *mmc)
avail_type = mmc_select_card_type(mmc, ext_csd);
 
if (avail_type & EXT_CSD_CARD_TYPE_HS)
-   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
-EXT_CSD_HS_TIMING, 1);
+   err = mmc_select_hs(mmc);
else
err = -EINVAL;
 
diff --git a/include/mmc.h b/include/mmc.h
index 68b6790..060c1f8 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -228,6 +228,12 @@
 #define EXT_CSD_DDR_BUS_WIDTH_45   /* Card is in 4 bit DDR mode */
 #define EXT_CSD_DDR_BUS_WIDTH_86   /* Card is in 8 bit DDR mode */
 
+#define EXT_CSD_TIMING_BC  0   /* Backwards compatility */
+#define EXT_CSD_TIMING_HS  1   /* High speed */
+#define EXT_CSD_TIMING_HS200   2   /* HS200 */
+#define EXT_CSD_TIMING_HS400   3   /* HS400 */
+#define EXT_CSD_DRV_STR_SHIFT  4   /* Driver Strength shift */
+
 #define EXT_CSD_BOOT_ACK_ENABLE(1 << 6)
 #define EXT_CSD_BOOT_PARTITION_ENABLE  (1 << 3)
 #define EXT_CSD_PARTITION_ACCESS_ENABLE(1 << 0)
-- 
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[U-Boot] [PATCH 13/33] cmd: mmc: show the current speed mode

[Ziyuan Xu]

So far mmc framework had support speed mode switch, it good to show the
current speed mode from 'mmc info'.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 cmd/mmc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/cmd/mmc.c b/cmd/mmc.c
index 6ead27a..832eeb0 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -15,6 +15,10 @@ static int curr_device = -1;
 static void print_mmcinfo(struct mmc *mmc)
 {
int i;
+   const char *timing[] = {
+   "Legacy", "High Speed", "High Speed", "SDR12",
+   "SDR25", "SDR50", "SDR104", "DDR50",
+   "DDR52", "HS200", "HS400", "HS400 Enhanced Strobe"};
 
printf("Device: %s\n", mmc->cfg->name);
printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24);
@@ -23,6 +27,7 @@ static void print_mmcinfo(struct mmc *mmc)
(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
 
+   printf("Timing Interface: %s\n", timing[mmc->timing]);
printf("Tran Speed: %d\n", mmc->clock);
printf("Rd Block Len: %d\n", mmc->read_bl_len);
 
-- 
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[U-Boot] [PATCH 09/33] mmc: rework mmc_switch for non-send_status scenario

[Ziyuan Xu]

Per JEDEC spec, it is not recommended to use cmd13 to get card status
after speed mode switch. CMD13 can't be guaranteed due to the
asynchronous operation.

Besieds, if the host controller supports busy detection in HW, we use it
instead of cmd13.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 55 +--
 1 file changed, 45 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 13d8f04..9aee6ff 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -523,10 +523,46 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
return err;
 }
 
-int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
+static int mmc_poll_for_busy(struct mmc *mmc)
 {
struct mmc_cmd cmd;
+   u8 busy = true;
+   uint start;
+   int ret;
int timeout = 1000;
+
+   cmd.cmdidx = MMC_CMD_SEND_STATUS;
+   cmd.resp_type = MMC_RSP_R1;
+   cmd.cmdarg = mmc->rca << 16;
+
+   start = get_timer(0);
+
+   do {
+   if (mmc_can_card_busy(mmc)) {
+   busy = mmc_card_busy(mmc);
+   } else {
+   ret = mmc_send_cmd(mmc, , NULL);
+
+   if (ret)
+   return ret;
+
+   if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
+   return -EBADMSG;
+   busy = (cmd.response[0] & MMC_STATUS_CURR_STATE) ==
+   MMC_STATE_PRG;
+   }
+
+   if (get_timer(start) > timeout && busy)
+   return -ETIMEDOUT;
+   } while (busy);
+
+   return 0;
+}
+
+static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
+   u8 send_status)
+{
+   struct mmc_cmd cmd;
int retries = 3;
int ret;
 
@@ -536,20 +572,19 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 
value)
 (index << 16) |
 (value << 8);
 
-   while (retries > 0) {
+   do {
ret = mmc_send_cmd(mmc, , NULL);
 
-   /* Waiting for the ready status */
-   if (!ret) {
-   ret = mmc_send_status(mmc, timeout);
-   return ret;
-   }
-
-   retries--;
-   }
+   if (!ret && send_status)
+   return mmc_poll_for_busy(mmc);
+   } while (--retries > 0 && ret);
 
return ret;
+}
 
+int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
+{
+   return __mmc_switch(mmc, set, index, value, true);
 }
 
 static int mmc_select_hs(struct mmc *mmc)
-- 
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[U-Boot] [PATCH 03/33] mmc: xenon_sdhci: drop redundant timing definitions

[Ziyuan Xu]

Remove the redundant mmc timing definitions which have defined in mmc.h.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/xenon_sdhci.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 2a0d8b4..f0a33c1 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -94,18 +94,6 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Hyperion only have one slot 0 */
 #define XENON_MMC_SLOT_ID_HYPERION 0
 
-#define MMC_TIMING_LEGACY  0
-#define MMC_TIMING_MMC_HS  1
-#define MMC_TIMING_SD_HS   2
-#define MMC_TIMING_UHS_SDR12   3
-#define MMC_TIMING_UHS_SDR25   4
-#define MMC_TIMING_UHS_SDR50   5
-#define MMC_TIMING_UHS_SDR104  6
-#define MMC_TIMING_UHS_DDR50   7
-#define MMC_TIMING_MMC_DDR52   8
-#define MMC_TIMING_MMC_HS200   9
-#define MMC_TIMING_MMC_HS400   10
-
 #define XENON_MMC_MAX_CLK  4
 
 enum soc_pad_ctrl_type {
-- 
2.7.4


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[U-Boot] [PATCH 08/33] mmc: sdhci: implement card_busy detection

[Ziyuan Xu]

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/sdhci.c | 19 +++
 include/sdhci.h |  1 +
 2 files changed, 20 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 58cc0ab..48bac04 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -424,6 +424,23 @@ static void sdhci_set_power(struct sdhci_host *host, 
unsigned short power)
 }
 
 #ifdef CONFIG_DM_MMC_OPS
+static bool sdhci_card_busy(struct udevice *dev)
+{
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static bool sdhci_card_busy(struct mmc *mmc)
+{
+#endif
+   struct sdhci_host *host = mmc->priv;
+   u32 present_state;
+
+   /* Check whether DAT[0] is 0 */
+   present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
+
+   return !(present_state & SDHCI_DATA_0_LVL);
+}
+
+#ifdef CONFIG_DM_MMC_OPS
 static int sdhci_set_ios(struct udevice *dev)
 {
struct mmc *mmc = mmc_get_mmc_dev(dev);
@@ -510,11 +527,13 @@ int sdhci_probe(struct udevice *dev)
 }
 
 const struct dm_mmc_ops sdhci_ops = {
+   .card_busy  = sdhci_card_busy,
.send_cmd   = sdhci_send_command,
.set_ios= sdhci_set_ios,
 };
 #else
 static const struct mmc_ops sdhci_ops = {
+   .card_busy  = sdhci_card_busy,
.send_cmd   = sdhci_send_command,
.set_ios= sdhci_set_ios,
.init   = sdhci_init,
diff --git a/include/sdhci.h b/include/sdhci.h
index 6a43271..75432db 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -64,6 +64,7 @@
 #define  SDHCI_CARD_STATE_STABLE   BIT(17)
 #define  SDHCI_CARD_DETECT_PIN_LEVEL   BIT(18)
 #define  SDHCI_WRITE_PROTECT   BIT(19)
+#define SDHCI_DATA_0_LVL   BIT(20)
 
 #define SDHCI_HOST_CONTROL 0x28
 #define  SDHCI_CTRL_LEDBIT(0)
-- 
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[U-Boot] [PATCH 05/33] mmc: sdhci: fix HISPD bit setting

[Ziyuan Xu]

Configure HISPD bit field according to the timing parameter instead of
the card clock frequency.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/sdhci.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index b745977..58cc0ab 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -457,14 +457,12 @@ static int sdhci_set_ios(struct mmc *mmc)
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
 
-   if (mmc->clock > 2600)
+   if (!(mmc->timing == MMC_TIMING_LEGACY) &&
+   !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
 
-   if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
-   ctrl &= ~SDHCI_CTRL_HISPD;
-
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 
/* If available, call the driver specific "post" set_ios() function */
-- 
2.7.4


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[U-Boot] [PATCH 05/33] mmc: sdhci: fix HISPD bit setting

[Ziyuan Xu]

Configure HISPD bit field according to the timing parameter instead of
the card clock frequency.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/sdhci.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index b745977..58cc0ab 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -457,14 +457,12 @@ static int sdhci_set_ios(struct mmc *mmc)
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
 
-   if (mmc->clock > 2600)
+   if (!(mmc->timing == MMC_TIMING_LEGACY) &&
+   !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
 
-   if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
-   ctrl &= ~SDHCI_CTRL_HISPD;
-
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 
/* If available, call the driver specific "post" set_ios() function */
-- 
2.7.4


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[U-Boot] [PATCH 02/33] mmc: add set_timing entry for timing selection

[Ziyuan Xu]

Some controller should do some configuration according to the selected
timing.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c |  7 +++
 include/mmc.h | 49 +
 2 files changed, 56 insertions(+)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f5b2280..1b3652a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -318,6 +318,12 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t 
start, lbaint_t blkcnt,
return blkcnt;
 }
 
+static void mmc_set_timing(struct mmc *mmc, uint timing)
+{
+   mmc->timing = timing;
+   mmc_set_ios(mmc);
+}
+
 static int mmc_go_idle(struct mmc *mmc)
 {
struct mmc_cmd cmd;
@@ -1734,6 +1740,7 @@ int mmc_start_init(struct mmc *mmc)
mmc->ddr_mode = 0;
mmc_set_bus_width(mmc, 1);
mmc_set_clock(mmc, 1);
+   mmc_set_timing(mmc, MMC_TIMING_LEGACY);
 
/* Reset the Card */
err = mmc_go_idle(mmc);
diff --git a/include/mmc.h b/include/mmc.h
index 0bae1a1..68b6790 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -434,6 +434,21 @@ struct mmc {
uint has_init;
int high_capacity;
uint bus_width;
+   uint timing;
+
+#define MMC_TIMING_LEGACY  0
+#define MMC_TIMING_MMC_HS  1
+#define MMC_TIMING_SD_HS   2
+#define MMC_TIMING_UHS_SDR12   3
+#define MMC_TIMING_UHS_SDR25   4
+#define MMC_TIMING_UHS_SDR50   5
+#define MMC_TIMING_UHS_SDR104  6
+#define MMC_TIMING_UHS_DDR50   7
+#define MMC_TIMING_MMC_DDR52   8
+#define MMC_TIMING_MMC_HS200   9
+#define MMC_TIMING_MMC_HS400   10
+#define MMC_TIMING_MMC_HS400ES 11
+
uint clock;
uint card_caps;
uint ocr;
@@ -493,6 +508,40 @@ enum mmc_hwpart_conf_mode {
MMC_HWPART_CONF_COMPLETE,
 };
 
+static inline bool mmc_card_hs(struct mmc *mmc)
+{
+   return (mmc->timing == MMC_TIMING_MMC_HS) ||
+   (mmc->timing == MMC_TIMING_SD_HS);
+}
+
+static inline bool mmc_card_ddr(struct mmc *mmc)
+{
+   return (mmc->timing == MMC_TIMING_UHS_DDR50) ||
+   (mmc->timing == MMC_TIMING_MMC_DDR52) ||
+   (mmc->timing == MMC_TIMING_MMC_HS400) ||
+   (mmc->timing == MMC_TIMING_MMC_HS400ES);
+}
+
+static inline bool mmc_card_hs200(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_HS200;
+}
+
+static inline bool mmc_card_ddr52(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_DDR52;
+}
+
+static inline bool mmc_card_hs400(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_HS400;
+}
+
+static inline bool mmc_card_hs400es(struct mmc *mmc)
+{
+   return mmc->timing == MMC_TIMING_MMC_HS400ES;
+}
+
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 
 /**
-- 
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[U-Boot] [PATCH 04/33] mmc: rework high speed mode selection

[Ziyuan Xu]

Select timing parameter for the host since HS mode switch is completed.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 16 ++--
 include/mmc.h |  6 ++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1b3652a..0b30172 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -552,6 +552,19 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 
 }
 
+static int mmc_select_hs(struct mmc *mmc)
+{
+   int ret;
+
+   ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS);
+
+   if (!ret)
+   mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
+
+   return ret;
+}
+
 static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
 {
u8 card_type;
@@ -630,8 +643,7 @@ static int mmc_change_freq(struct mmc *mmc)
avail_type = mmc_select_card_type(mmc, ext_csd);
 
if (avail_type & EXT_CSD_CARD_TYPE_HS)
-   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
-EXT_CSD_HS_TIMING, 1);
+   err = mmc_select_hs(mmc);
else
err = -EINVAL;
 
diff --git a/include/mmc.h b/include/mmc.h
index 68b6790..060c1f8 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -228,6 +228,12 @@
 #define EXT_CSD_DDR_BUS_WIDTH_45   /* Card is in 4 bit DDR mode */
 #define EXT_CSD_DDR_BUS_WIDTH_86   /* Card is in 8 bit DDR mode */
 
+#define EXT_CSD_TIMING_BC  0   /* Backwards compatility */
+#define EXT_CSD_TIMING_HS  1   /* High speed */
+#define EXT_CSD_TIMING_HS200   2   /* HS200 */
+#define EXT_CSD_TIMING_HS400   3   /* HS400 */
+#define EXT_CSD_DRV_STR_SHIFT  4   /* Driver Strength shift */
+
 #define EXT_CSD_BOOT_ACK_ENABLE(1 << 6)
 #define EXT_CSD_BOOT_PARTITION_ENABLE  (1 << 3)
 #define EXT_CSD_PARTITION_ACCESS_ENABLE(1 << 0)
-- 
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[U-Boot] [PATCH 03/33] mmc: xenon_sdhci: drop redundant timing definitions

[Ziyuan Xu]

Remove the redundant mmc timing definitions which have defined in mmc.h.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/xenon_sdhci.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 2a0d8b4..f0a33c1 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -94,18 +94,6 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Hyperion only have one slot 0 */
 #define XENON_MMC_SLOT_ID_HYPERION 0
 
-#define MMC_TIMING_LEGACY  0
-#define MMC_TIMING_MMC_HS  1
-#define MMC_TIMING_SD_HS   2
-#define MMC_TIMING_UHS_SDR12   3
-#define MMC_TIMING_UHS_SDR25   4
-#define MMC_TIMING_UHS_SDR50   5
-#define MMC_TIMING_UHS_SDR104  6
-#define MMC_TIMING_UHS_DDR50   7
-#define MMC_TIMING_MMC_DDR52   8
-#define MMC_TIMING_MMC_HS200   9
-#define MMC_TIMING_MMC_HS400   10
-
 #define XENON_MMC_MAX_CLK  4
 
 enum soc_pad_ctrl_type {
-- 
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[U-Boot] [PATCH 01/33] mmc: select the available type from host_caps and card_caps

[Ziyuan Xu]

The original implementation select HS timing by default, add available
type selection for higher speed mode compatibility, such as hs200,
hs400, hs400es.

By the way, we assume that card run at 1.8V or 1.2V I/O when its timing
is ddr52/hs200/hs400(es).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 59 ++-
 include/mmc.h | 16 +++
 2 files changed, 74 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 72fc177..f5b2280 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -546,10 +546,62 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 
value)
 
 }
 
+static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
+{
+   u8 card_type;
+   u32 host_caps, avail_type = 0;
+
+   card_type = ext_csd[EXT_CSD_CARD_TYPE];
+   host_caps = mmc->cfg->host_caps;
+
+   if ((host_caps & MMC_MODE_HS) &&
+   (card_type & EXT_CSD_CARD_TYPE_26))
+   avail_type |= EXT_CSD_CARD_TYPE_26;
+
+   if ((host_caps & MMC_MODE_HS) &&
+   (card_type & EXT_CSD_CARD_TYPE_52))
+   avail_type |= EXT_CSD_CARD_TYPE_52;
+
+   /*
+* For the moment, u-boot doesn't support signal voltage
+* switch, therefor we assume that host support ddr52
+* at 1.8v or 3.3v I/O(1.2v I/O not supported, hs200 and
+* hs400 are the same).
+*/
+   if ((host_caps & MMC_MODE_DDR_52MHz) &&
+   (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V;
+
+   if ((host_caps & MMC_MODE_HS200) &&
+   (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V;
+
+   /*
+* If host can support HS400, it means that host can also
+* support HS200.
+*/
+   if ((host_caps & MMC_MODE_HS400) &&
+   (host_caps & MMC_MODE_8BIT) &&
+   (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V |
+   EXT_CSD_CARD_TYPE_HS400_1_8V;
+
+   if ((host_caps & MMC_MODE_HS400ES) &&
+   (host_caps & MMC_MODE_8BIT) &&
+   ext_csd[EXT_CSD_STROBE_SUPPORT] &&
+   (avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V |
+   EXT_CSD_CARD_TYPE_HS400_1_8V |
+   EXT_CSD_CARD_TYPE_HS400ES;
+
+   return avail_type;
+}
+
 static int mmc_change_freq(struct mmc *mmc)
 {
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
char cardtype;
+   u32 avail_type;
int err;
 
mmc->card_caps = 0;
@@ -569,8 +621,13 @@ static int mmc_change_freq(struct mmc *mmc)
return err;
 
cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
+   avail_type = mmc_select_card_type(mmc, ext_csd);
 
-   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+   if (avail_type & EXT_CSD_CARD_TYPE_HS)
+   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING, 1);
+   else
+   err = -EINVAL;
 
if (err)
return err;
diff --git a/include/mmc.h b/include/mmc.h
index fad12d6..0bae1a1 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -58,6 +58,9 @@
 #define MMC_MODE_8BIT  (1 << 3)
 #define MMC_MODE_SPI   (1 << 4)
 #define MMC_MODE_DDR_52MHz (1 << 5)
+#define MMC_MODE_HS200 (1 << 6)
+#define MMC_MODE_HS400 (1 << 7)
+#define MMC_MODE_HS400ES   (1 << 8)
 
 #define SD_DATA_4BIT   0x0004
 
@@ -182,6 +185,7 @@
 #define EXT_CSD_BOOT_BUS_WIDTH 177
 #define EXT_CSD_PART_CONF  179 /* R/W */
 #define EXT_CSD_BUS_WIDTH  183 /* R/W */
+#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
 #define EXT_CSD_HS_TIMING  185 /* R/W */
 #define EXT_CSD_REV192 /* RO */
 #define EXT_CSD_CARD_TYPE  196 /* RO */
@@ -201,6 +205,18 @@
 
 #define EXT_CSD_CARD_TYPE_26   (1 << 0)/* Card can run at 26MHz */
 #define EXT_CSD_CARD_TYPE_52   (1 << 1)/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_HS   (EXT_CSD_CARD_TYPE_26 | \
+EXT_CSD_CARD_TYPE_52)
+#define EXT_CSD_CARD_TYPE_HS200_1_8V   BIT(4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_HS200_1_2V   BIT(5)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_HS200(EXT_CSD_CARD_TYPE_HS200_1_8V | 
\
+EXT_CSD_CARD_TYPE_HS200_1_2V)
+#define EXT_CSD_CARD_TYPE_HS400_1_8V   BIT(6)  /* Car

[U-Boot] [PATCH 4/5] rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3288.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c 
b/drivers/clk/rockchip/clk_rk3288.c
index 7835676..fc369dd 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -513,16 +513,19 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, 
uint gclk_rate,
 
switch (periph) {
case HCLK_EMMC:
+   case SCLK_EMMC:
con = readl(>cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
case HCLK_SDMMC:
+   case SCLK_SDMMC:
con = readl(>cru_clksel_con[11]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
break;
case HCLK_SDIO0:
+   case SCLK_SDIO0:
con = readl(>cru_clksel_con[12]);
mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
@@ -556,6 +559,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, 
uint gclk_rate,
}
switch (periph) {
case HCLK_EMMC:
+   case SCLK_EMMC:
rk_clrsetreg(>cru_clksel_con[12],
 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
@@ -563,6 +567,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, 
uint gclk_rate,
 (src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
case HCLK_SDMMC:
+   case SCLK_SDMMC:
rk_clrsetreg(>cru_clksel_con[11],
 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -570,6 +575,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, 
uint gclk_rate,
 (src_clk_div - 1) << MMC0_DIV_SHIFT);
break;
case HCLK_SDIO0:
+   case SCLK_SDIO0:
rk_clrsetreg(>cru_clksel_con[12],
 SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
@@ -662,6 +668,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO0:
+   case SCLK_EMMC:
+   case SCLK_SDMMC:
+   case SCLK_SDIO0:
new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
break;
case SCLK_SPI0:
@@ -706,6 +715,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong 
rate)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO0:
+   case SCLK_EMMC:
+   case SCLK_SDMMC:
+   case SCLK_SDIO0:
new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
break;
case SCLK_SPI0:
-- 
2.7.4


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[U-Boot] [PATCH 5/5] rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3328.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3328.c 
b/drivers/clk/rockchip/clk_rk3328.c
index 0ff1e30..8ec1574 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -397,9 +397,11 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, 
uint clk_id)
 
switch (clk_id) {
case HCLK_SDMMC:
+   case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
+   case SCLK_EMMC:
con_id = 32;
break;
default:
@@ -423,9 +425,11 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
 
switch (clk_id) {
case HCLK_SDMMC:
+   case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
+   case SCLK_EMMC:
con_id = 32;
break;
default:
@@ -483,6 +487,8 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
+   case SCLK_SDMMC:
+   case SCLK_EMMC:
rate = rk3328_mmc_get_clk(priv->cru, clk->id);
break;
case SCLK_I2C0:
@@ -511,6 +517,8 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong 
rate)
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
+   case SCLK_SDMMC:
+   case SCLK_EMMC:
ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_I2C0:
-- 
2.7.4


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[U-Boot] [PATCH 2/5] rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3036.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3036.c 
b/drivers/clk/rockchip/clk_rk3036.c
index 7e3bf96..d866d0b 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -228,11 +228,13 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, 
uint clk_general_rate,
 
switch (periph) {
case HCLK_EMMC:
+   case SCLK_EMMC:
con = readl(>cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
case HCLK_SDIO:
+   case SCLK_SDIO:
con = readl(>cru_clksel_con[12]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
@@ -265,6 +267,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, 
uint clk_general_rate,
 
switch (periph) {
case HCLK_EMMC:
+   case SCLK_EMMC:
rk_clrsetreg(>cru_clksel_con[12],
 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
@@ -272,6 +275,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, 
uint clk_general_rate,
 (src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
case HCLK_SDIO:
+   case SCLK_SDIO:
rk_clrsetreg(>cru_clksel_con[11],
 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -307,6 +311,7 @@ static ulong rk3036_clk_set_rate(struct clk *clk, ulong 
rate)
case 0 ... 63:
return 0;
case HCLK_EMMC:
+   case SCLK_EMMC:
new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
clk->id, rate);
break;
-- 
2.7.4


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[U-Boot] [PATCH 3/5] rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

[Ziyuan Xu]

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3188.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3188.c 
b/drivers/clk/rockchip/clk_rk3188.c
index d36cf8f..b32491d 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -269,14 +269,17 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, 
uint gclk_rate,
 
switch (periph) {
case HCLK_EMMC:
+   case SCLK_EMMC:
con = readl(>cru_clksel_con[12]);
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
case HCLK_SDMMC:
+   case SCLK_SDMMC:
con = readl(>cru_clksel_con[11]);
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
break;
case HCLK_SDIO:
+   case SCLK_SDIO:
con = readl(>cru_clksel_con[12]);
div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
break;
@@ -298,16 +301,19 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, 
uint gclk_rate,
 
switch (periph) {
case HCLK_EMMC:
+   case SCLK_EMMC:
rk_clrsetreg(>cru_clksel_con[12],
 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 src_clk_div << EMMC_DIV_SHIFT);
break;
case HCLK_SDMMC:
+   case SCLK_SDMMC:
rk_clrsetreg(>cru_clksel_con[11],
 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 src_clk_div << MMC0_DIV_SHIFT);
break;
case HCLK_SDIO:
+   case SCLK_SDIO:
rk_clrsetreg(>cru_clksel_con[12],
 SDIO_DIV_MASK << SDIO_DIV_SHIFT,
 src_clk_div << SDIO_DIV_SHIFT);
@@ -466,6 +472,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
+   case SCLK_EMMC:
+   case SCLK_SDMMC:
+   case SCLK_SDIO:
new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
clk->id);
break;
@@ -505,6 +514,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong 
rate)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
+   case SCLK_EMMC:
+   case SCLK_SDMMC:
+   case SCLK_SDIO:
new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
clk->id, rate);
break;
-- 
2.7.4


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[U-Boot] [PATCH 1/5] mmc: dw_mmc: rockchip: select proper card clock

[Ziyuan Xu]

As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
used for communication between host and card devices. The real bus clock
is ciu, so let's rectify it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/rockchip_dw_mmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index c36eda0..b0e52b0 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -44,7 +44,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host 
*host, uint freq)
 
ret = clk_set_rate(>clk, freq);
if (ret < 0) {
-   debug("%s: err=%d\n", __func__, ret);
+   printf("%s: err=%d\n", __func__, ret);
return ret;
}
 
@@ -109,7 +109,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
if (ret < 0)
return ret;
 #else
-   ret = clk_get_by_index(dev, 0, >clk);
+   ret = clk_get_by_name(dev, "ciu", >clk);
if (ret < 0)
return ret;
 #endif
-- 
2.7.4


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[U-Boot] [PATCH] mmc: drop unnecessary send_status request

[Ziyuan Xu]

It's redundant to send cmd13 after cmd9 whose response is not R1b. The
card devices will not be busy w/ cmd9.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/mmc.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3648950..72fc177 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -,7 +,6 @@ static int mmc_startup(struct mmc *mmc)
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
-   int timeout = 1000;
bool has_parts = false;
bool part_completed;
struct blk_desc *bdesc;
@@ -1167,9 +1166,6 @@ static int mmc_startup(struct mmc *mmc)
 
err = mmc_send_cmd(mmc, , NULL);
 
-   /* Waiting for the ready status */
-   mmc_send_status(mmc, timeout);
-
if (err)
return err;
 
-- 
2.7.4


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Re: [U-Boot] [PATCH] rockchip: rk3288: sdram: fix DDR address range

[Ziyuan Xu]

Hi Simon,


On 2016年09月23日 10:39, Simon Glass wrote:

Hi,

On 4 September 2016 at 19:39, Ziyuan Xu <xzy...@rock-chips.com> wrote:

The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe00~0xff00. Actually, some IP
controller can't address to, so let's limit the available range.

This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe00. So that DMAC didn't work sane.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

No comments on this one?


This patch could fix a bug while booting to kernel, which could be 
reproduce on 4 GB board. I hope someone who has 4 GB board could test it .




Acked-by: Simon Glass <s...@chromium.org>
Tested on firefly-rk3288:
Tested-by: Simon Glass <s...@chromium.org>






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Re: [U-Boot] [PATCH 1/3] mmc: dw_mmc: change the read/write order under fifo mode

[Ziyuan Xu]

hi Simon,


On 2016年09月23日 10:39, Simon Glass wrote:

Hi,

On 7 September 2016 at 21:54, Jaehoon Chung <jh80.ch...@samsung.com> wrote:

On 09/08/2016 12:43 PM, Ziyuan Xu wrote:


On 2016年09月07日 14:50, Jaehoon Chung wrote:

On 09/07/2016 03:14 PM, Ziyuan Xu wrote:

hi Jaehoon,


On 2016年08月30日 17:54, Jaehoon Chung wrote:

Hi Jacob,

On 08/30/2016 02:26 AM, Jacob Chen wrote:

From: "jacob2.chen" <jacob2.c...@rock-chips.com>

The former implement have a bug.
It will cause wrong data reading sometimes.

Could you explain what bug is there?

Signed-off-by: jacob2.chen <jacob2.c...@rock-chips.com>

Could you change from jacob2.chen to your name?


---

drivers/mmc/dw_mmc.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index afc674d..f072739 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,35 +120,37 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
  if (host->fifo_mode && size) {
len = 0;
-if (data->flags == MMC_DATA_READ) {
-if ((dwmci_readl(host, DWMCI_RINTSTS) &
- DWMCI_INTMSK_RXDR)) {
+if (data->flags == MMC_DATA_READ &&
+(mask & DWMCI_INTMSK_RXDR)) {
+while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = (len >> DWMCI_FIFO_SHIFT) &
-DWMCI_FIFO_MASK;
+DWMCI_FIFO_MASK;

What is the status of this patch please?


I have sent patch v2, and Jaehoon applied it. Pls see 
http://patchwork.ozlabs.org/patch/671533/.

Thanks for your attention.



[...]

Regards,
Simon






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Re: [U-Boot] [PATCH] mmc: dw_mmc: push/pop all FIFO data if any data request

[Ziyuan Xu]

hi Jaehoon,


On 2016年09月19日 14:43, Jaehoon Chung wrote:

Hi Ziyuan,

On 09/19/2016 11:16 AM, Ziyuan Xu wrote:

From: "jacob2.chen" <jacob2.c...@rock-chips.com>

As I remembered, I mentioned that changed to real name, not mail ID.
likes "Jacob Chen <jacob2,c...@rock-chips.com>"

If it's right and you're ok, i will change this when i apply this patch.
How about?


Yup, it's ok.



And Next Time, could you add the changelog for Patch Version, plz? :)


I'm sorry about it, I'll bear it in mind, thanks!



Best Regards,
Jaehoon Chung


When DTO interrupt occurred, there are any remaining data still in FIFO
due to RX FIFO threshold is larger than remaining data. It also
causes that dwmmc didn't trigger RXDR interrupt, so is TX.

It's responsibility of driver to read remaining bytes on seeing DTO
interrupt.

Signed-off-by: jacob2.chen <jacob2.c...@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  drivers/mmc/dw_mmc.c | 23 ---
  1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index afc674d..074f86c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,9 +120,9 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
  
  		if (host->fifo_mode && size) {

len = 0;
-   if (data->flags == MMC_DATA_READ) {
-   if ((dwmci_readl(host, DWMCI_RINTSTS) &
-DWMCI_INTMSK_RXDR)) {
+   if (data->flags == MMC_DATA_READ &&
+   (mask & DWMCI_INTMSK_RXDR)) {
+   while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = (len >> DWMCI_FIFO_SHIFT) &
DWMCI_FIFO_MASK;
@@ -130,12 +130,13 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
for (i = 0; i < len; i++)
*buf++ =
dwmci_readl(host, DWMCI_DATA);
-   dwmci_writel(host, DWMCI_RINTSTS,
-DWMCI_INTMSK_RXDR);
+   size = size > len ? (size - len) : 0;
}
-   } else {
-   if ((dwmci_readl(host, DWMCI_RINTSTS) &
-DWMCI_INTMSK_TXDR)) {
+   dwmci_writel(host, DWMCI_RINTSTS,
+DWMCI_INTMSK_RXDR);
+   } else if (data->flags == MMC_DATA_WRITE &&
+  (mask & DWMCI_INTMSK_TXDR)) {
+   while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = fifo_depth - ((len >>
   DWMCI_FIFO_SHIFT) &
@@ -144,11 +145,11 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
for (i = 0; i < len; i++)
dwmci_writel(host, DWMCI_DATA,
 *buf++);
-   dwmci_writel(host, DWMCI_RINTSTS,
-DWMCI_INTMSK_TXDR);
+   size = size > len ? (size - len) : 0;
}
+   dwmci_writel(host, DWMCI_RINTSTS,
+DWMCI_INTMSK_TXDR);
}
-   size = size > len ? (size - len) : 0;
}
  
  		/* Data arrived correctly. */









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[U-Boot] [PATCH] mmc: dw_mmc: push/pop all FIFO data if any data request

[Ziyuan Xu]

From: "jacob2.chen" <jacob2.c...@rock-chips.com>

When DTO interrupt occurred, there are any remaining data still in FIFO
due to RX FIFO threshold is larger than remaining data. It also
causes that dwmmc didn't trigger RXDR interrupt, so is TX.

It's responsibility of driver to read remaining bytes on seeing DTO
interrupt.

Signed-off-by: jacob2.chen <jacob2.c...@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c | 23 ---
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index afc674d..074f86c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,9 +120,9 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
 
if (host->fifo_mode && size) {
len = 0;
-   if (data->flags == MMC_DATA_READ) {
-   if ((dwmci_readl(host, DWMCI_RINTSTS) &
-DWMCI_INTMSK_RXDR)) {
+   if (data->flags == MMC_DATA_READ &&
+   (mask & DWMCI_INTMSK_RXDR)) {
+   while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = (len >> DWMCI_FIFO_SHIFT) &
DWMCI_FIFO_MASK;
@@ -130,12 +130,13 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
for (i = 0; i < len; i++)
*buf++ =
dwmci_readl(host, DWMCI_DATA);
-   dwmci_writel(host, DWMCI_RINTSTS,
-DWMCI_INTMSK_RXDR);
+   size = size > len ? (size - len) : 0;
}
-   } else {
-   if ((dwmci_readl(host, DWMCI_RINTSTS) &
-DWMCI_INTMSK_TXDR)) {
+   dwmci_writel(host, DWMCI_RINTSTS,
+DWMCI_INTMSK_RXDR);
+   } else if (data->flags == MMC_DATA_WRITE &&
+  (mask & DWMCI_INTMSK_TXDR)) {
+   while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = fifo_depth - ((len >>
   DWMCI_FIFO_SHIFT) &
@@ -144,11 +145,11 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
for (i = 0; i < len; i++)
dwmci_writel(host, DWMCI_DATA,
 *buf++);
-   dwmci_writel(host, DWMCI_RINTSTS,
-DWMCI_INTMSK_TXDR);
+   size = size > len ? (size - len) : 0;
}
+   dwmci_writel(host, DWMCI_RINTSTS,
+DWMCI_INTMSK_TXDR);
}
-   size = size > len ? (size - len) : 0;
}
 
/* Data arrived correctly. */
-- 
2.9.2


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Re: [U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Ziyuan Xu]

hi Vagrant,


On 2016年09月11日 03:01, Vagrant Cascadian wrote:

On 2016-09-10, Ziyuan Xu wrote:

On 2016年09月09日 03:28, Vagrant Cascadian wrote:

On 2016-09-08, Kever Yang wrote:

The rk3288 spl size is very close to 32KB while the rk3288 bootrom
has the limitation of maximum size of SPL is 32KB. After apply this
patch, the SPL size will exceed 32KB if we do not enable macro
CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.

With CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y, it fails to boot with no output
on the console.



This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.

Thanks for the patch!

Unfortunately, fails to build the firefly-rk3288 target, using
arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705, applied to
u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:

CC  spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
'conv_of_platdata':
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30: error: 'struct
dtd_rockchip_rk3288_dmc' has no member named 'rockchip_num_channels';
did you mean 'rockchip_noc'?
plat->num_channels = of_plat->rockchip_num_channels;

-   plat->num_channels = of_plat->rockchip_num_channels;
+   plat->num_channels = 2;

firefly-rk3288 deploy CONFIG_OF_PLATDATA,  driver read platform data
from include/generated/dt-structs.h which is generated according to dts
file.
Please try above change.

With this change, it builds, but it hangs at boot:

   U-Boot SPL 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28)
   Trying to boot from MMC1


   U-Boot 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28 +)

   Model: Firefly-RK3288
   DRAM:


Could you help to add DEBUG macro in common.h like:
#indef CONFIG_SPL_BUILD
#define DEBUG
#endif

So that we can figure out where it is.



This is on a firefly with 2GB of ram. I also have one with 4GB of ram,
hence my interest in this patch series!


live well,
   vagrant



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Re: [U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288

[Ziyuan Xu]

hi Vagrant,


On 2016年09月09日 03:28, Vagrant Cascadian wrote:

On 2016-09-08, Kever Yang wrote:

The rk3288 spl size is very close to 32KB while the rk3288 bootrom
has the limitation of maximum size of SPL is 32KB. After apply this
patch, the SPL size will exceed 32KB if we do not enable macro
CONFIG_ROCKCHIP_SPL_BACK_TO_BROM.

I think this patch is usful and should be go upstream other than the
size issue.

This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3.

Thanks for the patch!

Unfortunately, fails to build the firefly-rk3288 target, using
arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705, applied to
u-boot master 01c5075506afcb7a74e0db8600af8979f45881b5:

   CC  spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function
   'conv_of_platdata':
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1042:30: error: 'struct
   dtd_rockchip_rk3288_dmc' has no member named 'rockchip_num_channels';
   did you mean 'rockchip_noc'?
   plat->num_channels = of_plat->rockchip_num_channels;


-   plat->num_channels = of_plat->rockchip_num_channels;
+   plat->num_channels = 2;

firefly-rk3288 deploy CONFIG_OF_PLATDATA,  driver read platform data 
from include/generated/dt-structs.h which is generated according to dts 
file.

Please try above change.

@Kever,

Please fix below.

arch/arm/mach-rockchip/rk3288/sdram_rk3288.c: In function 
‘conv_of_platdata’:
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1035:6: warning: unused 
variable ‘i’ [-Wunused-variable]




   ^~
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c:1035:6: warning: unused
   variable 'i' [-Wunused-variable]
   int i, ret;
   ^
scripts/Makefile.build:280: recipe for target
   'spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o' failed
make[3]: *** [spl/arch/arm/mach-rockchip/rk3288/sdram_rk3288.o] Error 1
scripts/Makefile.build:425: recipe for target
   'spl/arch/arm/mach-rockchip/rk3288' failed
make[2]: *** [spl/arch/arm/mach-rockchip/rk3288] Error 2
scripts/Makefile.spl:292: recipe for target 'spl/arch/arm/mach-rockchip'
   failed
make[1]: *** [spl/arch/arm/mach-rockchip] Error 2
Makefile:1334: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2


live well,
   vagrant



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[U-Boot] [PATCH] rockchip: miniarm: remove eMMC support

[Ziyuan Xu]

The latest rk3288-miniarm board doesn't have eMMC device, so remove it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 arch/arm/dts/rk3288-miniarm.dtsi   | 12 
 board/rockchip/miniarm_rk3288/miniarm-rk3288.c |  8 
 include/configs/miniarm_rk3288.h   |  7 ++-
 3 files changed, 6 insertions(+), 21 deletions(-)

diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
index b889875..ceb4e2b 100644
--- a/arch/arm/dts/rk3288-miniarm.dtsi
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -116,18 +116,6 @@
cpu0-supply = <_cpu>;
 };
 
- {
-   broken-cd;
-   bus-width = <8>;
-   cap-mmc-highspeed;
-   disable-wp;
-   non-removable;
-   num-slots = <1>;
-   pinctrl-names = "default";
-   pinctrl-0 = <_clk _cmd _pwr _bus8>;
-   status = "okay";
-};
-
  {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c 
b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
index aad74ef..79541a3 100644
--- a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
+++ b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
@@ -5,11 +5,3 @@
  */
 
 #include 
-#include 
-
-void board_boot_order(u32 *spl_boot_list)
-{
-   /* eMMC prior to sdcard */
-   spl_boot_list[0] = BOOT_DEVICE_MMC2;
-   spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/include/configs/miniarm_rk3288.h b/include/configs/miniarm_rk3288.h
index 342557f..4f251cc 100644
--- a/include/configs/miniarm_rk3288.h
+++ b/include/configs/miniarm_rk3288.h
@@ -12,8 +12,13 @@
 
 #define CONFIG_SPL_MMC_SUPPORT
 
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0)
+
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
 /* SPL @ 32k for ~36k
  * ENV @ 96k
  * u-boot @ 128K
-- 
2.9.2


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Re: [U-Boot] [PATCH 1/3] mmc: dw_mmc: change the read/write order under fifo mode

[Ziyuan Xu]

On 2016年09月07日 14:50, Jaehoon Chung wrote:

On 09/07/2016 03:14 PM, Ziyuan Xu wrote:

hi Jaehoon,


On 2016年08月30日 17:54, Jaehoon Chung wrote:

Hi Jacob,

On 08/30/2016 02:26 AM, Jacob Chen wrote:

From: "jacob2.chen" <jacob2.c...@rock-chips.com>

The former implement have a bug.
It will cause wrong data reading sometimes.

Could you explain what bug is there?

Signed-off-by: jacob2.chen <jacob2.c...@rock-chips.com>

Could you change from jacob2.chen to your name?


---

   drivers/mmc/dw_mmc.c | 32 +---
   1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index afc674d..f072739 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,35 +120,37 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
 if (host->fifo_mode && size) {
   len = 0;
-if (data->flags == MMC_DATA_READ) {
-if ((dwmci_readl(host, DWMCI_RINTSTS) &
- DWMCI_INTMSK_RXDR)) {
+if (data->flags == MMC_DATA_READ &&
+(mask & DWMCI_INTMSK_RXDR)) {
+while (size) {
   len = dwmci_readl(host, DWMCI_STATUS);
   len = (len >> DWMCI_FIFO_SHIFT) &
-DWMCI_FIFO_MASK;
+DWMCI_FIFO_MASK;

this changing is related with bug?

I just hit this bug on rk3036 board.

This changing is just an indentation, isn't?
It looks like unnecessary modifying.


When DTO interrupt occurred, there are any remaining data still in FIFO due to 
RX FIFO threshold is larger than remaining data. It also causes that dwmmc 
didn't trigger RXDR interrupt.
It's responsibility of driver to read remaining bytes on seeing DTO interrupt. 
So we need rework dwmci_data_transfer w/ pio mode.

Sure, your bug is possible to occur..but my mean is that modified 
DWMCI_FIFO_MASK isn't related with your entire bug.


Okay I see. If I understand correctly, you recommend that set fifo-depth 
to 1, so that host can trigger RXDR interrupt as soon as 1 bytes data 
come in.

I think it's inefficient.



Best Regards,
Jaehoon Chung


   len = min(size, len);
   for (i = 0; i < len; i++)
   *buf++ =
-dwmci_readl(host, DWMCI_DATA);
-dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_RXDR);
+dwmci_readl(host,
+DWMCI_DATA);
+size = size > len ? (size - len) : 0;
   }
-} else {
-if ((dwmci_readl(host, DWMCI_RINTSTS) &
- DWMCI_INTMSK_TXDR)) {
+dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_RXDR);
+} else if (data->flags == MMC_DATA_WRITE &&
+   (mask & DWMCI_INTMSK_TXDR)) {

data->flags == MMC_DATA_WRITE doesn't need..flags are only two..
one is MMC_DATA_READ, otherwise it's MMC_DATA_WRITE.


+while (size) {
   len = dwmci_readl(host, DWMCI_STATUS);
   len = fifo_depth - ((len >>
-   DWMCI_FIFO_SHIFT) &
-   DWMCI_FIFO_MASK);
+ DWMCI_FIFO_SHIFT) &
+DWMCI_FIFO_MASK);

ditto.

Best Regards,
Jaehoon Chung


   len = min(size, len);
   for (i = 0; i < len; i++)
   dwmci_writel(host, DWMCI_DATA,
*buf++);
-dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_TXDR);
+size = size > len ? (size - len) : 0;
   }
+dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_TXDR);
   }
-size = size > len ? (size - len) : 0;
   }
 /* Data arrived correctly. */


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Re: [U-Boot] [PATCH 1/3] mmc: dw_mmc: change the read/write order under fifo mode

[Ziyuan Xu]

hi Jaehoon,


On 2016年08月30日 17:54, Jaehoon Chung wrote:

Hi Jacob,

On 08/30/2016 02:26 AM, Jacob Chen wrote:

From: "jacob2.chen" 

The former implement have a bug.
It will cause wrong data reading sometimes.

Could you explain what bug is there?


Signed-off-by: jacob2.chen 

Could you change from jacob2.chen to your name?


---

  drivers/mmc/dw_mmc.c | 32 +---
  1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index afc674d..f072739 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,35 +120,37 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
  
  		if (host->fifo_mode && size) {

len = 0;
-   if (data->flags == MMC_DATA_READ) {
-   if ((dwmci_readl(host, DWMCI_RINTSTS) &
-DWMCI_INTMSK_RXDR)) {
+   if (data->flags == MMC_DATA_READ &&
+   (mask & DWMCI_INTMSK_RXDR)) {
+   while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = (len >> DWMCI_FIFO_SHIFT) &
-   DWMCI_FIFO_MASK;
+   DWMCI_FIFO_MASK;

this changing is related with bug?


I just hit this bug on rk3036 board.

When DTO interrupt occurred, there are any remaining data still in FIFO 
due to RX FIFO threshold is larger than remaining data. It also causes 
that dwmmc didn't trigger RXDR interrupt.
It's responsibility of driver to read remaining bytes on seeing DTO 
interrupt. So we need rework dwmci_data_transfer w/ pio mode.





len = min(size, len);
for (i = 0; i < len; i++)
*buf++ =
-   dwmci_readl(host, DWMCI_DATA);
-   dwmci_writel(host, DWMCI_RINTSTS,
-DWMCI_INTMSK_RXDR);
+   dwmci_readl(host,
+   DWMCI_DATA);
+   size = size > len ? (size - len) : 0;
}
-   } else {
-   if ((dwmci_readl(host, DWMCI_RINTSTS) &
-DWMCI_INTMSK_TXDR)) {
+   dwmci_writel(host, DWMCI_RINTSTS,
+DWMCI_INTMSK_RXDR);
+   } else if (data->flags == MMC_DATA_WRITE &&
+  (mask & DWMCI_INTMSK_TXDR)) {

data->flags == MMC_DATA_WRITE doesn't need..flags are only two..
one is MMC_DATA_READ, otherwise it's MMC_DATA_WRITE.


+   while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = fifo_depth - ((len >>
-  DWMCI_FIFO_SHIFT) &
-  DWMCI_FIFO_MASK);
+DWMCI_FIFO_SHIFT) &
+   DWMCI_FIFO_MASK);

ditto.

Best Regards,
Jaehoon Chung


len = min(size, len);
for (i = 0; i < len; i++)
dwmci_writel(host, DWMCI_DATA,
 *buf++);
-   dwmci_writel(host, DWMCI_RINTSTS,
-DWMCI_INTMSK_TXDR);
+   size = size > len ? (size - len) : 0;
}
+   dwmci_writel(host, DWMCI_RINTSTS,
+DWMCI_INTMSK_TXDR);
}
-   size = size > len ? (size - len) : 0;
}
  
  		/* Data arrived correctly. */



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[U-Boot] [PATCH] rockchip: rk3288: sdram: fix DDR address range

[Ziyuan Xu]

The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe00~0xff00. Actually, some IP
controller can't address to, so let's limit the available range.

This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe00. So that DMAC didn't work sane.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index cf9ef2e..8020e9c 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -755,10 +755,11 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
}
 
/*
-   * we use the 0x~0xfeff space since 0xff00~0x
-   * is SoC register space (i.e. reserved)
+   * we use the 0x~0xfdff space since 0xff00~0x
+   * is SoC register space (i.e. reserved), and 0xfe00~0xfeff is 
+   * inaccessible for some IP controller.
*/
-   size_mb = min(size_mb, 0xff00 >> 20);
+   size_mb = min(size_mb, 0xfe00 >> 20);
 
return size_mb;
 }
-- 
2.9.2


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Re: [U-Boot] [PATCH 1/3] mmc: dw_mmc: change the read/write order under fifo mode

[Ziyuan Xu]

On 2016年08月30日 21:56, 陈豪 wrote:

Hi jaehoon,


2016-08-30 17:54 GMT+08:00 Jaehoon Chung :

Hi Jacob,

On 08/30/2016 02:26 AM, Jacob Chen wrote:

From: "jacob2.chen" 

The former implement have a bug.
It will cause wrong data reading sometimes.

Could you explain what bug is there?

This bug affects data reading and make board fail to boot.
There will be some errors like,
"Warning - bad CRC, using the default environmen"


It's not cause by mmc device, U-Boot will read env from media device, 
and do CRC checking.



"ERROR: Can 't read GPT header"


Which board do you use? RK3288 use DMA-mode for dw_mmc, not pio. I'm 
interest in it, show me more information.




Actually I am not very familiar with the MMC hardware and i don't know
why former implemen will cause this bug.
I just rewrite it according to the driver in kernel.



Signed-off-by: jacob2.chen 

Could you change from jacob2.chen to your name?


---

  drivers/mmc/dw_mmc.c | 32 +---
  1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index afc674d..f072739 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,35 +120,37 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)

   if (host->fifo_mode && size) {
   len = 0;
- if (data->flags == MMC_DATA_READ) {
- if ((dwmci_readl(host, DWMCI_RINTSTS) &
-  DWMCI_INTMSK_RXDR)) {
+ if (data->flags == MMC_DATA_READ &&
+ (mask & DWMCI_INTMSK_RXDR)) {
+ while (size) {
   len = dwmci_readl(host, DWMCI_STATUS);
   len = (len >> DWMCI_FIFO_SHIFT) &
- DWMCI_FIFO_MASK;
+ DWMCI_FIFO_MASK;

this changing is related with bug?


   len = min(size, len);
   for (i = 0; i < len; i++)
   *buf++ =
- dwmci_readl(host, DWMCI_DATA);
- dwmci_writel(host, DWMCI_RINTSTS,
-  DWMCI_INTMSK_RXDR);
+ dwmci_readl(host,
+ DWMCI_DATA);
+ size = size > len ? (size - len) : 0;
   }
- } else {
- if ((dwmci_readl(host, DWMCI_RINTSTS) &
-  DWMCI_INTMSK_TXDR)) {
+ dwmci_writel(host, DWMCI_RINTSTS,
+  DWMCI_INTMSK_RXDR);
+ } else if (data->flags == MMC_DATA_WRITE &&
+(mask & DWMCI_INTMSK_TXDR)) {

data->flags == MMC_DATA_WRITE doesn't need..flags are only two..
one is MMC_DATA_READ, otherwise it's MMC_DATA_WRITE.

The reason why i write it so strange is that it warning "Too many
leading tabs"


+ while (size) {
   len = dwmci_readl(host, DWMCI_STATUS);
   len = fifo_depth - ((len >>
-DWMCI_FIFO_SHIFT) &
-DWMCI_FIFO_MASK);
+  DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK);

ditto.

Best Regards,
Jaehoon Chung


   len = min(size, len);
   for (i = 0; i < len; i++)
   dwmci_writel(host, DWMCI_DATA,
*buf++);
- dwmci_writel(host, DWMCI_RINTSTS,
-  DWMCI_INTMSK_TXDR);
+ size = size > len ? (size - len) : 0;
   }
+ dwmci_writel(host, DWMCI_RINTSTS,
+  DWMCI_INTMSK_TXDR);
   }
- size = size > len ? (size - len) : 0;
   }

   /* Data arrived correctly. */


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Re: [U-Boot] [PATCH v2 2/2] Enable ROCKCHIP_SPL_BACK_TO_BROM for rock2 board

[Ziyuan Xu]

Hi,


On 2016年08月28日 03:39, Sandy Patterson wrote:

Rock2 has been tested with back to brom feature. The tricky part is that
with this feature the default environment is inside u-boot, and it's
defined for every rk3288 board independetly. So I just changed it for
rock2 here.

Solve by moving environment after u-boot before 1M boundary

Signed-off-by: Sandy Patterson 
---


According to your change, I think your commit message is not match.
Enable ROCKCHIP_SPL_BACK_TO_BROM for rock2 board???



Changes in v2: None

  include/configs/rock2.h | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/configs/rock2.h b/include/configs/rock2.h
index ee924c3..946367f 100644
--- a/include/configs/rock2.h
+++ b/include/configs/rock2.h
@@ -16,11 +16,11 @@
  
  #define CONFIG_ENV_IS_IN_MMC

  #define CONFIG_SYS_MMC_ENV_DEV 0
-/* SPL @ 32k for ~36k
- * ENV @ 96k
- * u-boot @ 128K
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
   */
-#define CONFIG_ENV_OFFSET (96 * 1024)
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
  
  #define CONFIG_SYS_WHITE_ON_BLACK

  #define CONFIG_CONSOLE_SCROLL_LINES   10



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Re: [U-Boot] [PATCH v2 1/2] Disable SPL_MMC_SUPPORT if ROCKCHIP_SPL_BACK_TO_BROM is enabled.

[Ziyuan Xu]

On 2016年08月28日 03:39, Sandy Patterson wrote:

Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled.

Signed-off-by: Sandy Patterson <apatter...@sightlogix.com>


Acked-by: Ziyuan Xu <xzy...@rock-chips.com>


---

Changes in v2:
  - Rebase after "Kconfig: Move CONFIG_SPL_..._SUPPORT to Kconfig."
  - Remove all the refactoring in the configs.
  - Split enabling featuring in rock2 into separate commit.




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[U-Boot] [RFC PATCH] rockchip: rk3288: skip lowlevel_init process

[Ziyuan Xu]

lowlevel_init() is never needed for rk3288, so drop it.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>

---

 arch/arm/mach-rockchip/board.c| 4 
 arch/arm/mach-rockchip/rk3288-board-spl.c | 4 
 include/configs/rk3288_common.h   | 1 +
 3 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index bec756d..6c36bf9 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -81,10 +81,6 @@ void enable_caches(void)
 }
 #endif
 
-void lowlevel_init(void)
-{
-}
-
 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
 #include 
 #include 
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index e0d92a6..ae509ff 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -280,7 +280,3 @@ err:
/* No way to report error here */
hang();
 }
-
-void lowlevel_init(void)
-{
-}
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index d3d4c68..e909ef9 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -11,6 +11,7 @@
 
 #include 
 
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NR_DRAM_BANKS   1
 #define CONFIG_ENV_SIZE0x2000
-- 
2.9.2


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Re: [U-Boot] *** Your dtc is too old, please upgrade to dtc 1.4 or newer make: *** [checkdtc] Error 1

[Ziyuan Xu]

On 2016年08月26日 13:45, pc.ramachandra wrote:

Hai,
I am running u-boot time DTC is old is coming, Actually i am upgraded my
system Just know once again same problem coming i think DTC old means Device
tree Compiler old:
*** Your dtc is too old, please upgrade to dtc 1.4 or newer make: ***
[checkdtc] Error 1


If you play on ubuntu, try apt-get install device-tree- compiler



Thanking you



--
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[U-Boot] [PATCH] README: add cmd directory description

[Ziyuan Xu]

All of the command files have moved to cmd directory, add description to
Directory Hierarchy.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 README | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README b/README
index 30d7ee3..f41a6af 100644
--- a/README
+++ b/README
@@ -151,6 +151,7 @@ Directory Hierarchy:
   /x86 Files generic to x86 architecture
 /api   Machine/arch independent API for external apps
 /board Board dependent files
+/cmd   U-Boot commands functions
 /commonMisc architecture independent functions
 /configs   Board default configuration files
 /disk  Code for disk drive partition handling
-- 
2.9.2


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Re: [U-Boot] [PATCH] rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabled

[Ziyuan Xu]

Acked-by: Ziyuan Xu <xzy...@rock-chips.com>


On 2016年08月11日 19:08, Sandy Patterson wrote:


On Wed, Aug 10, 2016 at 11:01 PM, Ziyuan Xu <xzy...@rock-chips.com 
<mailto:xzy...@rock-chips.com>> wrote:




On 2016年08月10日 22:21, Sandy Patterson wrote:

Move back_to_bootrom() call later in SPL init so that the
console is
initialized and printouts happen.

Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is
no console
output from the SPL init stages.

I wasn't sure exactly where this should happen, so if we are
set to do
run spl_board_init, then go back to bootrom there after
preloader_console_init(). Otherwise fall back to old behavior
of doing
it in board_init_f.

In fact, ROCKCHIP_SPL_BACK_TO_BROM's aim is to reduce SPL's size,
and we can undef CONFIG_SPL_MMC_SUPPORT and other thing.
The SPL only in charge of DDR initialization, so that boot rom
could load u-boot to RAM.
If you really need something output, you can enable EARYLY_UART in
rk3288-board-spl.c:board_init_f().
But the above is my own understanding.

EARLY_UART is a good tool, but this patch just fixes printouts. It's 
not enabling or disabling any code compilation. The console init and 
version information code is there. I just move the back_to_bootrom 
call later in the SPL if that later point exits. You can still 
disable CONFIG_SPL_BOARD_INIT and it will fall back to calling the 
bootrom earlier.


We don't actually need that much space. We chose to use BOOT_TO_BROM 
instead of disabling the console in SPL.


We disable CONFIG_SPL_MMC_SUPPORT in our production system within the 
rock2.h file if CONFIG_SPL_MMC_SUPPORT. I'll submit another patch for 
that. I think if boootrom is used then the mmc should be removed from 
spl. I'm not really sure how the config system is supposed to work in 
this case.



Signed-off-by: Sandy Patterson <apatter...@sightlogix.com
<mailto:apatter...@sightlogix.com>>
---

  arch/arm/mach-rockchip/rk3288-board-spl.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index e0d92a6..0c2d525 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -206,7 +206,7 @@ void board_init_f(ulong dummy)
debug("DRAM init failed: %d\n", ret);
return;
}
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) &&
!defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
  #endif
  }
@@ -273,6 +273,9 @@ void spl_board_init(void)
}
preloader_console_init();
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+   back_to_bootrom();
+#endif
return;
  err:
printf("spl_board_init: Error %d\n", ret);







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[U-Boot] [PATCH] rockchip: use dummy byte only enable OF_PLATDATA

[Ziyuan Xu]

Add a condition to determine the rk3288_sdram_channel size.

This patch fixes read sdram_channel property failed from DT on rk3288
boards, which not enable OF_PLATDATA.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/sdram.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h 
b/arch/arm/include/asm/arch-rockchip/sdram.h
index e08e28f..82c3d07 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -24,12 +24,16 @@ struct rk3288_sdram_channel {
u8 row_3_4;
u8 cs0_row;
u8 cs1_row;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
/*
 * For of-platdata, which would otherwise convert this into two
 * byte-swapped integers. With a size of 9 bytes, this struct will
 * appear in of-platdata as a byte array.
+*
+* If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
 */
u8 dummy;
+#endif
 };
 
 struct rk3288_sdram_pctl_timing {
-- 
2.9.2


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Re: [U-Boot] disabling mmc in spl when booting using bootrom

[Ziyuan Xu]

On 2016年08月11日 19:31, Sandy Patterson wrote:

Simon,

I am trying to format a patch to disable MMC in the SPL if booting 
main u-boot using BOOTROM, therefore the SPL MMC isn't needed.


Is the best solution to wrap every header file (rock2.h 
firefly-rk3288.h, etc) with ifdefs on the BACK_TO_BROM define? Or 
would it be better to move the SPL MMC define into rk3288-common.h and 
just have chromebook_jerry undef it like it does the SPL GPIO code.


With that change, enabling BOOT_TO_BROM shrinks the spl from 32K to 23K.
Note that, firefly-rk3288 use OF_PLATDATA, we will use 
u-boot-spl-no-dtb.bin instead of u-boot-spl-dtb.bin, and the size of 
u-boot-spl-no-dtb.bin is almost 23K.


@Simon, I think we will update doc/README.rockchip if you insist on 
OF_PLATDATA for firefly-rk3288. we no longer use u-boot-spl-dtb.bin.:-)


Sandy



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Re: [U-Boot] disabling mmc in spl when booting using bootrom

[Ziyuan Xu]

On 2016年08月11日 19:39, Sandy Patterson wrote:


On Thu, Aug 11, 2016 at 7:35 AM, Ziyuan Xu <xzy...@rock-chips.com 
<mailto:xzy...@rock-chips.com>> wrote:




On 2016年08月11日 19:31, Sandy Patterson wrote:

Simon,

I am trying to format a patch to disable MMC in the SPL if
booting main u-boot using BOOTROM, therefore the SPL MMC isn't
needed.

Is the best solution to wrap every header file (rock2.h
firefly-rk3288.h, etc) with ifdefs on the BACK_TO_BROM define?
Or would it be better to move the SPL MMC define into
rk3288-common.h and just have chromebook_jerry undef it like
it does the SPL GPIO code.

With that change, enabling BOOT_TO_BROM shrinks the spl from
32K to 23K.

Note that, firefly-rk3288 use OF_PLATDATA, we will use
u-boot-spl-no-dtb.bin instead of u-boot-spl-dtb.bin, and the size
of u-boot-spl-no-dtb.bin is almost 23K.


The patch would apply if OF_PLATDATA is used too (Although I haven't 
tested it). It would just shrink the SPL more right because you don't 
need the MMC driver. I wasn't planning to change any of the defconfigs.

Okay, I'll have no objection to your doing it.



@Simon, I think we will update doc/README.rockchip if you insist
on OF_PLATDATA for firefly-rk3288. we no longer use
u-boot-spl-dtb.bin.:-)


Sandy







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Re: [U-Boot] [PATCH] rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabled

[Ziyuan Xu]

On 2016年08月10日 22:21, Sandy Patterson wrote:

Move back_to_bootrom() call later in SPL init so that the console is
initialized and printouts happen.

Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console
output from the SPL init stages.

I wasn't sure exactly where this should happen, so if we are set to do
run spl_board_init, then go back to bootrom there after
preloader_console_init(). Otherwise fall back to old behavior of doing
it in board_init_f.
In fact, ROCKCHIP_SPL_BACK_TO_BROM's aim is to reduce SPL's size, and we 
can undef CONFIG_SPL_MMC_SUPPORT and other thing.
The SPL only in charge of DDR initialization, so that boot rom could 
load u-boot to RAM.
If you really need something output, you can enable EARYLY_UART in 
rk3288-board-spl.c:board_init_f().

But the above is my own understanding.


Signed-off-by: Sandy Patterson 
---

  arch/arm/mach-rockchip/rk3288-board-spl.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index e0d92a6..0c2d525 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -206,7 +206,7 @@ void board_init_f(ulong dummy)
debug("DRAM init failed: %d\n", ret);
return;
}
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && 
!defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
  #endif
  }
@@ -273,6 +273,9 @@ void spl_board_init(void)
}
  
  	preloader_console_init();

+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+   back_to_bootrom();
+#endif
return;
  err:
printf("spl_board_init: Error %d\n", ret);



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Re: [U-Boot] [PATCH v2 3/3] CONFIG_EFI_LOADER breaks rock2 kernel loading

[Ziyuan Xu]

Hi Simon,

I think you can drop this patch due to it fixes by a78cd86 - ARM: Rework 
and correct barrier which Tom had merge it into u-boot/master.


On 2016年08月09日 05:43, Simon Glass wrote:

Hi Sandy,

On 22 July 2016 at 08:40, Sandy Patterson  wrote:

The problem seems to be invalidate_icache_all() inside the runtime.
This patch just disables EFI_LOADER for rock2 board.

Signed-off-by: Sandy Patterson 
---

  configs/rock2_defconfig | 1 +
  1 file changed, 1 insertion(+)

Can you please give me an update on these patches? Did you discover
the root cause? What patches do you think need to be applied for this
release. I'd like to get a few more test reports too if possible.

Regards,
Simon






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Re: [U-Boot] [PATCH] ARM: Rework and correct barrier definitions

[Ziyuan Xu]

Hi Tom,


On 2016年08月02日 08:39, Tom Rini wrote:

On Tue, Aug 02, 2016 at 08:37:19AM +0800, Ziyuan Xu wrote:

Hi Tom,


On 2016年08月02日 06:54, Tom Rini wrote:

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First,  now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.

Reported-by: Ziyuan Xu <xzy...@rock-chips.com>
Reported-by: Sandy Patterson <apatter...@sightlogix.com>
Signed-off-by: Tom Rini <tr...@konsulko.com>

Great, this rework is similar to linux kernel, and it's better than
what I did.  Moreover, it works for my rk3288 boards.
Tested-by: Ziyuan Xu <xzy...@rock-chips.com>

But please can you keep things in alpha order? See below.

Sure, I'll re-work when applying or reposting if there's any other
comments.  Thanks!

I wonder does this patch could be applied into the 2016.9 release version?
It's imperative for rockchip rk3288.:-)





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[U-Boot] [RESEND PATCH 1/2] rockchip: add basic partitions support for rk3288

[Ziyuan Xu]

For compatibility with distro boot, fastboot, and mount the mmc deivce
to PC via usb mass storage feature, GPT partitions are essential.

You should write the partitions to mmc device prior to use above
feature.

=> gpt write mmc 1 $partitions
GPT successfully written to block device!
success!

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 include/configs/rk3288_common.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 814116c..fa37335 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -113,6 +113,12 @@
"kernel_addr_r=0x0200\0" \
"ramdisk_addr_r=0x0400\0"
 
+#define CONFIG_RANDOM_UUID
+#define PARTS_DEFAULT \
+   "uuid_disk=${uuid_gpt_disk};" \
+   "name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
+   "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+
 /* First try to boot from SD (index 0), then eMMC (index 1 */
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
@@ -125,6 +131,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x1fff\0" \
"initrd_high=0x1fff\0" \
+   "partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
-- 
2.9.2


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[U-Boot] [RESEND PATCH 2/2] rockchip: add usb mass storage feature support for rk3288

[Ziyuan Xu]

Enable ums feature for rk3288 boards, so that we can mount the mmc
device to PC.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 include/configs/rk3288_common.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index fa37335..d3d4c68 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -96,6 +96,10 @@
 #define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE   0x0800
 
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER  "Rockchip"
 #define CONFIG_G_DNL_VENDOR_NUM0x2207
-- 
2.9.2


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[U-Boot] [PATCH 2/2] rockchip: add usb mass storage feature support for rk3288

[Ziyuan Xu]

Enable ums feature for rk3288 boards, so that we can mount the mmc
device to PC.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 include/common.h| 4 +++-
 include/configs/rk3288_common.h | 4 
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/common.h b/include/common.h
index e9f0dea..1866cf3 100644
--- a/include/common.h
+++ b/include/common.h
@@ -9,7 +9,9 @@
 #define __COMMON_H_1
 
 #ifndef __ASSEMBLY__   /* put C only stuff in this section */
-
+#ifndef CONFIG_SPL_BUILD
+#define DEBUG
+#endif
 typedef unsigned char  uchar;
 typedef volatile unsigned long vu_long;
 typedef volatile unsigned short vu_short;
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index fa37335..d3d4c68 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -96,6 +96,10 @@
 #define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE   0x0800
 
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER  "Rockchip"
 #define CONFIG_G_DNL_VENDOR_NUM0x2207
-- 
2.9.2


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[U-Boot] [PATCH 1/2] rockchip: add basic partitions support for rk3288

[Ziyuan Xu]

For compatibility with distro boot, fastboot, and mount the mmc deivce
to PC via usb mass storage feature, GPT partitions are essential.

You should write the partitions to mmc device prior to use above
feature.

=> gpt write mmc 1 $partitions
GPT successfully written to block device!
success!

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 include/configs/rk3288_common.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 814116c..fa37335 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -113,6 +113,12 @@
"kernel_addr_r=0x0200\0" \
"ramdisk_addr_r=0x0400\0"
 
+#define CONFIG_RANDOM_UUID
+#define PARTS_DEFAULT \
+   "uuid_disk=${uuid_gpt_disk};" \
+   "name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
+   "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+
 /* First try to boot from SD (index 0), then eMMC (index 1 */
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
@@ -125,6 +131,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x1fff\0" \
"initrd_high=0x1fff\0" \
+   "partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
-- 
2.9.2


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Re: [U-Boot] [PATCH] configs: rk3399: add gpt and fs support

[Ziyuan Xu]

On 2016年08月02日 10:56, Ziyuan Xu wrote:

Hi kever,


On 2016年08月02日 10:29, Kever Yang wrote:

To compatible with distro boot, we need to add gpt and fs support,
including gpt table and vfat, ext2, ext4 support.

Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---

  include/configs/rk3399_common.h | 19 +++
  1 file changed, 19 insertions(+)

diff --git a/include/configs/rk3399_common.h 
b/include/configs/rk3399_common.h

index a9c9d29..12327d5 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -35,6 +35,15 @@
  #define CONFIG_BOUNCE_BUFFER
  #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ2
  +#define CONFIG_DOS_PARTITION
CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in 
config_distro_defaults.h, you not need to define it.

See 77337c1 rockchip: remove the duplicated macro config

+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_PART
+
+/*  EXT4 FS */
+#define CONFIG_FS_EXT4
  #define CONFIG_FAT_WRITE
/* RAW SD card / eMMC locations. */
@@ -60,6 +69,14 @@
  "kernel_addr_r=0x0200\0" \
  "ramdisk_addr_r=0x0400\0"
  +#define CONFIG_CMD_GPT
+#define CONFIG_RANDOM_UUID
+#define CONFIG_EFI_PARTITION
+#define PARTS_DEFAULT \
+"uuid_disk=${uuid_gpt_disk};" \
+"name=boot,start=16M,size=32M,bootable;" \
+"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};" \

I think partitions table should be defined in includes/configs/${board}.h.

miss '\0'.
should be  "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \

+
  /* First try to boot from SD (index 0), then eMMC (index 1) */
  #define BOOT_TARGET_DEVICES(func) \
  func(MMC, mmc, 0) \
@@ -67,6 +84,8 @@
#include 
  #define CONFIG_EXTRA_ENV_SETTINGS \
+ENV_MEM_LAYOUT_SETTINGS \
+"partitions=" PARTS_DEFAULT \
  BOOTENV
#endif





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Re: [U-Boot] [PATCH] configs: rk3399: add gpt and fs support

[Ziyuan Xu]

On 2016年08月02日 10:56, Ziyuan Xu wrote:

Hi kever,


On 2016年08月02日 10:29, Kever Yang wrote:

To compatible with distro boot, we need to add gpt and fs support,
including gpt table and vfat, ext2, ext4 support.

Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---

  include/configs/rk3399_common.h | 19 +++
  1 file changed, 19 insertions(+)

diff --git a/include/configs/rk3399_common.h 
b/include/configs/rk3399_common.h

index a9c9d29..12327d5 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -35,6 +35,15 @@
  #define CONFIG_BOUNCE_BUFFER
  #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ2
  +#define CONFIG_DOS_PARTITION
CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in 
config_distro_defaults.h, you not need to define it.

See 77337c1 rockchip: remove the duplicated macro config

+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_PART
+
+/*  EXT4 FS */
+#define CONFIG_FS_EXT4
  #define CONFIG_FAT_WRITE
/* RAW SD card / eMMC locations. */
@@ -60,6 +69,14 @@
  "kernel_addr_r=0x0200\0" \
  "ramdisk_addr_r=0x0400\0"
  +#define CONFIG_CMD_GPT
+#define CONFIG_RANDOM_UUID
+#define CONFIG_EFI_PARTITION
+#define PARTS_DEFAULT \
+"uuid_disk=${uuid_gpt_disk};" \
+"name=boot,start=16M,size=32M,bootable;" \
+"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};" \

I think partitions table should be defined in includes/configs/${board}.h

miss '\0'.
should be  "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \

+
  /* First try to boot from SD (index 0), then eMMC (index 1) */
  #define BOOT_TARGET_DEVICES(func) \
  func(MMC, mmc, 0) \
@@ -67,6 +84,8 @@
#include 
  #define CONFIG_EXTRA_ENV_SETTINGS \
+ENV_MEM_LAYOUT_SETTINGS \
+"partitions=" PARTS_DEFAULT \
  BOOTENV
#endif





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Re: [U-Boot] [PATCH] configs: rk3399: add gpt and fs support

[Ziyuan Xu]

Hi kever,


On 2016年08月02日 10:29, Kever Yang wrote:

To compatible with distro boot, we need to add gpt and fs support,
including gpt table and vfat, ext2, ext4 support.

Signed-off-by: Kever Yang 
---

  include/configs/rk3399_common.h | 19 +++
  1 file changed, 19 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index a9c9d29..12327d5 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -35,6 +35,15 @@
  #define CONFIG_BOUNCE_BUFFER
  #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ2
  
+#define CONFIG_DOS_PARTITION
CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in 
config_distro_defaults.h, you not need to define it.

See 77337c1 rockchip: remove the duplicated macro config

+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_PART
+
+/*  EXT4 FS */
+#define CONFIG_FS_EXT4
  #define CONFIG_FAT_WRITE
  
  /* RAW SD card / eMMC locations. */

@@ -60,6 +69,14 @@
"kernel_addr_r=0x0200\0" \
"ramdisk_addr_r=0x0400\0"
  
+#define CONFIG_CMD_GPT

+#define CONFIG_RANDOM_UUID
+#define CONFIG_EFI_PARTITION
+#define PARTS_DEFAULT \
+   "uuid_disk=${uuid_gpt_disk};" \
+   "name=boot,start=16M,size=32M,bootable;" \
+   "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};" \

miss '\0'.
should be  "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \

+
  /* First try to boot from SD (index 0), then eMMC (index 1) */
  #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
@@ -67,6 +84,8 @@
  
  #include 

  #define CONFIG_EXTRA_ENV_SETTINGS \
+   ENV_MEM_LAYOUT_SETTINGS \
+   "partitions=" PARTS_DEFAULT \
BOOTENV
  
  #endif



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Re: [U-Boot] [PATCH] ARM: Rework and correct barrier definitions

[Ziyuan Xu]

Hi Tom,


On 2016年08月02日 06:54, Tom Rini wrote:

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First,  now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.

Reported-by: Ziyuan Xu <xzy...@rock-chips.com>
Reported-by: Sandy Patterson <apatter...@sightlogix.com>
Signed-off-by: Tom Rini <tr...@konsulko.com>
Great, this rework is similar to linux kernel, and it's better than what 
I did.  Moreover, it works for my rk3288 boards.

Tested-by: Ziyuan Xu <xzy...@rock-chips.com>

But please can you keep things in alpha order? See below.

---
Good work on figuring this out guys.  Please test and ack this on your
hardware as well.  I've given this a boot test on one of my platforms
and built it for all ARM targets.
---
  arch/arm/Makefile  |  8 
  arch/arm/cpu/armv7/cache_v7.c  | 10 +-
  arch/arm/cpu/armv7/psci-common.c   |  2 +-
  arch/arm/cpu/armv7/sunxi/psci.c| 12 ++--
  arch/arm/include/asm/barriers.h| 11 +--
  arch/arm/include/asm/io.h  |  4 ++--
  arch/arm/include/asm/system.h  |  8 +---
  arch/arm/lib/Makefile  |  5 -
  arch/arm/mach-exynos/include/mach/system.h | 10 --
  arch/arm/mach-sunxi/dram_helpers.c |  2 +-
  arch/arm/mach-tegra/tegra20/Makefile   |  3 ++-
  11 files changed, 35 insertions(+), 40 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6a07cd1..82f2fd0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -20,6 +20,14 @@ arch-$(CONFIG_CPU_V7)=$(call cc-option, 
-march=armv7-a, \
 $(call cc-option, -march=armv7, -march=armv5))
  arch-$(CONFIG_ARM64)  =-march=armv8-a
  
+# On Tegra systems we must build SPL for the armv4 core on the device

+# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+arch-y += -D__LINUX_ARM_ARCH__=4
+else
+arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
  # Evaluate arch cc-option calls now
  arch-y := $(arch-y)
  
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c

index 52f1856..c4bbcc3 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -75,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 
range_op)
}
  
  	/* DSB to make sure the operation is complete */

-   DSB;
+   dsb();
  }
  
  /* Invalidate TLB */

@@ -88,9 +88,9 @@ static void v7_inval_tlb(void)
/* Invalidate entire instruction TLB */
asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
-   DSB;
+   dsb();
/* Full system ISB - make sure the instruction stream sees it */
-   ISB;
+   isb();
  }
  
  void invalidate_dcache_all(void)

@@ -194,10 +194,10 @@ void invalidate_icache_all(void)
asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
  
  	/* Full system DSB - make sure that the invalidation is complete */

-   DSB;
+   dsb();
  
  	/* ISB - make sure the instruction stream sees it */

-   ISB;
+   isb();
  }
  #else
  void invalidate_icache_all(void)
diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c
index d14b693..8cb4107 100644
--- a/arch/arm/cpu/armv7/psci-common.c
+++ b/arch/arm/cpu/armv7/psci-common.c
@@ -29,7 +29,7 @@ static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] 
__secure_data = { 0 };
  void __secure psci_save_target_pc(int cpu, u32 pc)
  {
psci_target_pc[cpu] = pc;
-   DSB;
+   dsb();
  }
  
  u32 __secure psci_get_target_pc(int cpu)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 7ac8406..766b8c7 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms)
u32 reg = ONE_MS 

Re: [U-Boot] [PATCH] MAINTAINERS, git-mailrc: Update the mmc maintainer

[Ziyuan Xu]

Hi Jaehoon,

On 2016年08月01日 11:35, Jaehoon Chung wrote:

Update the mmc maintainer from Pantelis to me.

Signed-off-by: Jaehoon Chung 
---

Congratulations!:-)

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Re: [U-Boot] [PATCH] rockchip: rockchip, sdram-channel 0xff fix remaining dts

[Ziyuan Xu]

Hi Simon,


On 2016年08月01日 10:21, Simon Glass wrote:

Hi Ziyuan,

On 31 July 2016 at 20:13, Ziyuan Xu <xzy...@rock-chips.com> wrote:

Hi Simon,


On 2016年08月01日 09:51, Simon Glass wrote:

Hi Sandy,

On 28 July 2016 at 07:49, Sandy Patterson <apatter...@sightlogix.com>
wrote:

Add an extra byte so that this data is not byteswapped.

Signed-off-by: Sandy Patterson <apatter...@sightlogix.com>
---

   arch/arm/dts/rk3288-rock2-square.dts | 2 +-
   arch/arm/dts/rk3288-veyron.dtsi  | 2 +-
   2 files changed, 2 insertions(+), 2 deletions(-)

Acked-by: Simon Glass <s...@chromium.org>

Do these board use OF_PLATDATA? I thought not.

Yes, only firefly-rk3288 board use OF_PLATDATA. But driver get
rk3288_sdram_channel via fdtdec_get_byte_array with the size which is
sizeof(struct rk3288_sdram_channel).
In commit 9ca7e67 rockchip: Update the sdram-channel property to support
of-platdata, you add dummy element in struct rk3288_sdram_channel and size
was changed to 9.
Without this fix, driver get rk3288_sdram_channel failed.

Maybe add CONFIG_IS_ENABLED(OF_PLATDATA) for distinction is better, how
about?

struct rk3288_sdram_channel {
 u8 rank;
 u8 col;
 u8 bk;
 u8 bw;
 u8 dbw;
 u8 row_3_4;
 u8 cs0_row;
 u8 cs1_row;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
 /*
  * For of-platdata, which would otherwise convert this into two
  * byte-swapped integers. With a size of 9 bytes, this struct will
  * appear in of-platdata as a byte array.
  */
 u8 dummy;
#endif
};



Yes, but I'm happy with either solution. Your one may be a little
easier to understand, but if someone switches a board over to
OF_PLATDATA then it will be confusing... Please let me know which you
prefer.
OF_PLATDATA is used to reduce the size of the SPL, right? In most cases, 
some rk3288 boards use OF_LIBFDT. If OF_PLATDATA is really required, I 
think your comment is very clear.

I perfer my above opinion? :-)

Regards,
Simon






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Re: [U-Boot] [PATCH] rockchip: rockchip, sdram-channel 0xff fix remaining dts

[Ziyuan Xu]

Hi Simon,


On 2016年08月01日 09:51, Simon Glass wrote:

Hi Sandy,

On 28 July 2016 at 07:49, Sandy Patterson  wrote:

Add an extra byte so that this data is not byteswapped.

Signed-off-by: Sandy Patterson 
---

  arch/arm/dts/rk3288-rock2-square.dts | 2 +-
  arch/arm/dts/rk3288-veyron.dtsi  | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

Acked-by: Simon Glass 

Do these board use OF_PLATDATA? I thought not.
Yes, only firefly-rk3288 board use OF_PLATDATA. But driver get 
rk3288_sdram_channel via fdtdec_get_byte_array with the size which is  
sizeof(struct rk3288_sdram_channel).
In commit 9ca7e67 rockchip: Update the sdram-channel property to support 
of-platdata, you add dummy element in struct rk3288_sdram_channel and 
size was changed to 9.

Without this fix, driver get rk3288_sdram_channel failed.

Maybe add CONFIG_IS_ENABLED(OF_PLATDATA) for distinction is better, how 
about?


struct rk3288_sdram_channel {
u8 rank;
u8 col;
u8 bk;
u8 bw;
u8 dbw;
u8 row_3_4;
u8 cs0_row;
u8 cs1_row;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/*
 * For of-platdata, which would otherwise convert this into two
 * byte-swapped integers. With a size of 9 bytes, this struct will
 * appear in of-platdata as a byte array.
 */
u8 dummy;
#endif
};



diff --git a/arch/arm/dts/rk3288-rock2-square.dts 
b/arch/arm/dts/rk3288-rock2-square.dts
index 34073c9..2c30355 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -192,7 +192,7 @@
 0x5 0x0>;
 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 0xa60 0x40 0x10 0x0>;
-   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 
0xff>;
 rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
  };

diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 421d212..d9d5187 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -253,7 +253,7 @@
 0x5 0x0>;
 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 0xa60 0x40 0x10 0x0>;
-   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 
0xff>;
 rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
  };

--
1.9.1


Regards,
Simon
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Re: [U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

On 2016年07月31日 22:27, Tom Rini wrote:

On Sun, Jul 31, 2016 at 11:59:19AM +0800, Ziyuan Xu wrote:

Hi Tom,


On 2016年07月29日 09:12, Tom Rini wrote:

On Fri, Jul 29, 2016 at 09:06:29AM +0800, Ziyuan Xu wrote:

Hi Tom,

On 2016年07月29日 08:34, Tom Rini wrote:

On Fri, Jul 29, 2016 at 07:34:09AM +0800, Ziyuan Xu wrote:

Hi Tom,

On 2016年07月29日 06:15, Tom Rini wrote:

On Thu, Jul 28, 2016 at 07:03:17PM +0800, Chen-Yu Tsai wrote:

Hi,

On Thu, Jul 28, 2016 at 6:13 PM, Ziyuan Xu <xzy...@rock-chips.com> wrote:

For ARMv7-A architecture, the valid ISB instruction is asm volatile("isb").

This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
ramdisk start = 0x, ramdisk end = 0x
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS

Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/include/asm/system.h | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..12d4ba0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -227,13 +227,15 @@ void __noreturn psci_system_reset(bool smc);
   */
  void save_boot_params_ret(void);

-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
  #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

  #ifdef __ARM_ARCH_7A__
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
  #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  #else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
  #define wfi()
  #endif


arch/arm/include/asm/barriers.h already has a proper set of
ISB/DSB macros. Please consider using those instead.

Please fix arch/arm/include/asm/system.h to use the macros found in
barriers.h rather than have their own versions.  Thanks!

If I understand correctly, I can change into as bellow:
#define isb() ISB
How about it?

Well, I'd rather not have ISB and isb, just ISB, which means we might
have to fix other places too.  If that starts looking too huge, we can
do this in steps and just do what you suggested for now and for next
release move everything over.

As I mentioned before, arch/arm/include/asm/barriers.h defined ISB
macro.  If I only want to fix the issue which I hit on rk3288 board,
I just use ISB in arch/arm/include/asm/system.h::set_cr() instead of
isb(). But isb() had been invoked in some places.

I can't verify integrallty after all revision, it involve some
boards and feature. But this does fix for rk3288, if you agree with
me, could you apply it provisionally?:-)

I would really like to try and fix the other possibly latent issues that
we have by not calling a real ISB.  Please try moving towards all places
that need an isb calling the correct one from barriers.h and giving it a
spin on the hardware you have available.

I used ISB instead of isb(), everything works sane on my rockchip
rk3288 boards.:-)
Will you send a patch to fix it and other possibly latent issues? Or
apply this temporarily?

Please send a patch of all of the changes you did, thanks!
Tom, it's impracticable only use ISB for all situation instead of isb(). 
There're two isb() invocation in drivers/ddr/fsl/fsl_ddr_gen4.c, and not 
only used on ARM architecture board, but also powerpc. See below:


arch/powerpc/include/asm/config_mpc85xx.h:769:#define 
CONFIG_SYS_FSL_DDRC_GEN4
arch/powerpc/include/asm/config_mpc85xx.h:822:#define 
CONFIG_SYS_FSL_DDRC_GEN4
arch/powerpc/include/asm/config_mpc85xx.h:955: 
!defined(CONFIG_SYS_FSL_DDRC_GEN4)
arch/arm/include/asm/arch-ls102xa/config.h:100:#define 
CONFIG_SYS_FSL_DDRC_GEN4
arch/arm/include/asm/arch-fsl-layerscape/config.h:13:#define 
CONFIG_SYS_FSL_DDRC_GEN4


If you insist on ISB only, we have to differentiate arch via 
CONFIG_SYS_ARCH, seems twisted.

How about it?
#define isb() ISB





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[U-Boot] [PATCH v2] rockchip: add support for rk3288 miniarm board

[Ziyuan Xu]

From: Xu Ziyuan <xzy...@rock-chips.com>

Miniarm is a rockchip rk3288 based development board, which has lots of
interface such as HDMI, USB, micro-SD card, Audio etc.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---

Changes in v2:
- Sort soemthing in alpha order

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3288-miniarm.dts|  61 +++
 arch/arm/dts/rk3288-miniarm.dtsi   | 533 +
 arch/arm/mach-rockchip/rk3288/Kconfig  |  14 +-
 board/rockchip/miniarm_rk3288/Kconfig  |  15 +
 board/rockchip/miniarm_rk3288/MAINTAINERS  |   6 +
 board/rockchip/miniarm_rk3288/Makefile |   7 +
 board/rockchip/miniarm_rk3288/miniarm-rk3288.c |  15 +
 configs/miniarm-rk3288_defconfig   |  65 +++
 doc/README.rockchip|   9 +-
 include/configs/miniarm_rk3288.h   |  26 ++
 11 files changed, 746 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/dts/rk3288-miniarm.dts
 create mode 100644 arch/arm/dts/rk3288-miniarm.dtsi
 create mode 100644 board/rockchip/miniarm_rk3288/Kconfig
 create mode 100644 board/rockchip/miniarm_rk3288/MAINTAINERS
 create mode 100644 board/rockchip/miniarm_rk3288/Makefile
 create mode 100644 board/rockchip/miniarm_rk3288/miniarm-rk3288.c
 create mode 100644 configs/miniarm-rk3288_defconfig
 create mode 100644 include/configs/miniarm_rk3288.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 639c06d..d93fabc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
+   rk3288-miniarm.dtb \
rk3288-popmetal.dtb \
rk3036-sdk.dtb \
rk3399-evb.dtb
diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts
new file mode 100644
index 000..c741082
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dts
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miniarm.dtsi"
+
+/ {
+   model = "Miniarm-RK3288";
+   compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   rockchip,num-channels = <2>;
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   /* Add a dummy value to cause of-platdata think this is bytes */
+   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 
0xff>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
new file mode 100644
index 000..b889875
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -0,0 +1,533 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * inc

Re: [U-Boot] [PATCH] rockchip: add support for rk3288 miniarm board

[Ziyuan Xu]

Hi Simon,


On 2016年08月01日 07:28, Simon Glass wrote:

Hi Ziyuan,

On 27 July 2016 at 21:43, Ziyuan Xu <xzy...@rock-chips.com> wrote:

Miniarm is a rockchip rk3288 based development board, which has lots of
interface such as HDMI, USB, micro-SD card, Audio etc.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/dts/Makefile  |   1 +
  arch/arm/dts/rk3288-miniarm.dts|  61 +++
  arch/arm/dts/rk3288-miniarm.dtsi   | 533 +
  arch/arm/mach-rockchip/rk3288/Kconfig  |  10 +
  board/rockchip/miniarm_rk3288/Kconfig  |  15 +
  board/rockchip/miniarm_rk3288/MAINTAINERS  |   6 +
  board/rockchip/miniarm_rk3288/Makefile |   7 +
  board/rockchip/miniarm_rk3288/miniarm-rk3288.c |  15 +
  configs/miniarm-rk3288_defconfig   |  65 +++
  doc/README.rockchip|   3 +-
  include/configs/miniarm_rk3288.h   |  26 ++
  11 files changed, 741 insertions(+), 1 deletion(-)
  create mode 100644 arch/arm/dts/rk3288-miniarm.dts
  create mode 100644 arch/arm/dts/rk3288-miniarm.dtsi
  create mode 100644 board/rockchip/miniarm_rk3288/Kconfig
  create mode 100644 board/rockchip/miniarm_rk3288/MAINTAINERS
  create mode 100644 board/rockchip/miniarm_rk3288/Makefile
  create mode 100644 board/rockchip/miniarm_rk3288/miniarm-rk3288.c
  create mode 100644 configs/miniarm-rk3288_defconfig
  create mode 100644 include/configs/miniarm_rk3288.h

Acked-by: Simon Glass <s...@chromium.org>

But please can you keep things in alpha order? See below.

Okay, I will send v2 patch later, also keep your ASK tag.



diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 639c06d..50ddb39 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 rk3288-evb.dtb \
 rk3288-fennec.dtb \
 rk3288-popmetal.dtb \
+   rk3288-miniarm.dtb \

move up one line


 rk3036-sdk.dtb \
 rk3399-evb.dtb
  dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts
new file mode 100644
index 000..c741082
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dts
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miniarm.dtsi"
+
+/ {
+   model = "Miniarm-RK3288";
+   compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   rockchip,num-channels = <2>;
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   /* Add a dummy value to cause of-platdata think this is bytes */
+   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 
0xff>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
new file mode 100644
index 000..b889875
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -0,0 +1,533 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and

Re: [U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

Hi Tom,


On 2016年07月29日 09:12, Tom Rini wrote:

On Fri, Jul 29, 2016 at 09:06:29AM +0800, Ziyuan Xu wrote:

Hi Tom,

On 2016年07月29日 08:34, Tom Rini wrote:

On Fri, Jul 29, 2016 at 07:34:09AM +0800, Ziyuan Xu wrote:

Hi Tom,

On 2016年07月29日 06:15, Tom Rini wrote:

On Thu, Jul 28, 2016 at 07:03:17PM +0800, Chen-Yu Tsai wrote:

Hi,

On Thu, Jul 28, 2016 at 6:13 PM, Ziyuan Xu <xzy...@rock-chips.com> wrote:

For ARMv7-A architecture, the valid ISB instruction is asm volatile("isb").

This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
ramdisk start = 0x, ramdisk end = 0x
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS

Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/include/asm/system.h | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..12d4ba0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -227,13 +227,15 @@ void __noreturn psci_system_reset(bool smc);
   */
  void save_boot_params_ret(void);

-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
  #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

  #ifdef __ARM_ARCH_7A__
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
  #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  #else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
  #define wfi()
  #endif


arch/arm/include/asm/barriers.h already has a proper set of
ISB/DSB macros. Please consider using those instead.

Please fix arch/arm/include/asm/system.h to use the macros found in
barriers.h rather than have their own versions.  Thanks!

If I understand correctly, I can change into as bellow:
#define isb() ISB
How about it?

Well, I'd rather not have ISB and isb, just ISB, which means we might
have to fix other places too.  If that starts looking too huge, we can
do this in steps and just do what you suggested for now and for next
release move everything over.

As I mentioned before, arch/arm/include/asm/barriers.h defined ISB
macro.  If I only want to fix the issue which I hit on rk3288 board,
I just use ISB in arch/arm/include/asm/system.h::set_cr() instead of
isb(). But isb() had been invoked in some places.

I can't verify integrallty after all revision, it involve some
boards and feature. But this does fix for rk3288, if you agree with
me, could you apply it provisionally?:-)

I would really like to try and fix the other possibly latent issues that
we have by not calling a real ISB.  Please try moving towards all places
that need an isb calling the correct one from barriers.h and giving it a
spin on the hardware you have available.
I used ISB instead of isb(), everything works sane on my rockchip rk3288 
boards.:-)
Will you send a patch to fix it and other possibly latent issues? Or 
apply this temporarily?







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Re: [U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

On 2016年07月29日 09:12, Tom Rini wrote:

On Fri, Jul 29, 2016 at 09:06:29AM +0800, Ziyuan Xu wrote:

Hi Tom,

On 2016年07月29日 08:34, Tom Rini wrote:

On Fri, Jul 29, 2016 at 07:34:09AM +0800, Ziyuan Xu wrote:

Hi Tom,

On 2016年07月29日 06:15, Tom Rini wrote:

On Thu, Jul 28, 2016 at 07:03:17PM +0800, Chen-Yu Tsai wrote:

Hi,

On Thu, Jul 28, 2016 at 6:13 PM, Ziyuan Xu <xzy...@rock-chips.com> wrote:

For ARMv7-A architecture, the valid ISB instruction is asm volatile("isb").

This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
ramdisk start = 0x, ramdisk end = 0x
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS

Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/include/asm/system.h | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..12d4ba0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -227,13 +227,15 @@ void __noreturn psci_system_reset(bool smc);
   */
  void save_boot_params_ret(void);

-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
  #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

  #ifdef __ARM_ARCH_7A__
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
  #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  #else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
  #define wfi()
  #endif


arch/arm/include/asm/barriers.h already has a proper set of
ISB/DSB macros. Please consider using those instead.

Please fix arch/arm/include/asm/system.h to use the macros found in
barriers.h rather than have their own versions.  Thanks!

If I understand correctly, I can change into as bellow:
#define isb() ISB
How about it?

Well, I'd rather not have ISB and isb, just ISB, which means we might
have to fix other places too.  If that starts looking too huge, we can
do this in steps and just do what you suggested for now and for next
release move everything over.

As I mentioned before, arch/arm/include/asm/barriers.h defined ISB
macro.  If I only want to fix the issue which I hit on rk3288 board,
I just use ISB in arch/arm/include/asm/system.h::set_cr() instead of
isb(). But isb() had been invoked in some places.

I can't verify integrallty after all revision, it involve some
boards and feature. But this does fix for rk3288, if you agree with
me, could you apply it provisionally?:-)

I would really like to try and fix the other possibly latent issues that
we have by not calling a real ISB.  Please try moving towards all places
that need an isb calling the correct one from barriers.h and giving it a
spin on the hardware you have available.


Okay,  I will confirm it on my boards.:-)






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Re: [U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

Hi Tom,

On 2016年07月29日 08:34, Tom Rini wrote:

On Fri, Jul 29, 2016 at 07:34:09AM +0800, Ziyuan Xu wrote:

Hi Tom,

On 2016年07月29日 06:15, Tom Rini wrote:

On Thu, Jul 28, 2016 at 07:03:17PM +0800, Chen-Yu Tsai wrote:

Hi,

On Thu, Jul 28, 2016 at 6:13 PM, Ziyuan Xu <xzy...@rock-chips.com> wrote:

For ARMv7-A architecture, the valid ISB instruction is asm volatile("isb").

This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
ramdisk start = 0x, ramdisk end = 0x
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS

Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/include/asm/system.h | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..12d4ba0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -227,13 +227,15 @@ void __noreturn psci_system_reset(bool smc);
   */
  void save_boot_params_ret(void);

-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
  #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

  #ifdef __ARM_ARCH_7A__
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
  #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  #else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
  #define wfi()
  #endif


arch/arm/include/asm/barriers.h already has a proper set of
ISB/DSB macros. Please consider using those instead.

Please fix arch/arm/include/asm/system.h to use the macros found in
barriers.h rather than have their own versions.  Thanks!

If I understand correctly, I can change into as bellow:
#define isb() ISB
How about it?

Well, I'd rather not have ISB and isb, just ISB, which means we might
have to fix other places too.  If that starts looking too huge, we can
do this in steps and just do what you suggested for now and for next
release move everything over.
As I mentioned before, arch/arm/include/asm/barriers.h defined ISB 
macro.  If I only want to fix the issue which I hit on rk3288 board, I 
just use ISB in arch/arm/include/asm/system.h::set_cr() instead of 
isb(). But isb() had been invoked in some places.


I can't verify integrallty after all revision, it involve some boards 
and feature. But this does fix for rk3288, if you agree with me, could 
you apply it provisionally?:-)







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Re: [U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

Hi Tom,

On 2016年07月29日 06:15, Tom Rini wrote:

On Thu, Jul 28, 2016 at 07:03:17PM +0800, Chen-Yu Tsai wrote:

Hi,

On Thu, Jul 28, 2016 at 6:13 PM, Ziyuan Xu <xzy...@rock-chips.com> wrote:

For ARMv7-A architecture, the valid ISB instruction is asm volatile("isb").

This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
ramdisk start = 0x, ramdisk end = 0x
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS

Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/include/asm/system.h | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..12d4ba0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -227,13 +227,15 @@ void __noreturn psci_system_reset(bool smc);
   */
  void save_boot_params_ret(void);

-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
  #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

  #ifdef __ARM_ARCH_7A__
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
  #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  #else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
  #define wfi()
  #endif


arch/arm/include/asm/barriers.h already has a proper set of
ISB/DSB macros. Please consider using those instead.

Please fix arch/arm/include/asm/system.h to use the macros found in
barriers.h rather than have their own versions.  Thanks!


If I understand correctly, I can change into as bellow:
#define isb() ISB
How about it?




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Re: [U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

Hi Alexander,

On 2016年07月28日 18:39, Alexander Graf wrote:

On 07/28/2016 12:13 PM, Ziyuan Xu wrote:
For ARMv7-A architecture, the valid ISB instruction is asm 
volatile("isb").


This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
ramdisk start = 0x, ramdisk end = 0x
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS

Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>


Perfect! So with this, EFI support can still be in and things work fine?


I had not test EFI feature, in fact, I have no experience about it. Any 
progress I will promptly inform you.





Alex







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Re: [U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

Hi,

On 2016年07月28日 19:03, Chen-Yu Tsai wrote:

Hi,

On Thu, Jul 28, 2016 at 6:13 PM, Ziyuan Xu <xzy...@rock-chips.com> wrote:

For ARMv7-A architecture, the valid ISB instruction is asm volatile("isb").

This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
ramdisk start = 0x, ramdisk end = 0x
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS

Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

  arch/arm/include/asm/system.h | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..12d4ba0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -227,13 +227,15 @@ void __noreturn psci_system_reset(bool smc);
   */
  void save_boot_params_ret(void);

-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
  #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

  #ifdef __ARM_ARCH_7A__
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
  #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  #else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
  #define wfi()
  #endif


arch/arm/include/asm/barriers.h already has a proper set of
ISB/DSB macros. Please consider using those instead.

I know just what you mean.
arch/arm/include/asm/barriers.h defined ISB macro.  If I only want to 
fix the issue which I hit on rk3288 board, I just use ISB in 
arch/arm/include/asm/system.h::set_cr() instead of isb(). But isb() had 
been invoked in some places, IMHO, this patch is more apposite.:-)


You'll see they also support ARMv6's CP15 ISB/DSB.

Regards
ChenYu






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[U-Boot] [PATCH] arm: re-implement proper ISB instruction for ARMv7-A

[Ziyuan Xu]

For ARMv7-A architecture, the valid ISB instruction is asm volatile("isb").

This patch fixes the U-Boot was stuck in invalidate_dcache_all() before
booting linux kernel, which occurred on rk3288-base development board
such as evb-rk3288, rock2-rk3288. And something output via console like:

=> bootz 0x200
0x0200
   ramdisk start = 0x, ramdisk end = 0x
   Continuing to boot without FDT
   Initial value for argc=3
   Final value for argc=3
   using: ATAGS

   Starting kernel ...

Linux kernel exactly the same way(see arch/arm/include/asm/barrier.h).

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 arch/arm/include/asm/system.h | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0be..12d4ba0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -227,13 +227,15 @@ void __noreturn psci_system_reset(bool smc);
  */
 void save_boot_params_ret(void);
 
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
 #ifdef __ARM_ARCH_7A__
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
 #else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
 #define wfi()
 #endif
 
-- 
1.9.1


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Re: [U-Boot] [PATCH] mmc: dw_mmc: fix the wrong Mask bit boundary for fifo_count bit

[Ziyuan Xu]

Hi Jaehoon,

On 2016年07月28日 13:26, Jaehoon Chung wrote:

According to DesignWare TRM, FIFO_COUNT is bit[29:17].
If get the correct fifo_count value, it has to  use the FIFO_MASK
as 0x1FFF, not 0x1FF.
Ah, I have no doubt the fifo_count defined. The fifo depth of Rockchip 
SoCs is 256, the former work sane coincidentally.:-)

Thanks for fix.
Reviewed-by: Ziyuan Xu <xzy...@rock-chips.com>


Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
  include/dwmmc.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/dwmmc.h b/include/dwmmc.h
index 6aebe96..eb03f7f 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -105,7 +105,7 @@
  
  /* Status Register */

  #define DWMCI_BUSY(1 << 9)
-#define DWMCI_FIFO_MASK0x1ff
+#define DWMCI_FIFO_MASK0x1fff
  #define DWMCI_FIFO_SHIFT  17
  
  /* FIFOTH Register */



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[U-Boot] [PATCH] rockchip: add fastboot support for rk3036 board

[Ziyuan Xu]

Enable fastboot feature on rk3036, please refer to doc/README.rockchip
for more detailed usage.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 arch/arm/dts/rk3036-sdk.dts|  2 --
 board/rockchip/evb_rk3036/evb_rk3036.c | 46 ++
 board/rockchip/kylin_rk3036/kylin_rk3036.c | 46 ++
 include/configs/rk3036_common.h| 21 +-
 4 files changed, 112 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts
index a83badb..1c9ddf9 100644
--- a/arch/arm/dts/rk3036-sdk.dts
+++ b/arch/arm/dts/rk3036-sdk.dts
@@ -41,6 +41,4 @@
 
 _otg {
status = "okay";
-
-   dr_mode = "host";
 };
diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c 
b/board/rockchip/evb_rk3036/evb_rk3036.c
index f5758b1..e5582b4 100644
--- a/board/rockchip/evb_rk3036/evb_rk3036.c
+++ b/board/rockchip/evb_rk3036/evb_rk3036.c
@@ -47,3 +47,49 @@ void enable_caches(void)
dcache_enable();
 }
 #endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include 
+#include 
+
+static struct dwc2_plat_otg_data rk3036_otg_data = {
+   .rx_fifo_sz = 512,
+   .np_tx_fifo_sz  = 16,
+   .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   int node;
+   const char *mode;
+   bool matched = false;
+   const void *blob = gd->fdt_blob;
+
+   /* find the usb_otg node */
+   node = fdt_node_offset_by_compatible(blob, -1,
+   "rockchip,rk3288-usb");
+
+   while (node > 0) {
+   mode = fdt_getprop(blob, node, "dr_mode", NULL);
+   if (mode && strcmp(mode, "otg") == 0) {
+   matched = true;
+   break;
+   }
+
+   node = fdt_node_offset_by_compatible(blob, node,
+   "rockchip,rk3288-usb");
+   }
+   if (!matched) {
+   debug("Not found usb_otg device\n");
+   return -ENODEV;
+   }
+   rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+   return dwc2_udc_probe(_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+   return 0;
+}
+#endif
diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c 
b/board/rockchip/kylin_rk3036/kylin_rk3036.c
index 2a25871..5ade695 100644
--- a/board/rockchip/kylin_rk3036/kylin_rk3036.c
+++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c
@@ -79,3 +79,49 @@ void enable_caches(void)
dcache_enable();
 }
 #endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include 
+#include 
+
+static struct dwc2_plat_otg_data rk3036_otg_data = {
+   .rx_fifo_sz = 512,
+   .np_tx_fifo_sz  = 16,
+   .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   int node;
+   const char *mode;
+   bool matched = false;
+   const void *blob = gd->fdt_blob;
+
+   /* find the usb_otg node */
+   node = fdt_node_offset_by_compatible(blob, -1,
+   "rockchip,rk3288-usb");
+
+   while (node > 0) {
+   mode = fdt_getprop(blob, node, "dr_mode", NULL);
+   if (mode && strcmp(mode, "otg") == 0) {
+   matched = true;
+   break;
+   }
+
+   node = fdt_node_offset_by_compatible(blob, node,
+   "rockchip,rk3288-usb");
+   }
+   if (!matched) {
+   debug("Not found usb_otg device\n");
+   return -ENODEV;
+   }
+   rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+   return dwc2_udc_probe(_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+   return 0;
+}
+#endif
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index ffcaa6f..21d4683 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -6,7 +6,7 @@
 #ifndef __CONFIG_RK3036_COMMON_H
 #define __CONFIG_RK3036_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE  32
+#define CONFIG_SYS_CACHELINE_SIZE  64
 
 #include 
 
@@ -60,6 +60,25 @@
 #define CONFIG_SF_DEFAULT_SPEED 2000
 
 #ifndef CONFIG_SPL_BUILD
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_USB_GADGET_VBUS_DRAW0
+
+/* fastboot  */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV  0
+#define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE   0x0800

[U-Boot] [PATCH] rockchip: add support for rk3288 miniarm board

[Ziyuan Xu]

Miniarm is a rockchip rk3288 based development board, which has lots of
interface such as HDMI, USB, micro-SD card, Audio etc.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3288-miniarm.dts|  61 +++
 arch/arm/dts/rk3288-miniarm.dtsi   | 533 +
 arch/arm/mach-rockchip/rk3288/Kconfig  |  10 +
 board/rockchip/miniarm_rk3288/Kconfig  |  15 +
 board/rockchip/miniarm_rk3288/MAINTAINERS  |   6 +
 board/rockchip/miniarm_rk3288/Makefile |   7 +
 board/rockchip/miniarm_rk3288/miniarm-rk3288.c |  15 +
 configs/miniarm-rk3288_defconfig   |  65 +++
 doc/README.rockchip|   3 +-
 include/configs/miniarm_rk3288.h   |  26 ++
 11 files changed, 741 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3288-miniarm.dts
 create mode 100644 arch/arm/dts/rk3288-miniarm.dtsi
 create mode 100644 board/rockchip/miniarm_rk3288/Kconfig
 create mode 100644 board/rockchip/miniarm_rk3288/MAINTAINERS
 create mode 100644 board/rockchip/miniarm_rk3288/Makefile
 create mode 100644 board/rockchip/miniarm_rk3288/miniarm-rk3288.c
 create mode 100644 configs/miniarm-rk3288_defconfig
 create mode 100644 include/configs/miniarm_rk3288.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 639c06d..50ddb39 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-evb.dtb \
rk3288-fennec.dtb \
rk3288-popmetal.dtb \
+   rk3288-miniarm.dtb \
rk3036-sdk.dtb \
rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts
new file mode 100644
index 000..c741082
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dts
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miniarm.dtsi"
+
+/ {
+   model = "Miniarm-RK3288";
+   compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   rockchip,num-channels = <2>;
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   /* Add a dummy value to cause of-platdata think this is bytes */
+   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 
0xff>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
new file mode 100644
index 000..b889875
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -0,0 +1,533 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY K

[U-Boot] [PATCH 2/2] mmc: dw_mmc: fix data starvation by host timeout under FIFO mode

[Ziyuan Xu]

This patch fixes data starvation by host timeout(HTO) error interrupt
which occurred under FIFO mode transfer on rk3036 board.

The former implement, the actual bytes were transmitted may be less than
should be. The size will still subtract value of len in case of there is
no receive/transmit FIFO data request interrupt.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 38d4a64..41b7035 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,6 +120,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
}
 
if (host->fifo_mode && size) {
+   len = 0;
if (data->flags == MMC_DATA_READ) {
if ((dwmci_readl(host, DWMCI_RINTSTS) &
 DWMCI_INTMSK_RXDR)) {
-- 
1.9.1


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[U-Boot] [PATCH 1/2] mmc: dw_mmc: transfer proper bytes to FIFO

[Ziyuan Xu]

The former implement, dw_mmc will push and pop the redundant data to
FIFO, we should transfer it according to the real size.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

 drivers/mmc/dw_mmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 2cf7bae..38d4a64 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -126,6 +126,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
len = dwmci_readl(host, DWMCI_STATUS);
len = (len >> DWMCI_FIFO_SHIFT) &
DWMCI_FIFO_MASK;
+   len = min(size, len);
for (i = 0; i < len; i++)
*buf++ =
dwmci_readl(host, DWMCI_DATA);
@@ -139,6 +140,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, 
struct mmc_data *data)
len = fifo_depth - ((len >>
   DWMCI_FIFO_SHIFT) &
   DWMCI_FIFO_MASK);
+   len = min(size, len);
for (i = 0; i < len; i++)
dwmci_writel(host, DWMCI_DATA,
 *buf++);
-- 
1.9.1


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Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

[Ziyuan Xu]

On 2016年07月27日 19:15, Jaehoon Chung wrote:

On 07/27/2016 04:28 PM, Yangbo Lu wrote:

Hi Tom,

Could you help to assign this mmc patch reviewing to right person?
It seems no one had reviewed it for almost half year.

And another my mmc patch also needs to be reviewed.
I submitted in May. Please help.
http://patchwork.ozlabs.org/patch/624448/


Thank you very much.


Best regards,
Yangbo Lu


-Original Message-
From: Yangbo Lu [mailto:yangbo...@nxp.com]
Sent: Wednesday, March 09, 2016 11:00 AM
To: u-boot@lists.denx.de
Cc: Pantelis Antoniou; Yangbo Lu
Subject: [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

When the MMC framework was added in u-boot, the mmc_go_idle was added
before mmc_send_op_cond_iter in function mmc_send_op_cond annotating that
some cards seemed to need this. Actually, we still need to do this in
function mmc_complete_op_cond for those cards.
This has been verified on Micron MTFC4GACAECN eMMC chip.

If there is no go_idle(), then what happen?
If you share the information more, i can check the more..

Sounds interesting, I also want want to know what happen?
It seems like you failed in CMD1? The eMMC device was always in busy 
device within 1 second?


Best Regards,
Jaehoon Chung


Signed-off-by: Yangbo Lu 
---
  drivers/mmc/mmc.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index ede5d6e..82e3268
100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -418,6 +418,9 @@ static int mmc_complete_op_cond(struct mmc *mmc)
uint start;
int err;

+   /* Some cards seem to need this */
+   mmc_go_idle(mmc);
+
mmc->op_cond_pending = 0;
if (!(mmc->ocr & OCR_BUSY)) {
start = get_timer(0);
--
2.1.0.27.g96db324

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Re: [U-Boot] [issue report] mainline u-boot was stuck before booting kernel

[Ziyuan Xu]

Hi Sandy,

I'm pleased to learn that it does fix for you.

On 2016年07月26日 21:16, Sandy Patterson wrote:

Hi Ziyuan, good work!

This does in fact fix it for me.

I followed through your notes. What is isr() supposed to do? it looks 
like it just tells the compiler that the memory cache has been 
invalidated. But in the

isb()?
I'm not very enrich knowledgeable in cache, this issue I'm doing also is 
a big learning experience for me. I catch something from TRM, and review 
u-boot again and again in order to figure out the root cause. I suspect 
the former disable_dcache/mmu operation didn't complete, or branch 
prediction was abnormal?

I'm not really sure.


TRM it says we need to actually do an ISB.

Would fixing the dcache flush so it does an ISB when it disables the 
MMU maybe be an alternative solution? (I couldn't figure out which 
macro I should be using. isb() is defined for arm64 to do the actual op.


Anyway, the following also fixes for me.

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1121dc3..3494a5c 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -217,6 +217,8 @@ static void cache_disable(uint32_t cache_bit)
if (cache_bit == (CR_C | CR_M))
flush_dcache_all();
set_cr(reg & ~cache_bit);
+   if(cache_bit & CR_M)
+   asm volatile ("isb" : : : "memory");
 }
 #endif


I'm not sure what kinds of side effects for other boards these changes 
would have.

Let's listen to the opinions of others.


On Tue, Jul 26, 2016 at 8:15 AM, Ziyuan Xu <xzy...@rock-chips.com 
<mailto:xzy...@rock-chips.com>> wrote:


+ Simon and heiko

On 2016年07月26日 14:30, Ziyuan Xu wrote:

Dear All,

I add the ISB operation after dcache_disable(), and I can jump
to linux kernel entry.:-)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 6eac5ef..5cc09ba 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -43,6 +43,7 @@ int cleanup_before_linux_select(int flags)
*/
dcache_disable();
v7_outer_cache_disable();
+   ISB;

/*
* After D-cache is flushed and before it is
disabled there may

Sounds crazy. In fact, there is already an 'ISB' operation in
set_cr() which to disable dcache and MMU. But it just tell
processor that  memory had change, not real ISB for armv7.

dcache_disable
==>flush_dcache_all()
==>set_cr()   disable dcache and MMU.

#define isb() __asm__ __volatile__ ("" : : : "memory")
static inline void set_cr(unsigned int val)
{
if (is_hyp())
asm volatile("mcr p15, 4, %0, c1, c0, 0@ set CR" :
  : "r" (val)
  : "cc");
else
asm volatile("mcr p15, 0, %0, c1, c0, 0@ set CR" :
  : "r" (val)
  : "cc");
isb();
}

I also find something in ARM cortex-A17 TRM. ==>"Disable the
MMU from the each processor followed by an ISB to ensure the
MMU disable operation is complete, then followed by a DSB to
drain previous memory transactions."

In my humble opinion, maybe instructions tlb had alter, and
cause running away??? I'm not sure about it.
@Sandy, could you have a try with my update?

@Simon,  did you hit this glitch? I hope you can help ...:-)

On 2016年07月25日 23:00, Sandy Patterson wrote:

Ah, thanks. Your debugging looks the same as what I've
seen from printf debugging. I'll try to verify though.

On Mon, Jul 25, 2016 at 10:58 AM, Ziyuan Xu
<xzy...@rock-chips.com <mailto:xzy...@rock-chips.com>
<mailto:xzy...@rock-chips.com
<mailto:xzy...@rock-chips.com>>> wrote:

hi Stany,

The difference is that you print out assertion log.

Reset not supported on this platform
### ERROR ### Please RESET the board ###

You can add show_boot_progress() function in your bsp
file to find
out something.
#define CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);

}


On 2016年07月25日 22:12, Ziyuan Xu wrote:

Hi All,

I'm sorry to tell you t

Re: [U-Boot] [issue report] mainline u-boot was stuck before booting kernel

[Ziyuan Xu]

+ Simon and heiko

On 2016年07月26日 14:30, Ziyuan Xu wrote:

Dear All,

I add the ISB operation after dcache_disable(), and I can jump to 
linux kernel entry.:-)


diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 6eac5ef..5cc09ba 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -43,6 +43,7 @@ int cleanup_before_linux_select(int flags)
*/
dcache_disable();
v7_outer_cache_disable();
+   ISB;

/*
* After D-cache is flushed and before it is disabled 
there may


Sounds crazy. In fact, there is already an 'ISB' operation in set_cr() 
which to disable dcache and MMU. But it just tell processor that  
memory had change, not real ISB for armv7.


dcache_disable
==>flush_dcache_all()
==>set_cr()   disable dcache and MMU.

#define isb() __asm__ __volatile__ ("" : : : "memory")
static inline void set_cr(unsigned int val)
{
if (is_hyp())
asm volatile("mcr p15, 4, %0, c1, c0, 0@ set CR" :
  : "r" (val)
  : "cc");
else
asm volatile("mcr p15, 0, %0, c1, c0, 0@ set CR" :
  : "r" (val)
  : "cc");
isb();
}

I also find something in ARM cortex-A17 TRM. ==>"Disable the MMU from 
the each processor followed by an ISB to ensure the MMU disable 
operation is complete, then followed by a DSB to drain previous memory 
transactions."


In my humble opinion, maybe instructions tlb had alter, and cause 
running away??? I'm not sure about it.

@Sandy, could you have a try with my update?

@Simon,  did you hit this glitch? I hope you can help ...:-)

On 2016年07月25日 23:00, Sandy Patterson wrote:
Ah, thanks. Your debugging looks the same as what I've seen from 
printf debugging. I'll try to verify though.


On Mon, Jul 25, 2016 at 10:58 AM, Ziyuan Xu <xzy...@rock-chips.com 
<mailto:xzy...@rock-chips.com>> wrote:


hi Stany,

The difference is that you print out assertion log.

Reset not supported on this platform
### ERROR ### Please RESET the board ###

You can add show_boot_progress() function in your bsp file to find
out something.
#define CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);

}


On 2016年07月25日 22:12, Ziyuan Xu wrote:

Hi All,

I'm sorry to tell you that I failed to boot linux kernel with
the mainline u-boot on rk3288 board(both evb-rk3288 &
fennec-rk3288). It was stuck in cleanup_before_linux() before
jumping to linux, and the boot_stage_flag is
BOOTSTAGE_ID_BOOTM_HANDOFF.

## Current stack ends at 0x7df638b0 *  kernel: cmdline image
address = 0x0200
## No init Ramdisk
   ramdisk start = 0x, ramdisk end = 0x
## No Flattened Device Tree
Continuing to boot without FDT
Initial value for argc=3
Final value for argc=3
using: ATAGS
## Transferring control to Linux (at address 0200)...

Starting kernel ...

With the further investigation, it never returnned back from
invalidate_dcache_all(). I mean that I can't reach stage 4 as
below.

cleanup_before_linux
==>cleanup_before_linux_select
==>1.disable_interrupts
==>2.dcache_disable
==>3.invalidate_dcache_all
==>4.icache_disable

Debug further, invalidate_dcache_all  invalidate all cache
one-by-one which cache type is DATA_ONLY, INSTRUCTION_DATA or
UNIFIED. And invalidate way from one set to another set in
order. The problem is that the PC ran away in invalidate way
loop  [cache level L1!!!].

I add some serial output code in __v7_flush_dcache_all to
figure out the bog.
I expect:
Print the value of r9 in sequence, e.g 0x7f, 0x7e, 0x7d.
0x01, 0x00 (hex)
In fact, print the value of r9 in sequence at first, but print
unexpected value afterwards.   e.g 0x7f, 0x7e, 0x7d, ..,0x73,
0x40, 0x85,

ENTRY(__v7_flush_dcache_all)
[snip]
loop1:
movr9, r7@ create working copy of max
index
loop2:
+  stmfdsp!, {r0}
+  ldr r0, =0xff69
+  str r9, [r0]
+  ldmfdsp!, {r0}
 ARM(orrr11, r10, r4, lsl r5)@ factor way and
cache number into r11
 THUMB(lslr6, r4, r5)
 THUMB(orrr11, r10, r6)@ factor way and
cache number into r11
 ARM(orr

[U-Boot] [PATCH v2 10/10] rockchip: add support for rk3288 PopMetal board

[Ziyuan Xu]

PopMetal is a rockchip rk3288 based board made by ChipSpark, which has
many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and
Gigabit Ethernet.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

Changes in v2: None

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3288-popmetal.dts  |  61 +++
 arch/arm/dts/rk3288-popmetal.dtsi | 520 ++
 arch/arm/mach-rockchip/rk3288/Kconfig |  11 +
 board/chipspark/popmetal_rk3288/Kconfig   |  15 +
 board/chipspark/popmetal_rk3288/MAINTAINERS   |   6 +
 board/chipspark/popmetal_rk3288/Makefile  |   7 +
 board/chipspark/popmetal_rk3288/popmetal-rk3288.c |  15 +
 configs/popmetal-rk3288_defconfig |  65 +++
 doc/README.rockchip   |   3 +-
 include/configs/popmetal_rk3288.h |  26 ++
 11 files changed, 729 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3288-popmetal.dts
 create mode 100644 arch/arm/dts/rk3288-popmetal.dtsi
 create mode 100644 board/chipspark/popmetal_rk3288/Kconfig
 create mode 100644 board/chipspark/popmetal_rk3288/MAINTAINERS
 create mode 100644 board/chipspark/popmetal_rk3288/Makefile
 create mode 100644 board/chipspark/popmetal_rk3288/popmetal-rk3288.c
 create mode 100644 configs/popmetal-rk3288_defconfig
 create mode 100644 include/configs/popmetal_rk3288.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 095a774..dffbd9c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
+   rk3288-popmetal.dtb \
rk3036-sdk.dtb \
rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
new file mode 100644
index 000..3f61a61
--- /dev/null
+++ b/arch/arm/dts/rk3288-popmetal.dts
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-popmetal.dtsi"
+
+/ {
+   model = "PopMetal-RK3288";
+   compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   rockchip,num-channels = <2>;
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   /* Add a dummy value to cause of-platdata think this is bytes */
+   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 
0xff>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi 
b/arch/arm/dts/rk3288-popmetal.dtsi
new file mode 100644
index 000..f3bd468
--- /dev/null
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -0,0 +1,520 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantia

[U-Boot] [PATCH v2 08/10] rockchip: rk3036: update MAINTAINER file

[Ziyuan Xu]

Update MAINTAINER files for kylin_rk3036, evb_rk3036.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---

Changes in v2: None

 board/rockchip/evb_rk3036/MAINTAINERS   | 4 ++--
 board/rockchip/kylin_rk3036/MAINTAINERS | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/rockchip/evb_rk3036/MAINTAINERS 
b/board/rockchip/evb_rk3036/MAINTAINERS
index 152d31c..91f8a83 100644
--- a/board/rockchip/evb_rk3036/MAINTAINERS
+++ b/board/rockchip/evb_rk3036/MAINTAINERS
@@ -1,6 +1,6 @@
 EVB-RK3036
 M:  huang lin <h...@rock-chips.com>
 S:  Maintained
-F:  board/evb/evb-rk3036
-F:  include/configs/evb-rk3036.h
+F:  board/rockchip/evb_rk3036
+F:  include/configs/evb_rk3036.h
 F:  configs/evb-rk3036_defconfig
diff --git a/board/rockchip/kylin_rk3036/MAINTAINERS 
b/board/rockchip/kylin_rk3036/MAINTAINERS
index f8ee834..5453e7d 100644
--- a/board/rockchip/kylin_rk3036/MAINTAINERS
+++ b/board/rockchip/kylin_rk3036/MAINTAINERS
@@ -1,6 +1,6 @@
 KYLIN-RK3036
 M:  huang lin <h...@rock-chips.com>
 S:  Maintained
-F:  board/kylin/kylin-rk3036
-F:  include/configs/kylin-rk3036.h
+F:  board/rockchip/kylin_rk3036
+F:  include/configs/kylin_rk3036.h
 F:  configs/kylin-rk3036_defconfig
-- 
1.9.1

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[U-Boot] [PATCH v2 09/10] rockchip: add basic support for fennec-rk3288 board

[Ziyuan Xu]

Fennec is a RK3288-based development board with 2 USB ports, HDMI,
micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes
on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access
to display pins, I2C, SPI, UART and GPIOs.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---

Changes in v2: None

 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/rk3288-fennec.dts   |  60 
 arch/arm/dts/rk3288-fennec.dtsi  | 421 +++
 arch/arm/mach-rockchip/rk3288-board-spl.c|   3 +-
 arch/arm/mach-rockchip/rk3288/Kconfig|  10 +
 board/rockchip/fennec_rk3288/Kconfig |  15 +
 board/rockchip/fennec_rk3288/MAINTAINERS |   6 +
 board/rockchip/fennec_rk3288/Makefile|   7 +
 board/rockchip/fennec_rk3288/fennec-rk3288.c |  15 +
 configs/fennec-rk3288_defconfig  |  66 +
 doc/README.rockchip  |   3 +-
 include/configs/fennec_rk3288.h  |  26 ++
 12 files changed, 630 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3288-fennec.dts
 create mode 100644 arch/arm/dts/rk3288-fennec.dtsi
 create mode 100644 board/rockchip/fennec_rk3288/Kconfig
 create mode 100644 board/rockchip/fennec_rk3288/MAINTAINERS
 create mode 100644 board/rockchip/fennec_rk3288/Makefile
 create mode 100644 board/rockchip/fennec_rk3288/fennec-rk3288.c
 create mode 100644 configs/fennec-rk3288_defconfig
 create mode 100644 include/configs/fennec_rk3288.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c97e3f6..095a774 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-jerry.dtb \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
+   rk3288-fennec.dtb \
rk3036-sdk.dtb \
rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts
new file mode 100644
index 000..36e9f3d
--- /dev/null
+++ b/arch/arm/dts/rk3288-fennec.dts
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-fennec.dtsi"
+
+/ {
+   model = "Rockchip RK3288 Fennec Board";
+   compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   rockchip,num-channels = <2>;
+   rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+   0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+   0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+   0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+   0x8 0x1f4>;
+   rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+   0x0 0xc3 0x6 0x2>;
+   /* Add a dummy value to cause of-platdata think this is bytes */
+   rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 
0xff>;
+   rockchip,sdram-params = <0x20d266a4 0x5b6 2 53300 6 9 0>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-fennec.dtsi b/arch/arm/dts/rk3288-fennec.dtsi
new file mode 100644
index 000..f61252c
--- /dev/null
+++ b/arch/arm/dts/rk3288-fennec.dtsi
@@ -0,0 +1,421 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and 

[U-Boot] [PATCH v2 06/10] rockchip: rk3288: revise CONFIG_FASTBOOT_BUF_ADDR

[Ziyuan Xu]

CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for
fastboot.

Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---

Changes in v2: None

 include/configs/rk3288_common.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 7ef0f03..bad5eea 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -96,9 +96,7 @@
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_FASTBOOT_FLASH
 #define CONFIG_FASTBOOT_FLASH_MMC_DEV  1   /* eMMC */
-/* stroe safely fastboot buffer data to the middle of bank */
-#define CONFIG_FASTBOOT_BUF_ADDR   (CONFIG_SYS_SDRAM_BASE \
-   + SDRAM_BANK_SIZE / 2)
+#define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE   0x0800
 
 #define CONFIG_USB_GADGET_DOWNLOAD
-- 
1.9.1

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