Re: [PATCH v2] arm: dts: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems

2021-04-16 Thread Lokesh Vutla 



On 12/04/21 9:10 pm, Aswath Govindraju wrote:
> According to latest errata of J721e [1], HS400 mode is not supported
> in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2
> subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v
> in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode.
> 
> Also, update the itap delay values for all the MMCSD subsystems according
> the latest J721e data sheet[2]
> 
> [1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf
> [2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf
> 
> Fixes: 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into 
> U-Boot")
> Signed-off-by: Aswath Govindraju 
> ---
> 
> Changes since v1:
> - Corrected the fixes tag.

Applied to u-boot-ti.

Thanks and regards,
Lokesh

[PATCH v2] arm: dts: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems

2021-04-12 Thread Aswath Govindraju 
According to latest errata of J721e [1], HS400 mode is not supported
in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2
subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v
in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode.

Also, update the itap delay values for all the MMCSD subsystems according
the latest J721e data sheet[2]

[1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf
[2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf

Fixes: 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot")
Signed-off-by: Aswath Govindraju 
---

Changes since v1:
- Corrected the fixes tag.

 arch/arm/dts/k3-j721e-main.dtsi | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index e47b6c0eb706..07b489679ed9 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -1078,13 +1078,12 @@
assigned-clocks = <_clks 91 1>;
assigned-clock-parents = <_clks 91 2>;
bus-width = <8>;
-   mmc-hs400-1_8v;
+   mmc-hs200-1_8v;
mmc-ddr-1_8v;
ti,otap-del-sel-legacy = <0xf>;
ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
-   ti,otap-del-sel-hs400 = <0x0>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
@@ -1102,14 +1101,20 @@
assigned-clocks = <_clks 92 0>;
assigned-clock-parents = <_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
-   ti,otap-del-sel-sd-hs = <0xf>;
+   ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+   ti,itap-del-sel-legacy = <0x0>;
+   ti,itap-del-sel-sd-hs = <0x0>;
+   ti,itap-del-sel-sdr12 = <0x0>;
+   ti,itap-del-sel-sdr25 = <0x0>;
+   ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+   sdhci-caps-mask = <0x2 0x0>;
};
 
main_sdhci2: sdhci@4f98000 {
@@ -1122,14 +1127,20 @@
assigned-clocks = <_clks 93 0>;
assigned-clock-parents = <_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
-   ti,otap-del-sel-sd-hs = <0xf>;
+   ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+   ti,itap-del-sel-legacy = <0x0>;
+   ti,itap-del-sel-sd-hs = <0x0>;
+   ti,itap-del-sel-sdr12 = <0x0>;
+   ti,itap-del-sel-sdr25 = <0x0>;
+   ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+   sdhci-caps-mask = <0x2 0x0>;
};
 
usbss0: cdns-usb@4104000 {
-- 
2.17.1