Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
Linux dts commit details:
commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
EDIMM2.2 Starter Kit")
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- add Linux commit details
arch/arm/dts/Makefile |1 +
.../imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi | 31 +
arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts | 97 +
arch/arm/dts/imx8mm-icore-mx8mm-u-boot.dtsi | 27 +
arch/arm/mach-imx/imx8m/Kconfig | 14 +
board/engicam/imx8mm/Kconfig | 14 +
board/engicam/imx8mm/MAINTAINERS |7 +
board/engicam/imx8mm/Makefile | 12 +
board/engicam/imx8mm/icore_mx8mm.c| 85 +
board/engicam/imx8mm/lpddr4_timing.c | 1846 +
board/engicam/imx8mm/spl.c| 101 +
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 92 +
include/configs/imx8mm_icore_mx8mm.h | 100 +
13 files changed, 2427 insertions(+)
create mode 100644 arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts
create mode 100644 arch/arm/dts/imx8mm-icore-mx8mm-u-boot.dtsi
create mode 100644 board/engicam/imx8mm/Kconfig
create mode 100644 board/engicam/imx8mm/MAINTAINERS
create mode 100644 board/engicam/imx8mm/Makefile
create mode 100644 board/engicam/imx8mm/icore_mx8mm.c
create mode 100644 board/engicam/imx8mm/lpddr4_timing.c
create mode 100644 board/engicam/imx8mm/spl.c
create mode 100644 configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
create mode 100644 include/configs/imx8mm_icore_mx8mm.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aec5020a0f..f5345af0e8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -833,6 +833,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
+ imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi
b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi
new file mode 100644
index 00..8b67bcff7d
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "imx8mm-icore-mx8mm-u-boot.dtsi"
+
+ {
+ u-boot,dm-spl;
+};
+
+_uart2 {
+ u-boot,dm-spl;
+};
+
+_usdhc1_gpio {
+ u-boot,dm-spl;
+};
+
+_usdhc1 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts
b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts
new file mode 100644
index 00..a4a2ada148
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "imx8mm.dtsi"
+#include "imx8mm-icore-mx8mm.dtsi"
+
+/ {
+ model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit";
+ compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
+"fsl,imx8mm";
+
+ chosen {
+ stdout-path =
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <40>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c2>;
+ status = "okay";
+};
+
+ {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c4>;
+ status = "okay";
+};
+
+ {
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x41c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x41c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x41c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x41c3
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1_gpio:
