Re: [U-Boot] [PATCH] ARM: dts: zynq: enablement of coresight topology
Hi Mathieu,
On 23. 10. 19 19:32, Mathieu Poirier wrote:
> Hi Michal,
>
> I was not CC'ed on the original post so I just noticed this today,
> hence the late reply. I don't know if you were looking for feedback
> or already picked up the patch but here it is anyway.
I haven't put the patch to my zynq/dt branch yet. And definitely any
feedback on this is welcome.
>
> On Wed, 9 Oct 2019 at 08:07, Michal Simek wrote:
>>
>> From: Zumeng Chen
>>
>> This patch is to build the coresight topology structure of zynq-7000
>> series according to the docs of coresight and userguide of zynq-7000.
>>
>> Signed-off-by: Zumeng Chen
>> Signed-off-by: Quanyang Wang
>> Signed-off-by: Michal Simek
>> ---
>>
>> arch/arm/boot/dts/zynq-7000.dtsi | 158 +++
>> 1 file changed, 158 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
>> b/arch/arm/boot/dts/zynq-7000.dtsi
>> index ca6425ad794c..86430ad76fee 100644
>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>> @@ -59,6 +59,40 @@
>> regulator-always-on;
>> };
>>
>> + replicator {
>> + compatible = "arm,coresight-static-replicator";
>> + clocks = < 27>, < 46>, < 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> +
>> + out-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* replicator output ports */
>> + port@0 {
>> + reg = <0>;
>> + replicator_out_port0: endpoint {
>> + remote-endpoint = <_in_port>;
>> + };
>> + };
>> + port@1 {
>> + reg = <1>;
>> + replicator_out_port1: endpoint {
>> + remote-endpoint = <_in_port>;
>> + };
>> + };
>> + };
>> + in-ports {
>> + /* replicator input port */
>> + port {
>> + replicator_in_port0: endpoint {
>> + slave-mode;
>
> The slave-mode property is no longer required and probably an
> oversight since it doesn't appear elsewhere in this patch.
likely yes. I will remove it.
>
>> + remote-endpoint = <_out_port>;
>> + };
>> + };
>> + };
>> + };
>> +
>> amba: amba {
>> compatible = "simple-bus";
>> #address-cells = <1>;
>> @@ -365,5 +399,129 @@
>> reg = <0xf8005000 0x1000>;
>> timeout-sec = <10>;
>> };
>> +
>> + etb@f8801000 {
>> + compatible = "arm,coresight-etb10", "arm,primecell";
>> + reg = <0xf8801000 0x1000>;
>> + clocks = < 27>, < 46>, < 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + in-ports {
>> + port {
>> + etb_in_port: endpoint {
>> + remote-endpoint =
>> <_out_port1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + tpiu@f8803000 {
>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>> + reg = <0xf8803000 0x1000>;
>> + clocks = < 27>, < 46>, < 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> + in-ports {
>> + port {
>> + tpiu_in_port: endpoint {
>> + remote-endpoint =
>> <_out_port0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@f8804000 {
>> + compatible = "arm,coresight-static-funnel",
>> "arm,primecell";
>> + reg = <0xf8804000 0x1000>;
>> + clocks = < 27>, < 46>, < 47>;
>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>> +
>> + /* funnel output ports */
>> + out-ports {
>> + port {
>> + funnel_out_port: endpoint {
>> + remote-endpoint =
>> +
>> <_in_port0>;
>> +
Re: [U-Boot] [PATCH] ARM: dts: zynq: enablement of coresight topology
Hi Michal,
I was not CC'ed on the original post so I just noticed this today,
hence the late reply. I don't know if you were looking for feedback
or already picked up the patch but here it is anyway.
On Wed, 9 Oct 2019 at 08:07, Michal Simek wrote:
>
> From: Zumeng Chen
>
> This patch is to build the coresight topology structure of zynq-7000
> series according to the docs of coresight and userguide of zynq-7000.
>
> Signed-off-by: Zumeng Chen
> Signed-off-by: Quanyang Wang
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/boot/dts/zynq-7000.dtsi | 158 +++
> 1 file changed, 158 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
> b/arch/arm/boot/dts/zynq-7000.dtsi
> index ca6425ad794c..86430ad76fee 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -59,6 +59,40 @@
> regulator-always-on;
> };
>
> + replicator {
> + compatible = "arm,coresight-static-replicator";
> + clocks = < 27>, < 46>, < 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* replicator output ports */
> + port@0 {
> + reg = <0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <_in_port>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <_in_port>;
> + };
> + };
> + };
> + in-ports {
> + /* replicator input port */
> + port {
> + replicator_in_port0: endpoint {
> + slave-mode;
The slave-mode property is no longer required and probably an
oversight since it doesn't appear elsewhere in this patch.
> + remote-endpoint = <_out_port>;
> + };
> + };
> + };
> + };
> +
> amba: amba {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -365,5 +399,129 @@
> reg = <0xf8005000 0x1000>;
> timeout-sec = <10>;
> };
> +
> + etb@f8801000 {
> + compatible = "arm,coresight-etb10", "arm,primecell";
> + reg = <0xf8801000 0x1000>;
> + clocks = < 27>, < 46>, < 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + in-ports {
> + port {
> + etb_in_port: endpoint {
> + remote-endpoint =
> <_out_port1>;
> + };
> + };
> + };
> + };
> +
> + tpiu@f8803000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0xf8803000 0x1000>;
> + clocks = < 27>, < 46>, < 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> + in-ports {
> + port {
> + tpiu_in_port: endpoint {
> + remote-endpoint =
> <_out_port0>;
> + };
> + };
> + };
> + };
> +
> + funnel@f8804000 {
> + compatible = "arm,coresight-static-funnel",
> "arm,primecell";
> + reg = <0xf8804000 0x1000>;
> + clocks = < 27>, < 46>, < 47>;
> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> + /* funnel output ports */
> + out-ports {
> + port {
> + funnel_out_port: endpoint {
> + remote-endpoint =
> +
> <_in_port0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* funnel input ports */
>
Re: [U-Boot] [PATCH] ARM: dts: zynq: enablement of coresight topology
On 10/9/19 10:07 PM, Michal Simek wrote:
From: Zumeng Chen
This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.
Signed-off-by: Zumeng Chen
Signed-off-by: Quanyang Wang
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-7000.dtsi | 158 +++
1 file changed, 158 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ca6425ad794c..86430ad76fee 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -59,6 +59,40 @@
regulator-always-on;
};
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <_in_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <_in_port>;
+ };
+ };
+ };
+ in-ports {
+ /* replicator input port */
+ port {
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <_out_port>;
+ };
+ };
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
@@ -365,5 +399,129 @@
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
+
+ etb@f8801000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0xf8801000 0x1000>;
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ etb_in_port: endpoint {
+ remote-endpoint =
<_out_port1>;
+ };
+ };
+ };
+ };
+
+ tpiu@f8803000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0xf8803000 0x1000>;
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint =
<_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@f8804000 {
+ compatible = "arm,coresight-static-funnel",
"arm,primecell";
+ reg = <0xf8804000 0x1000>;
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ /* funnel output ports */
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint =
+ <_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port@0 {
+ reg = <0>;
+ funnel0_in_port0: endpoint {
+ remote-endpoint =
<_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel0_in_port1: endpoint {
+ remote-endpoint =
<_out_port>;
+
[U-Boot] [PATCH] ARM: dts: zynq: enablement of coresight topology
From: Zumeng Chen
This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.
Signed-off-by: Zumeng Chen
Signed-off-by: Quanyang Wang
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-7000.dtsi | 158 +++
1 file changed, 158 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ca6425ad794c..86430ad76fee 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -59,6 +59,40 @@
regulator-always-on;
};
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <_in_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <_in_port>;
+ };
+ };
+ };
+ in-ports {
+ /* replicator input port */
+ port {
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <_out_port>;
+ };
+ };
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
@@ -365,5 +399,129 @@
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
+
+ etb@f8801000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0xf8801000 0x1000>;
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ etb_in_port: endpoint {
+ remote-endpoint =
<_out_port1>;
+ };
+ };
+ };
+ };
+
+ tpiu@f8803000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0xf8803000 0x1000>;
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint =
<_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@f8804000 {
+ compatible = "arm,coresight-static-funnel",
"arm,primecell";
+ reg = <0xf8804000 0x1000>;
+ clocks = < 27>, < 46>, < 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ /* funnel output ports */
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint =
+ <_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port@0 {
+ reg = <0>;
+ funnel0_in_port0: endpoint {
+ remote-endpoint =
<_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel0_in_port1: endpoint {
+ remote-endpoint =
<_out_port>;
+ };
+
