Re: [U-Boot] [PATCH 10/19] riscv: Add CSR numbers
Hi Lukas, On Thu, Nov 15, 2018 at 6:26 AM Auer, Lukas wrote: > > Hi Bin, > > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote: > > The standard RISC-V ISA sets aside a 12-bit encoding space for up > > to 4096 CSRs. This adds all known CSR numbers as defined in the > > RISC-V Privileged Architecture Version 1.10. > > > > Signed-off-by: Bin Meng > > --- > > > > arch/riscv/include/asm/encoding.h | 219 > > ++ > > 1 file changed, 219 insertions(+) > > > > What is the reason for adding these and also the exception code > definitions in the next patch? These are needed for the SBI and CSR instruction emulation. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 10/19] riscv: Add CSR numbers
Hi Bin, On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote: > The standard RISC-V ISA sets aside a 12-bit encoding space for up > to 4096 CSRs. This adds all known CSR numbers as defined in the > RISC-V Privileged Architecture Version 1.10. > > Signed-off-by: Bin Meng > --- > > arch/riscv/include/asm/encoding.h | 219 > ++ > 1 file changed, 219 insertions(+) > What is the reason for adding these and also the exception code definitions in the next patch? Thanks, Lukas > diff --git a/arch/riscv/include/asm/encoding.h > b/arch/riscv/include/asm/encoding.h > index 9ea50ce..0c47c53 100644 > --- a/arch/riscv/include/asm/encoding.h > +++ b/arch/riscv/include/asm/encoding.h > @@ -146,6 +146,225 @@ > #define RISCV_PGSHIFT 12 > #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) > > +/* CSR numbers */ > +#define CSR_FFLAGS 0x1 > +#define CSR_FRM 0x2 > +#define CSR_FCSR 0x3 > + > +#define CSR_SSTATUS 0x100 > +#define CSR_SIE 0x104 > +#define CSR_STVEC0x105 > +#define CSR_SCOUNTEREN 0x106 > +#define CSR_SSCRATCH 0x140 > +#define CSR_SEPC 0x141 > +#define CSR_SCAUSE 0x142 > +#define CSR_STVAL0x143 > +#define CSR_SIP 0x144 > +#define CSR_SATP 0x180 > + > +#define CSR_MSTATUS 0x300 > +#define CSR_MISA 0x301 > +#define CSR_MEDELEG 0x302 > +#define CSR_MIDELEG 0x303 > +#define CSR_MIE 0x304 > +#define CSR_MTVEC0x305 > +#define CSR_MCOUNTEREN 0x306 > +#define CSR_MHPMEVENT3 0x323 > +#define CSR_MHPMEVENT4 0x324 > +#define CSR_MHPMEVENT5 0x325 > +#define CSR_MHPMEVENT6 0x326 > +#define CSR_MHPMEVENT7 0x327 > +#define CSR_MHPMEVENT8 0x328 > +#define CSR_MHPMEVENT9 0x329 > +#define CSR_MHPMEVENT10 0x32a > +#define CSR_MHPMEVENT11 0x32b > +#define CSR_MHPMEVENT12 0x32c > +#define CSR_MHPMEVENT13 0x32d > +#define CSR_MHPMEVENT14 0x32e > +#define CSR_MHPMEVENT15 0x32f > +#define CSR_MHPMEVENT16 0x330 > +#define CSR_MHPMEVENT17 0x331 > +#define CSR_MHPMEVENT18 0x332 > +#define CSR_MHPMEVENT19 0x333 > +#define CSR_MHPMEVENT20 0x334 > +#define CSR_MHPMEVENT21 0x335 > +#define CSR_MHPMEVENT22 0x336 > +#define CSR_MHPMEVENT23 0x337 > +#define CSR_MHPMEVENT24 0x338 > +#define CSR_MHPMEVENT25 0x339 > +#define CSR_MHPMEVENT26 0x33a > +#define CSR_MHPMEVENT27 0x33b > +#define CSR_MHPMEVENT28 0x33c > +#define CSR_MHPMEVENT29 0x33d > +#define CSR_MHPMEVENT30 0x33e > +#define CSR_MHPMEVENT31 0x33f > +#define CSR_MSCRATCH 0x340 > +#define CSR_MEPC 0x341 > +#define CSR_MCAUSE 0x342 > +#define CSR_MTVAL0x343 > +#define CSR_MIP 0x344 > +#define CSR_PMPCFG0 0x3a0 > +#define CSR_PMPCFG1 0x3a1 > +#define CSR_PMPCFG2 0x3a2 > +#define CSR_PMPCFG3 0x3a3 > +#define CSR_PMPADDR0 0x3b0 > +#define CSR_PMPADDR1 0x3b1 > +#define CSR_PMPADDR2 0x3b2 > +#define CSR_PMPADDR3 0x3b3 > +#define CSR_PMPADDR4 0x3b4 > +#define CSR_PMPADDR5 0x3b5 > +#define CSR_PMPADDR6 0x3b6 > +#define CSR_PMPADDR7 0x3b7 > +#define CSR_PMPADDR8 0x3b8 > +#define CSR_PMPADDR9 0x3b9 > +#define CSR_PMPADDR100x3ba > +#define CSR_PMPADDR110x3bb > +#define CSR_PMPADDR120x3bc > +#define CSR_PMPADDR130x3bd > +#define CSR_PMPADDR140x3be > +#define CSR_PMPADDR150x3bf > + > +#define CSR_TSELECT 0x7a0 > +#define CSR_TDATA1 0x7a1 > +#define CSR_TDATA2 0x7a2 > +#define CSR_TDATA3 0x7a3 > +#define CSR_DCSR 0x7b0 > +#define CSR_DPC 0x7b1 > +#define CSR_DSCRATCH 0x7b2 > + > +#define CSR_MCYCLE 0xb00 > +#define CSR_MINSTRET 0xb02 > +#define CSR_MHPMCOUNTER3 0xb03 > +#define CSR_MHPMCOUNTER4 0xb04 > +#define CSR_MHPMCOUNTER5 0xb05 > +#define CSR_MHPMCOUNTER6 0xb06 > +#define CSR_MHPMCOUNTER7 0xb07 > +#define CSR_MHPMCOUNTER8 0xb08 > +#define CSR_MHPMCOUNTER9 0xb09 > +#define CSR_MHPMCOUNTER100xb0a > +#define CSR_MHPMCOUNTER110xb0b > +#define CSR_MHPMCOUNTER120xb0c > +#define CSR_MHPMCOUNTER130xb0d > +#define CSR_MHPMCOUNTER140xb0e > +#define CSR_MHPMCOUNTER150xb0f > +#define CSR_MHPMCOUNTER160xb10 > +#define CSR_MHPMCOUNTER170xb11 > +#define CSR_MHPMCOUNTER180xb12 > +#define CSR_MHPMCOUNTER190xb13 >
[U-Boot] [PATCH 10/19] riscv: Add CSR numbers
The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng --- arch/riscv/include/asm/encoding.h | 219 ++ 1 file changed, 219 insertions(+) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 9ea50ce..0c47c53 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -146,6 +146,225 @@ #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) +/* CSR numbers */ +#define CSR_FFLAGS 0x1 +#define CSR_FRM0x2 +#define CSR_FCSR 0x3 + +#define CSR_SSTATUS0x100 +#define CSR_SIE0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP0x144 +#define CSR_SATP 0x180 + +#define CSR_MSTATUS0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG0x302 +#define CSR_MIDELEG0x303 +#define CSR_MIE0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT100x32a +#define CSR_MHPMEVENT110x32b +#define CSR_MHPMEVENT120x32c +#define CSR_MHPMEVENT130x32d +#define CSR_MHPMEVENT140x32e +#define CSR_MHPMEVENT150x32f +#define CSR_MHPMEVENT160x330 +#define CSR_MHPMEVENT170x331 +#define CSR_MHPMEVENT180x332 +#define CSR_MHPMEVENT190x333 +#define CSR_MHPMEVENT200x334 +#define CSR_MHPMEVENT210x335 +#define CSR_MHPMEVENT220x336 +#define CSR_MHPMEVENT230x337 +#define CSR_MHPMEVENT240x338 +#define CSR_MHPMEVENT250x339 +#define CSR_MHPMEVENT260x33a +#define CSR_MHPMEVENT270x33b +#define CSR_MHPMEVENT280x33c +#define CSR_MHPMEVENT290x33d +#define CSR_MHPMEVENT300x33e +#define CSR_MHPMEVENT310x33f +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP0x344 +#define CSR_PMPCFG00x3a0 +#define CSR_PMPCFG10x3a1 +#define CSR_PMPCFG20x3a2 +#define CSR_PMPCFG30x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf + +#define CSR_TSELECT0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC0x7b1 +#define CSR_DSCRATCH 0x7b2 + +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c
