Re: [U-Boot] [PATCH 3/5] arm:imx-common introduce a new function to set gpr
Hi Peng,
On 11/1/2014 10:19 AM, Peng Fan wrote:
Add a new function mxc_iomux_set_gpr_register to
set the iomux gpr register.
32-bit general purpose registers according to SoC
requirements for any usage.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/imx-common/iomux-v3.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 22cd11a..b27aab8 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -77,3 +77,28 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const
*pad_list,
p += stride;
}
}
+
+/*
+ * Configure the IOMUX General Purpose Registers.
+ *
+ * @group, which gpr register to configure.
+ * @start_bit, the first bit to set
+ * @num_bits, how many bits to set
+ * @value, the value will be set to [start_bits...start_bits+num_bits-1]
+ */
+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,
+ int value)
+{
+ int i = 0;
+ u32 reg;
+
+ reg = readl(base + group * 4);
+ while (num_bits) {
+ reg = ~(1 (start_bit + i));
+ i++;
+ num_bits--;
+ }
+
+ reg |= (value start_bit);
+ writel(reg, base + group * 4);
+}
This function is already in my previous patch
(http://patchwork.ozlabs.org/patch/405013/). The function name is changed to
imx_iomux_set_gpr_register.
Best regards,
Ye Li
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Re: [U-Boot] [PATCH 3/5] arm:imx-common introduce a new function to set gpr
On 11/01/2014 03:39 PM, Li Ye-B37916 wrote:
Hi Peng,
On 11/1/2014 10:19 AM, Peng Fan wrote:
Add a new function mxc_iomux_set_gpr_register to
set the iomux gpr register.
32-bit general purpose registers according to SoC
requirements for any usage.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/imx-common/iomux-v3.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 22cd11a..b27aab8 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -77,3 +77,28 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t
const *pad_list,
p += stride;
}
}
+
+/*
+ * Configure the IOMUX General Purpose Registers.
+ *
+ * @group, which gpr register to configure.
+ * @start_bit, the first bit to set
+ * @num_bits, how many bits to set
+ * @value, the value will be set to [start_bits...start_bits+num_bits-1]
+ */
+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,
+int value)
+{
+int i = 0;
+u32 reg;
+
+reg = readl(base + group * 4);
+while (num_bits) {
+reg = ~(1 (start_bit + i));
+i++;
+num_bits--;
+}
+
+reg |= (value start_bit);
+writel(reg, base + group * 4);
+}
This function is already in my previous patch
(http://patchwork.ozlabs.org/patch/405013/). The function name is changed to
imx_iomux_set_gpr_register.
oh. I missed this piece of code.
Then please ignore this patch set. Sorry for troubles.
Regards,
Peng.
Best regards,
Ye Li
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Re: [U-Boot] [PATCH 3/5] arm:imx-common introduce a new function to set gpr
Dear Peng Fan, In message 1414808359-4750-4-git-send-email-peng@freescale.com you wrote: Add a new function mxc_iomux_set_gpr_register to set the iomux gpr register. 32-bit general purpose registers according to SoC requirements for any usage. ... +/* + * Configure the IOMUX General Purpose Registers. + * + * @group, which gpr register to configure. + * @start_bit, the first bit to set + * @num_bits, how many bits to set + * @value, the value will be set to [start_bits...start_bits+num_bits-1] + */ Can you please rework the API and use a mask instead of counting bits? Relying on bit numbers is error prone and inherently non-portable. Use the standard register access macros (like setbits, clrbits, clrsetbits) as example, please. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de All I ask is a chance to prove that money can't make me happy. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] arm:imx-common introduce a new function to set gpr
Add a new function mxc_iomux_set_gpr_register to
set the iomux gpr register.
32-bit general purpose registers according to SoC
requirements for any usage.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
arch/arm/imx-common/iomux-v3.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 22cd11a..b27aab8 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -77,3 +77,28 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const
*pad_list,
p += stride;
}
}
+
+/*
+ * Configure the IOMUX General Purpose Registers.
+ *
+ * @group, which gpr register to configure.
+ * @start_bit, the first bit to set
+ * @num_bits, how many bits to set
+ * @value, the value will be set to [start_bits...start_bits+num_bits-1]
+ */
+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,
+ int value)
+{
+ int i = 0;
+ u32 reg;
+
+ reg = readl(base + group * 4);
+ while (num_bits) {
+ reg = ~(1 (start_bit + i));
+ i++;
+ num_bits--;
+ }
+
+ reg |= (value start_bit);
+ writel(reg, base + group * 4);
+}
--
1.8.4.5
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