Re: [U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
Hi Stefan, On Sat, 6 Sep 2014 19:47:06 +0200, Stefan Agner ste...@agner.ch wrote: From: Anthony Felice tony.fel...@timesys.com Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice tony.fel...@timesys.com [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner ste...@agner.ch --- As discuessed in the initial patch set this fixes a lot of wrong/ undocummented access and it would be nice to have in the next U-Boot release. Verified the patchset after rebase again using memtester on Vybrid Tower. arch/arm/include/asm/arch-vf610/imx-regs.h| 49 +++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- arch/arm/include/asm/imx-common/iomux-v3.h| 2 + board/freescale/vf610twr/vf610twr.c | 94 +-- 4 files changed, 127 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index bb00217..9d797db 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x2613 #define DDRMC_PHY_DQS_TIMING 0x2615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x0021 #define DDRMC_PHY_MASTER_CTRL0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x2000 +#define DDRMC_PHY_OFF0x +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE(1 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 8) @@ -138,7 +140,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) 0x3f) 16) #define DDRMC_CR23_BSTLEN(v) (((v) 0x7) 24) -#define DDRMC_CR23_TDLL(v) ((v) 0xff) +#define DDRMC_CR23_TDLL(v) ((v) 0x) #define DDRMC_CR24_TRP_AB(v) ((v) 0x1f) #define DDRMC_CR25_TREF_EN (1 16) #define DDRMC_CR26_TREF(v) (((v) 0x) 16) @@ -151,7 +153,7 @@ #define DDRMC_CR33_EN_QK_SREF(1 16) #define DDRMC_CR34_CKSRX(v) (((v) 0xf) 16) #define DDRMC_CR34_CKSRE(v) (((v) 0xf) 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 8) +#define DDRMC_CR38_FREQ_CHG_EN(v)(((v) 0x1) 8) #define DDRMC_CR39_PHY_INI_COM(v)(((v) 0x) 16) #define DDRMC_CR39_PHY_INI_STA(v)(((v) 0xff) 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) 0x3) @@ -163,7 +165,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) 0xf) 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 24) +#define DDRMC_CR72_ZQCS_ROTATE(v)(((v) 0x1) 24) #define DDRMC_CR73_APREBIT(v)(((v) 0xf) 24) #define DDRMC_CR73_COL_DIFF(v) (((v) 0x7) 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) 0x3) 8) @@ -182,9 +184,10 @@ #define DDRMC_CR77_CS_MAP(1 24) #define DDRMC_CR77_DI_RD_INTLEAVE(1 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) 0x7) 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 24) -#define DDRMC_CR82_INT_MASK 0x1fff +#define DDRMC_CR79_CTLUPD_AREF(v)(((v) 0x1) 24) +#define DDRMC_CR82_INT_MASK 0x1000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) 0x1f) 16) @@ -192,9 +195,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) 0x7) 16) #define DDRMC_CR96_WLMRD(v) (((v) 0x3f) 8) #define DDRMC_CR96_WLDQSEN(v)((v) 0x3f)
Re: [U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
Hi Stefan, On Thu, 02 Oct 2014 09:09:48 +0200, Stefan Agner ste...@agner.ch wrote: Am 2014-09-09 17:19, schrieb Stefano Babic: Hi Stefan, Albert, On 09/09/2014 17:14, Stefan Agner wrote: Hi Albert, The RESEND version of the patch is actually an updated version (maybe I should have increased the version number?) For me, that patch applies cleanly on U-Boot master 0b703dbcee7103f07804d0a4328d1593355c4324 patman: Fix detection of git version Also I tested on U-Boot ARM master and next branch, applies without errors for me. I have tried myself and I can confirm that patch can be applied fine. Albert, should I apply it to u-boot-imx (vf610twr is part of iMX) and then send it in my next PR ? I guess this would be the correct path to go. Any chance this still makes into 2014.10? Sorry, for some reason this thread has escaped me. If the patch applies I will take it directly. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
Am 2014-09-09 17:19, schrieb Stefano Babic: Hi Stefan, Albert, On 09/09/2014 17:14, Stefan Agner wrote: Hi Albert, The RESEND version of the patch is actually an updated version (maybe I should have increased the version number?) For me, that patch applies cleanly on U-Boot master 0b703dbcee7103f07804d0a4328d1593355c4324 patman: Fix detection of git version Also I tested on U-Boot ARM master and next branch, applies without errors for me. I have tried myself and I can confirm that patch can be applied fine. Albert, should I apply it to u-boot-imx (vf610twr is part of iMX) and then send it in my next PR ? I guess this would be the correct path to go. Any chance this still makes into 2014.10? -- Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
Hi Stefan, On Sat, 6 Sep 2014 19:47:06 +0200, Stefan Agner ste...@agner.ch wrote: From: Anthony Felice tony.fel...@timesys.com Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice tony.fel...@timesys.com [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner ste...@agner.ch --- As discuessed in the initial patch set this fixes a lot of wrong/ undocummented access and it would be nice to have in the next U-Boot release. Verified the patchset after rebase again using memtester on Vybrid Tower. arch/arm/include/asm/arch-vf610/imx-regs.h| 49 +++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- arch/arm/include/asm/imx-common/iomux-v3.h| 2 + board/freescale/vf610twr/vf610twr.c | 94 +-- 4 files changed, 127 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index bb00217..9d797db 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x2613 #define DDRMC_PHY_DQS_TIMING 0x2615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x0021 #define DDRMC_PHY_MASTER_CTRL0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x2000 +#define DDRMC_PHY_OFF0x +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE(1 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 8) @@ -138,7 +140,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) 0x3f) 16) #define DDRMC_CR23_BSTLEN(v) (((v) 0x7) 24) -#define DDRMC_CR23_TDLL(v) ((v) 0xff) +#define DDRMC_CR23_TDLL(v) ((v) 0x) #define DDRMC_CR24_TRP_AB(v) ((v) 0x1f) #define DDRMC_CR25_TREF_EN (1 16) #define DDRMC_CR26_TREF(v) (((v) 0x) 16) @@ -151,7 +153,7 @@ #define DDRMC_CR33_EN_QK_SREF(1 16) #define DDRMC_CR34_CKSRX(v) (((v) 0xf) 16) #define DDRMC_CR34_CKSRE(v) (((v) 0xf) 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 8) +#define DDRMC_CR38_FREQ_CHG_EN(v)(((v) 0x1) 8) #define DDRMC_CR39_PHY_INI_COM(v)(((v) 0x) 16) #define DDRMC_CR39_PHY_INI_STA(v)(((v) 0xff) 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) 0x3) @@ -163,7 +165,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) 0xf) 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 24) +#define DDRMC_CR72_ZQCS_ROTATE(v)(((v) 0x1) 24) #define DDRMC_CR73_APREBIT(v)(((v) 0xf) 24) #define DDRMC_CR73_COL_DIFF(v) (((v) 0x7) 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) 0x3) 8) @@ -182,9 +184,10 @@ #define DDRMC_CR77_CS_MAP(1 24) #define DDRMC_CR77_DI_RD_INTLEAVE(1 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) 0x7) 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 24) -#define DDRMC_CR82_INT_MASK 0x1fff +#define DDRMC_CR79_CTLUPD_AREF(v)(((v) 0x1) 24) +#define DDRMC_CR82_INT_MASK 0x1000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) 0x1f) 16) @@ -192,9 +195,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) 0x7) 16) #define DDRMC_CR96_WLMRD(v) (((v) 0x3f) 8) #define DDRMC_CR96_WLDQSEN(v)((v) 0x3f)
Re: [U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
Hi Albert, The RESEND version of the patch is actually an updated version (maybe I should have increased the version number?) For me, that patch applies cleanly on U-Boot master 0b703dbcee7103f07804d0a4328d1593355c4324 patman: Fix detection of git version Also I tested on U-Boot ARM master and next branch, applies without errors for me. -- Stefan Am 2014-09-09 10:26, schrieb Albert ARIBAUD: Hi Stefan, On Sat, 6 Sep 2014 19:47:06 +0200, Stefan Agner ste...@agner.ch wrote: From: Anthony Felice tony.fel...@timesys.com Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice tony.fel...@timesys.com [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner ste...@agner.ch --- As discuessed in the initial patch set this fixes a lot of wrong/ undocummented access and it would be nice to have in the next U-Boot release. Verified the patchset after rebase again using memtester on Vybrid Tower. arch/arm/include/asm/arch-vf610/imx-regs.h| 49 +++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- arch/arm/include/asm/imx-common/iomux-v3.h| 2 + board/freescale/vf610twr/vf610twr.c | 94 +-- 4 files changed, 127 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index bb00217..9d797db 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x2613 #define DDRMC_PHY_DQS_TIMING0x2615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x0021 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL0x00012020 +#define DDRMC_PHY_SLAVE_CTRL0x2000 +#define DDRMC_PHY_OFF 0x +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE (1 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE(1 8) @@ -138,7 +140,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) 0x3f) 16) #define DDRMC_CR23_BSTLEN(v)(((v) 0x7) 24) -#define DDRMC_CR23_TDLL(v) ((v) 0xff) +#define DDRMC_CR23_TDLL(v) ((v) 0x) #define DDRMC_CR24_TRP_AB(v)((v) 0x1f) #define DDRMC_CR25_TREF_EN (1 16) #define DDRMC_CR26_TREF(v) (((v) 0x) 16) @@ -151,7 +153,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 16) #define DDRMC_CR34_CKSRX(v) (((v) 0xf) 16) #define DDRMC_CR34_CKSRE(v) (((v) 0xf) 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) 0x1) 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) 0x) 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) 0xff) 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) 0x3) @@ -163,7 +165,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) 0xf) 8) #define DDRMC_CR70_REF_PER_ZQ(v)(v) -#define DDRMC_CR72_ZQCS_ROTATE (1 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) 0x1) 24) #define DDRMC_CR73_APREBIT(v) (((v) 0xf) 24) #define DDRMC_CR73_COL_DIFF(v) (((v) 0x7) 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) 0x3) 8) @@ -182,9 +184,10 @@ #define DDRMC_CR77_CS_MAP (1 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v)(((v) 0x7) 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v)((v) 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 24) -#define DDRMC_CR82_INT_MASK 0x1fff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) 0x1) 24) +#define DDRMC_CR82_INT_MASK 0x1000 #define DDRMC_CR87_ODT_WR_MAPCS0
Re: [U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
Hi Stefan, Albert, On 09/09/2014 17:14, Stefan Agner wrote: Hi Albert, The RESEND version of the patch is actually an updated version (maybe I should have increased the version number?) For me, that patch applies cleanly on U-Boot master 0b703dbcee7103f07804d0a4328d1593355c4324 patman: Fix detection of git version Also I tested on U-Boot ARM master and next branch, applies without errors for me. I have tried myself and I can confirm that patch can be applied fine. Albert, should I apply it to u-boot-imx (vf610twr is part of iMX) and then send it in my next PR ? Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
From: Anthony Felice tony.fel...@timesys.com Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice tony.fel...@timesys.com [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner ste...@agner.ch --- As discuessed in the initial patch set this fixes a lot of wrong/ undocummented access and it would be nice to have in the next U-Boot release. Verified the patchset after rebase again using memtester on Vybrid Tower. arch/arm/include/asm/arch-vf610/imx-regs.h| 49 +++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- arch/arm/include/asm/imx-common/iomux-v3.h| 2 + board/freescale/vf610twr/vf610twr.c | 94 +-- 4 files changed, 127 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index bb00217..9d797db 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING0x2613 #define DDRMC_PHY_DQS_TIMING 0x2615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x0021 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x2000 +#define DDRMC_PHY_OFF 0x +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE (1 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 8) @@ -138,7 +140,7 @@ #define DDRMC_CR21_CCMAP_EN1 #define DDRMC_CR22_TDAL(v) (((v) 0x3f) 16) #define DDRMC_CR23_BSTLEN(v) (((v) 0x7) 24) -#define DDRMC_CR23_TDLL(v) ((v) 0xff) +#define DDRMC_CR23_TDLL(v) ((v) 0x) #define DDRMC_CR24_TRP_AB(v) ((v) 0x1f) #define DDRMC_CR25_TREF_EN (1 16) #define DDRMC_CR26_TREF(v) (((v) 0x) 16) @@ -151,7 +153,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 16) #define DDRMC_CR34_CKSRX(v)(((v) 0xf) 16) #define DDRMC_CR34_CKSRE(v)(((v) 0xf) 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) 0x1) 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) 0x) 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) 0xff) 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v)((v) 0x3) @@ -163,7 +165,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v)(((v) 0xf) 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) 0x1) 24) #define DDRMC_CR73_APREBIT(v) (((v) 0xf) 24) #define DDRMC_CR73_COL_DIFF(v) (((v) 0x7) 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) 0x3) 8) @@ -182,9 +184,10 @@ #define DDRMC_CR77_CS_MAP (1 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) 0x7) 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 24) -#define DDRMC_CR82_INT_MASK0x1fff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) 0x1) 24) +#define DDRMC_CR82_INT_MASK0x1000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 16) #define DDRMC_CR88_TODTL_CMD(v)(((v) 0x1f) 16) @@ -192,9 +195,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) 0x7) 16) #define DDRMC_CR96_WLMRD(v)(((v) 0x3f) 8) #define DDRMC_CR96_WLDQSEN(v) ((v) 0x3f) +#define DDRMC_CR97_WRLVL_EN(1 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define
