Re: [U-Boot] [PATCH u-boot] spi: Add Amlogic Meson SPI Flash Controller driver
Neil, I just saw that you found a bug and you will send a v2 patch, so I will retest it with the new version. On 11/21/18 12:45 AM, Loic Devulder wrote: > Hi Neil, > > I was able to detect the W25Q16FW SPI flash of my Khadas VIM2 with your > patch: > => sspi > SF: Detected w25q16dw with page size 256 Bytes, erase size 4 KiB, total > 2 MiB > > => sf probe > SF: Detected w25q16dw with page size 256 Bytes, erase size 4 KiB, total > 2 MiB > > So, you can add a "Tested-by: Loic Devulder " :) > > On 11/6/18 10:25 AM, Neil Armstrong wrote: >> The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. >> This driver, ported from the Linux meson-spi-spifc driver, add support >> for this controller on the Amlogic Meson GX SoCs in U-Boot. >> >> Signed-off-by: Neil Armstrong [ ... ] -- Loic Devulder | ldevulder@irc 0x175A963893C85F55 | D220 DEF5 56A3 DE00 9DAA 78BA 175A 9638 93C8 5F55 Senior QA Engineer | Container & Storage Solutions Quality Assurance team (qa-css) SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nuernberg, Germany GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton HRB, 21284 (AG Nuernberg) signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot] spi: Add Amlogic Meson SPI Flash Controller driver
Hi Neil,
I was able to detect the W25Q16FW SPI flash of my Khadas VIM2 with your
patch:
=> sspi
SF: Detected w25q16dw with page size 256 Bytes, erase size 4 KiB, total
2 MiB
=> sf probe
SF: Detected w25q16dw with page size 256 Bytes, erase size 4 KiB, total
2 MiB
So, you can add a "Tested-by: Loic Devulder " :)
On 11/6/18 10:25 AM, Neil Armstrong wrote:
> The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC.
> This driver, ported from the Linux meson-spi-spifc driver, add support
> for this controller on the Amlogic Meson GX SoCs in U-Boot.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/meson_spifc.c | 368
> ++
> 3 files changed, 377 insertions(+)
> create mode 100644 drivers/spi/meson_spifc.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 516188e..838a007 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -116,6 +116,14 @@ config ICH_SPI
> access the SPI NOR flash on platforms embedding this Intel
> ICH IP core.
>
> +config MESON_SPIFC
> + bool "Amlogic Meson SPI Flash Controller driver"
> + depends on ARCH_MESON
> + help
> + Enable the Amlogic Meson SPI Flash Controller SPIFC) driver.
> + This driver can be used to access the SPI NOR flash chips on
> + Amlogic Meson SoCs.
> +
> config MT7621_SPI
> bool "MediaTek MT7621 SPI driver"
> depends on ARCH_MT7620
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 7242ea7..67b42da 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -31,6 +31,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
> obj-$(CONFIG_ICH_SPI) += ich.o
> obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
> obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
> +obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
> obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
> obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
> diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c
> new file mode 100644
> index 000..6fd3d1a
> --- /dev/null
> +++ b/drivers/spi/meson_spifc.c
> @@ -0,0 +1,368 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2014 Beniamino Galvani
> + * Copyright (C) 2018 BayLibre, SAS
> + * Author: Neil Armstrong
> + *
> + * Amlogic Meson SPI Flash Controller driver
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* register map */
> +#define REG_CMD 0x00
> +#define REG_ADDR 0x04
> +#define REG_CTRL 0x08
> +#define REG_CTRL10x0c
> +#define REG_STATUS 0x10
> +#define REG_CTRL20x14
> +#define REG_CLOCK0x18
> +#define REG_USER 0x1c
> +#define REG_USER10x20
> +#define REG_USER20x24
> +#define REG_USER30x28
> +#define REG_USER40x2c
> +#define REG_SLAVE0x30
> +#define REG_SLAVE1 0x34
> +#define REG_SLAVE2 0x38
> +#define REG_SLAVE3 0x3c
> +#define REG_C0 0x40
> +#define REG_B8 0x60
> +#define REG_MAX 0x7c
> +
> +/* register fields */
> +#define CMD_USER BIT(18)
> +#define CTRL_ENABLE_AHB BIT(17)
> +#define CLOCK_SOURCE BIT(31)
> +#define CLOCK_DIV_SHIFT 12
> +#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
> +#define CLOCK_CNT_HIGH_SHIFT 6
> +#define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
> +#define CLOCK_CNT_LOW_SHIFT 0
> +#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
> +#define USER_DIN_EN_MS BIT(0)
> +#define USER_CMP_MODEBIT(2)
> +#define USER_CLK_NOT_INV BIT(7)
> +#define USER_UC_DOUT_SEL BIT(27)
> +#define USER_UC_DIN_SEL BIT(28)
> +#define USER_UC_MASK ((BIT(5) - 1) << 27)
> +#define USER1_BN_UC_DOUT_SHIFT 17
> +#define USER1_BN_UC_DOUT_MASK(0xff << 16)
> +#define USER1_BN_UC_DIN_SHIFT8
> +#define USER1_BN_UC_DIN_MASK (0xff << 8)
> +#define USER4_CS_POL_HIGHBIT(23)
> +#define USER4_IDLE_CLK_HIGH BIT(29)
> +#define USER4_CS_ACT BIT(30)
> +#define SLAVE_TRST_DONE BIT(4)
> +#define SLAVE_OP_MODEBIT(30)
> +#define SLAVE_SW_RST BIT(31)
> +
> +#define SPIFC_BUFFER_SIZE64
> +
> +struct meson_spifc_priv {
> + struct regmap *regmap;
> + struct clk clk;
> +};
> +
> +/**
> + * meson_spifc_wait_ready() - wait for the current operation to terminate
> + * @spifc: the Meson SPI device
> + * Return: 0 on success, a negative value on error
> + */
> +static int meson_spifc_wait_ready(struct meson_spifc_priv *spifc)
> +{
> + u32 data;
> + ulong tbase = get_timer(0);
> +
> + do {
Re: [U-Boot] [PATCH u-boot] spi: Add Amlogic Meson SPI Flash Controller driver
Dear Neil, In message <7206f5df-626e-a367-8933-4e6afb64a...@baylibre.com> you wrote: > > On 06/11/2018 10:25, Neil Armstrong wrote: > > The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. > > This driver, ported from the Linux meson-spi-spifc driver, add support > > for this controller on the Amlogic Meson GX SoCs in U-Boot. > > I found a bug in this driver, I'll send a v2 fixing it. Then please also fix attribution. See especially bullet # 4 at http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign Thanks. Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Cleverness and Style have no place in getting a project completed. -- Tom Christiansen ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot] spi: Add Amlogic Meson SPI Flash Controller driver
Hi,
On 06/11/2018 10:25, Neil Armstrong wrote:
> The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC.
> This driver, ported from the Linux meson-spi-spifc driver, add support
> for this controller on the Amlogic Meson GX SoCs in U-Boot.
I found a bug in this driver, I'll send a v2 fixing it.
Neil
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/meson_spifc.c | 368
> ++
> 3 files changed, 377 insertions(+)
> create mode 100644 drivers/spi/meson_spifc.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 516188e..838a007 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -116,6 +116,14 @@ config ICH_SPI
> access the SPI NOR flash on platforms embedding this Intel
> ICH IP core.
>
> +config MESON_SPIFC
> + bool "Amlogic Meson SPI Flash Controller driver"
> + depends on ARCH_MESON
> + help
> + Enable the Amlogic Meson SPI Flash Controller SPIFC) driver.
> + This driver can be used to access the SPI NOR flash chips on
> + Amlogic Meson SoCs.
> +
> config MT7621_SPI
> bool "MediaTek MT7621 SPI driver"
> depends on ARCH_MT7620
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 7242ea7..67b42da 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -31,6 +31,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
> obj-$(CONFIG_ICH_SPI) += ich.o
> obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
> obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
> +obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
> obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
> obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
> diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c
> new file mode 100644
> index 000..6fd3d1a
> --- /dev/null
> +++ b/drivers/spi/meson_spifc.c
> @@ -0,0 +1,368 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2014 Beniamino Galvani
> + * Copyright (C) 2018 BayLibre, SAS
> + * Author: Neil Armstrong
> + *
> + * Amlogic Meson SPI Flash Controller driver
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* register map */
> +#define REG_CMD 0x00
> +#define REG_ADDR 0x04
> +#define REG_CTRL 0x08
> +#define REG_CTRL10x0c
> +#define REG_STATUS 0x10
> +#define REG_CTRL20x14
> +#define REG_CLOCK0x18
> +#define REG_USER 0x1c
> +#define REG_USER10x20
> +#define REG_USER20x24
> +#define REG_USER30x28
> +#define REG_USER40x2c
> +#define REG_SLAVE0x30
> +#define REG_SLAVE1 0x34
> +#define REG_SLAVE2 0x38
> +#define REG_SLAVE3 0x3c
> +#define REG_C0 0x40
> +#define REG_B8 0x60
> +#define REG_MAX 0x7c
> +
> +/* register fields */
> +#define CMD_USER BIT(18)
> +#define CTRL_ENABLE_AHB BIT(17)
> +#define CLOCK_SOURCE BIT(31)
> +#define CLOCK_DIV_SHIFT 12
> +#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
> +#define CLOCK_CNT_HIGH_SHIFT 6
> +#define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
> +#define CLOCK_CNT_LOW_SHIFT 0
> +#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
> +#define USER_DIN_EN_MS BIT(0)
> +#define USER_CMP_MODEBIT(2)
> +#define USER_CLK_NOT_INV BIT(7)
> +#define USER_UC_DOUT_SEL BIT(27)
> +#define USER_UC_DIN_SEL BIT(28)
> +#define USER_UC_MASK ((BIT(5) - 1) << 27)
> +#define USER1_BN_UC_DOUT_SHIFT 17
> +#define USER1_BN_UC_DOUT_MASK(0xff << 16)
> +#define USER1_BN_UC_DIN_SHIFT8
> +#define USER1_BN_UC_DIN_MASK (0xff << 8)
> +#define USER4_CS_POL_HIGHBIT(23)
> +#define USER4_IDLE_CLK_HIGH BIT(29)
> +#define USER4_CS_ACT BIT(30)
> +#define SLAVE_TRST_DONE BIT(4)
> +#define SLAVE_OP_MODEBIT(30)
> +#define SLAVE_SW_RST BIT(31)
> +
> +#define SPIFC_BUFFER_SIZE64
> +
> +struct meson_spifc_priv {
> + struct regmap *regmap;
> + struct clk clk;
> +};
> +
> +/**
> + * meson_spifc_wait_ready() - wait for the current operation to terminate
> + * @spifc: the Meson SPI device
> + * Return: 0 on success, a negative value on error
> + */
> +static int meson_spifc_wait_ready(struct meson_spifc_priv *spifc)
> +{
> + u32 data;
> + ulong tbase = get_timer(0);
> +
> + do {
> + regmap_read(spifc->regmap, REG_SLAVE, );
> + if (data & SLAVE_TRST_DONE)
> + return 0;
> + } while (get_timer(tbase) < 5 * CONFIG_SYS_HZ);
> +
> + return -ETIMEDOUT;
> +}
> +
> +/**
> + *
Re: [U-Boot] [PATCH u-boot] spi: Add Amlogic Meson SPI Flash Controller driver
On Tue, 2018-11-06 at 10:25 +0100, Neil Armstrong wrote: > The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. > This driver, ported from the Linux meson-spi-spifc driver, add support > for this controller on the Amlogic Meson GX SoCs in U-Boot. > > Signed-off-by: Neil Armstrong Tested-by: Jerome Brunet ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot] spi: Add Amlogic Meson SPI Flash Controller driver
The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC.
This driver, ported from the Linux meson-spi-spifc driver, add support
for this controller on the Amlogic Meson GX SoCs in U-Boot.
Signed-off-by: Neil Armstrong
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/meson_spifc.c | 368 ++
3 files changed, 377 insertions(+)
create mode 100644 drivers/spi/meson_spifc.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 516188e..838a007 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -116,6 +116,14 @@ config ICH_SPI
access the SPI NOR flash on platforms embedding this Intel
ICH IP core.
+config MESON_SPIFC
+ bool "Amlogic Meson SPI Flash Controller driver"
+ depends on ARCH_MESON
+ help
+ Enable the Amlogic Meson SPI Flash Controller SPIFC) driver.
+ This driver can be used to access the SPI NOR flash chips on
+ Amlogic Meson SoCs.
+
config MT7621_SPI
bool "MediaTek MT7621 SPI driver"
depends on ARCH_MT7620
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7242ea7..67b42da 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
+obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c
new file mode 100644
index 000..6fd3d1a
--- /dev/null
+++ b/drivers/spi/meson_spifc.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Beniamino Galvani
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong
+ *
+ * Amlogic Meson SPI Flash Controller driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* register map */
+#define REG_CMD0x00
+#define REG_ADDR 0x04
+#define REG_CTRL 0x08
+#define REG_CTRL1 0x0c
+#define REG_STATUS 0x10
+#define REG_CTRL2 0x14
+#define REG_CLOCK 0x18
+#define REG_USER 0x1c
+#define REG_USER1 0x20
+#define REG_USER2 0x24
+#define REG_USER3 0x28
+#define REG_USER4 0x2c
+#define REG_SLAVE 0x30
+#define REG_SLAVE1 0x34
+#define REG_SLAVE2 0x38
+#define REG_SLAVE3 0x3c
+#define REG_C0 0x40
+#define REG_B8 0x60
+#define REG_MAX0x7c
+
+/* register fields */
+#define CMD_USER BIT(18)
+#define CTRL_ENABLE_AHBBIT(17)
+#define CLOCK_SOURCE BIT(31)
+#define CLOCK_DIV_SHIFT12
+#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
+#define CLOCK_CNT_HIGH_SHIFT 6
+#define CLOCK_CNT_HIGH_MASK(0x3f << CLOCK_CNT_HIGH_SHIFT)
+#define CLOCK_CNT_LOW_SHIFT0
+#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
+#define USER_DIN_EN_MS BIT(0)
+#define USER_CMP_MODE BIT(2)
+#define USER_CLK_NOT_INV BIT(7)
+#define USER_UC_DOUT_SEL BIT(27)
+#define USER_UC_DIN_SELBIT(28)
+#define USER_UC_MASK ((BIT(5) - 1) << 27)
+#define USER1_BN_UC_DOUT_SHIFT 17
+#define USER1_BN_UC_DOUT_MASK (0xff << 16)
+#define USER1_BN_UC_DIN_SHIFT 8
+#define USER1_BN_UC_DIN_MASK (0xff << 8)
+#define USER4_CS_POL_HIGH BIT(23)
+#define USER4_IDLE_CLK_HIGHBIT(29)
+#define USER4_CS_ACT BIT(30)
+#define SLAVE_TRST_DONEBIT(4)
+#define SLAVE_OP_MODE BIT(30)
+#define SLAVE_SW_RST BIT(31)
+
+#define SPIFC_BUFFER_SIZE 64
+
+struct meson_spifc_priv {
+ struct regmap *regmap;
+ struct clk clk;
+};
+
+/**
+ * meson_spifc_wait_ready() - wait for the current operation to terminate
+ * @spifc: the Meson SPI device
+ * Return: 0 on success, a negative value on error
+ */
+static int meson_spifc_wait_ready(struct meson_spifc_priv *spifc)
+{
+ u32 data;
+ ulong tbase = get_timer(0);
+
+ do {
+ regmap_read(spifc->regmap, REG_SLAVE, );
+ if (data & SLAVE_TRST_DONE)
+ return 0;
+ } while (get_timer(tbase) < 5 * CONFIG_SYS_HZ);
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * meson_spifc_drain_buffer() - copy data from device buffer to memory
+ * @spifc: the Meson SPI device
+ * @buf: the destination buffer
+ * @len: number of bytes to copy
+ */
+static void meson_spifc_drain_buffer(struct meson_spifc_priv *spifc,
+u8 *buf, int len)
+{
+ u32 data;
+
