On 02/20/2017 03:07 PM, Dalon Westergreen wrote:
[...]
>>> Okay, after much discussion and debate with a colleague..\
>>>
>>> Warm reset is preferred as the bootrom keeps a score card to determine
>>> whether an spl image in the boot media failed or not. If it failed,
>>> on a warm reset it will
On Sun, 2017-02-19 at 22:31 +0100, Marek Vasut wrote:
> On 02/18/2017 12:24 AM, Dalon Westergreen wrote:
> >
> > On Fri, 2017-02-17 at 22:16 +0100, Marek Vasut wrote:
> > >
> > > On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
> > > >
> > > >
> > > > On Wed, 2017-02-15 at 18:53 -0800, Dalon
On 02/18/2017 12:24 AM, Dalon Westergreen wrote:
> On Fri, 2017-02-17 at 22:16 +0100, Marek Vasut wrote:
>> On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
>>>
>>> On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
>
On Fri, 2017-02-17 at 22:16 +0100, Marek Vasut wrote:
> On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
> >
> > On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
> > >
> > > On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> > > >
> > > >
> > > > On 02/15/2017 10:48 PM, Dalon
On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
> On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
>> On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
>>>
>>> On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
> On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> >
> > On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> > >
> > >
> > > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > > >
> > > >
> > > > On 02/14/2017 07:28 PM,
On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> >
> > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > >
> > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > > >
> > > >
> > > > When CSEL=0x0 the socfpga bootrom does not
On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
>> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
>>>
>>> When CSEL=0x0 the socfpga bootrom does not touch the clock
>>> configuration for the device. This can lead to a boot failure
>>> on
On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> >
> > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > configuration for the device. This can lead to a boot failure
> > on warm resets. To address this, the bootrom is
On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> When CSEL=0x0 the socfpga bootrom does not touch the clock
> configuration for the device. This can lead to a boot failure
> on warm resets. To address this, the bootrom is configured to
> run a bit of code in the last 4KB of onchip ram on a
On 02/15/2017 07:56 AM, Chin Liang See wrote:
> On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote:
>> When CSEL=0x0 the socfpga bootrom does not touch the clock
>> configuration for the device. This can lead to a boot failure
>> on warm resets. To address this, the bootrom is configured
On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote:
> When CSEL=0x0 the socfpga bootrom does not touch the clock
> configuration for the device. This can lead to a boot failure
> on warm resets. To address this, the bootrom is configured to
> run a bit of code in the last 4KB of onchip
When CSEL=0x0 the socfpga bootrom does not touch the clock
configuration for the device. This can lead to a boot failure
on warm resets. To address this, the bootrom is configured to
run a bit of code in the last 4KB of onchip ram on a warm reset.
This code puts the PLLs in bypass, disables the
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