Re: [U-Boot] [PATCH v5 2/5] net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
On 09/07/19 3:52 AM, Joe Hershberger wrote:
On Thu, Jun 6, 2019 at 7:14 AM Keerthy wrote:
From: Grygorii Strashko
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
Independent Interface (RMII), and the Management Data Input/Output (MDIO)
interface for physical layer device (PHY) management. The TI AM65x SoC has
integrated two-port Gigabit Ethernet Switch subsystem into device MCU
domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII
and RMII interfaces and an internal Communications Port Programming
Interface (CPPI) port (Host port 0).
Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX
channels and on RX channels operating by TI am654 NAVSS Unified DMA
Peripheral Root Complex (UDMA-P) controller.
Signed-off-by: Grygorii Strashko
Signed-off-by: Keerthy
---
drivers/net/ti/Kconfig | 8 +
drivers/net/ti/Makefile | 1 +
drivers/net/ti/am65-cpsw-nuss.c | 794
3 files changed, 803 insertions(+)
create mode 100644 drivers/net/ti/am65-cpsw-nuss.c
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 82bc9f5d03..ecf642de10 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -18,3 +18,11 @@ config DRIVER_TI_KEYSTONE_NET
bool "TI Keystone 2 Ethernet"
help
This driver supports the TI Keystone 2 Ethernet subsystem
+
+config TI_AM65_CPSW_NUSS
+ bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver"
+ depends on ARCH_K3
+ select PHYLIB
+ help
+ This driver supports TI K3 MCU CPSW Nuss Ethernet controller
+ in Texas Instruments K3 AM65x SoCs.
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index ee3e4eb5d6..8d3808bb4b 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
+obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
new file mode 100644
index 00..658cc34033
--- /dev/null
+++ b/drivers/net/ti/am65-cpsw-nuss.c
[ ... ]
+static const struct eth_ops am65_cpsw_ops = {
+ .start = am65_cpsw_start,
+ .send = am65_cpsw_send,
+ .recv = am65_cpsw_recv,
+ .free_pkt = am65_cpsw_free_pkt,
+ .stop = am65_cpsw_stop,
+ .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
I'm surprised that write_hwaddr is not included.
This driver is pretty much based on cpsw.c under drivers/net/ti.
I believe there is no mandate to write the hw mac address to specific IP
register.
+};
+
+static int am65_cpsw_mdio_init(struct udevice *dev)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
+
+ if (!priv->has_phy || cpsw_common->bus)
+ return 0;
+
+ cpsw_common->bus = cpsw_mdio_init(dev->name,
+ cpsw_common->mdio_base,
+ cpsw_common->bus_freq,
+ clk_get_rate(_common->fclk));
+ if (!cpsw_common->bus)
+ return -EFAULT;
+
+ return 0;
+}
+
+static int am65_cpsw_phy_init(struct udevice *dev)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct phy_device *phydev;
+ u32 supported = PHY_GBIT_FEATURES;
+ int ret;
+
+ phydev = phy_connect(cpsw_common->bus,
+priv->phy_addr,
+priv->dev,
+pdata->phy_interface);
+
+ if (!phydev) {
+ dev_err(dev, "phy_connect() failed\n");
+ return -ENODEV;
+ }
+
+ phydev->supported &= supported;
+ if (pdata->max_speed) {
+ ret = phy_set_supported(phydev, pdata->max_speed);
+ if (ret)
+ return ret;
+ }
+ phydev->advertising = phydev->supported;
+
+#ifdef CONFIG_DM_ETH
Why is this needed? I would expect this to already be assumed.
Yes. This is redundant.
+ if (ofnode_valid(priv->phy_node))
+ phydev->node = priv->phy_node;
+#endif
+
+ priv->phydev = phydev;
+ ret = phy_config(phydev);
+ if (ret < 0)
+ pr_err("phy_config() failed: %d", ret);
+
+ return ret;
+}
+
+static int am65_cpsw_ofdata_parse_phy(struct udevice
Re: [U-Boot] [PATCH v5 2/5] net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
On Thu, Jun 6, 2019 at 7:14 AM Keerthy wrote:
>
> From: Grygorii Strashko
>
> Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
> NUSS). It has two ports and provides Ethernet packet communication for the
> device and can be configured as an Ethernet switch. CPSW NUSS features: the
> Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
> Independent Interface (RMII), and the Management Data Input/Output (MDIO)
> interface for physical layer device (PHY) management. The TI AM65x SoC has
> integrated two-port Gigabit Ethernet Switch subsystem into device MCU
> domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII
> and RMII interfaces and an internal Communications Port Programming
> Interface (CPPI) port (Host port 0).
>
> Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX
> channels and on RX channels operating by TI am654 NAVSS Unified DMA
> Peripheral Root Complex (UDMA-P) controller.
>
> Signed-off-by: Grygorii Strashko
> Signed-off-by: Keerthy
> ---
> drivers/net/ti/Kconfig | 8 +
> drivers/net/ti/Makefile | 1 +
> drivers/net/ti/am65-cpsw-nuss.c | 794
> 3 files changed, 803 insertions(+)
> create mode 100644 drivers/net/ti/am65-cpsw-nuss.c
>
> diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
> index 82bc9f5d03..ecf642de10 100644
> --- a/drivers/net/ti/Kconfig
> +++ b/drivers/net/ti/Kconfig
> @@ -18,3 +18,11 @@ config DRIVER_TI_KEYSTONE_NET
> bool "TI Keystone 2 Ethernet"
> help
>This driver supports the TI Keystone 2 Ethernet subsystem
> +
> +config TI_AM65_CPSW_NUSS
> + bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver"
> + depends on ARCH_K3
> + select PHYLIB
> + help
> + This driver supports TI K3 MCU CPSW Nuss Ethernet controller
> + in Texas Instruments K3 AM65x SoCs.
> diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
> index ee3e4eb5d6..8d3808bb4b 100644
> --- a/drivers/net/ti/Makefile
> +++ b/drivers/net/ti/Makefile
> @@ -5,3 +5,4 @@
> obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
> obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
> obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
> +obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> new file mode 100644
> index 00..658cc34033
> --- /dev/null
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
[ ... ]
> +static const struct eth_ops am65_cpsw_ops = {
> + .start = am65_cpsw_start,
> + .send = am65_cpsw_send,
> + .recv = am65_cpsw_recv,
> + .free_pkt = am65_cpsw_free_pkt,
> + .stop = am65_cpsw_stop,
> + .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
I'm surprised that write_hwaddr is not included.
> +};
> +
> +static int am65_cpsw_mdio_init(struct udevice *dev)
> +{
> + struct am65_cpsw_priv *priv = dev_get_priv(dev);
> + struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
> +
> + if (!priv->has_phy || cpsw_common->bus)
> + return 0;
> +
> + cpsw_common->bus = cpsw_mdio_init(dev->name,
> + cpsw_common->mdio_base,
> + cpsw_common->bus_freq,
> + clk_get_rate(_common->fclk));
> + if (!cpsw_common->bus)
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> +static int am65_cpsw_phy_init(struct udevice *dev)
> +{
> + struct am65_cpsw_priv *priv = dev_get_priv(dev);
> + struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
> + struct eth_pdata *pdata = dev_get_platdata(dev);
> + struct phy_device *phydev;
> + u32 supported = PHY_GBIT_FEATURES;
> + int ret;
> +
> + phydev = phy_connect(cpsw_common->bus,
> +priv->phy_addr,
> +priv->dev,
> +pdata->phy_interface);
> +
> + if (!phydev) {
> + dev_err(dev, "phy_connect() failed\n");
> + return -ENODEV;
> + }
> +
> + phydev->supported &= supported;
> + if (pdata->max_speed) {
> + ret = phy_set_supported(phydev, pdata->max_speed);
> + if (ret)
> + return ret;
> + }
> + phydev->advertising = phydev->supported;
> +
> +#ifdef CONFIG_DM_ETH
Why is this needed? I would expect this to already be assumed.
> + if (ofnode_valid(priv->phy_node))
> + phydev->node = priv->phy_node;
> +#endif
> +
> + priv->phydev = phydev;
> + ret = phy_config(phydev);
> + if (ret < 0)
> + pr_err("phy_config() failed: %d", ret);
> +
> + return ret;
> +}
> +
> +static int am65_cpsw_ofdata_parse_phy(struct udevice
[U-Boot] [PATCH v5 2/5] net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
From: Grygorii Strashko Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: Grygorii Strashko Signed-off-by: Keerthy --- drivers/net/ti/Kconfig | 8 + drivers/net/ti/Makefile | 1 + drivers/net/ti/am65-cpsw-nuss.c | 794 3 files changed, 803 insertions(+) create mode 100644 drivers/net/ti/am65-cpsw-nuss.c diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 82bc9f5d03..ecf642de10 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -18,3 +18,11 @@ config DRIVER_TI_KEYSTONE_NET bool "TI Keystone 2 Ethernet" help This driver supports the TI Keystone 2 Ethernet subsystem + +config TI_AM65_CPSW_NUSS + bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" + depends on ARCH_K3 + select PHYLIB + help + This driver supports TI K3 MCU CPSW Nuss Ethernet controller + in Texas Instruments K3 AM65x SoCs. diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile index ee3e4eb5d6..8d3808bb4b 100644 --- a/drivers/net/ti/Makefile +++ b/drivers/net/ti/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o +obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c new file mode 100644 index 00..658cc34033 --- /dev/null +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -0,0 +1,794 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver + * + * Copyright (C) 2019, Texas Instruments, Incorporated + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpsw_mdio.h" + +#define AM65_CPSW_CPSWNU_MAX_PORTS 2 + +#define AM65_CPSW_SS_BASE 0x0 +#define AM65_CPSW_SGMII_BASE 0x100 +#define AM65_CPSW_MDIO_BASE0xf00 +#define AM65_CPSW_XGMII_BASE 0x2100 +#define AM65_CPSW_CPSW_NU_BASE 0x2 +#define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000 + +#define AM65_CPSW_CPSW_NU_PORTS_OFFSET 0x1000 +#define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET0x330 + +#define AM65_CPSW_MDIO_BUS_FREQ_DEF 100 + +#define AM65_CPSW_CTL_REG 0x4 +#define AM65_CPSW_STAT_PORT_EN_REG 0x14 +#define AM65_CPSW_PTYPE_REG0x18 + +#define AM65_CPSW_CTL_REG_P0_ENABLEBIT(2) +#define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE BIT(13) +#define AM65_CPSW_CTL_REG_P0_RX_PADBIT(14) + +#define AM65_CPSW_P0_FLOW_ID_REG 0x8 +#define AM65_CPSW_PN_RX_MAXLEN_REG 0x24 +#define AM65_CPSW_PN_REG_SA_L 0x308 +#define AM65_CPSW_PN_REG_SA_H 0x30c + +#define AM65_CPSW_ALE_CTL_REG 0x8 +#define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31) +#define AM65_CPSW_ALE_CTL_REG_RESET_TBLBIT(30) +#define AM65_CPSW_ALE_CTL_REG_BYPASS BIT(4) +#define AM65_CPSW_ALE_PN_CTL_REG(x)(0x40 + (x) * 4) +#define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3 +#define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11) + +#define AM65_CPSW_MACSL_CTL_REG0x0 +#define AM65_CPSW_MACSL_CTL_REG_IFCTL_ABIT(15) +#define AM65_CPSW_MACSL_CTL_REG_GIGBIT(7) +#define AM65_CPSW_MACSL_CTL_REG_GMII_ENBIT(5) +#define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1) +#define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEXBIT(0) +#define AM65_CPSW_MACSL_RESET_REG 0x8 +#define AM65_CPSW_MACSL_RESET_REG_RESETBIT(0) +#define AM65_CPSW_MACSL_STATUS_REG 0x4 +#define AM65_CPSW_MACSL_RESET_REG_PN_IDLE BIT(31) +#define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLEBIT(30) +#define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLEBIT(29) +#define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE BIT(28) +#define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \ +
