From: Kevin Scholz
Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 2666MTs LPDDR configuration on J7200.
Signed-off-by: Kevin Scholz
Signed-off-by: Praneeth Bajjuri
Tested-by: Suman Anna
---
...00.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} | 437 +-
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +-
2 files changed, 220 insertions(+), 219 deletions(-)
rename arch/arm/dts/{k3-j7200-ddr-evm-lp4-1600.dtsi =>
k3-j7200-ddr-evm-lp4-2666.dtsi} (90%)
diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
similarity index 90%
rename from arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
rename to arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
index 12ffd913d1..42ac8c5c89 100644
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
@@ -1,13 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool,
Revision: 0.3.0
- * This file was generated on 06/08/2020
- * Includes hand edits
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
+ * This file was generated on 08/07/2020
+ * Includes hand-edits
*/
#define DDRSS_PLL_FHS_CNT 10
-#define DDRSS_PLL_FREQUENCY_1 4
-#define DDRSS_PLL_FREQUENCY_2 4
+#define DDRSS_PLL_FREQUENCY_1 66650
+#define DDRSS_PLL_FREQUENCY_2 66650
#define DDRSS_CTL_00_DATA 0x0B00
#define DDRSS_CTL_01_DATA 0x
@@ -20,14 +21,14 @@
#define DDRSS_CTL_08_DATA 0x000186A0
#define DDRSS_CTL_09_DATA 0x0005
#define DDRSS_CTL_10_DATA 0x0064
-#define DDRSS_CTL_11_DATA 0x00027100
-#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_11_DATA 0x000411AB
+#define DDRSS_CTL_12_DATA 0x0028B0AB
#define DDRSS_CTL_13_DATA 0x0005
-#define DDRSS_CTL_14_DATA 0x0640
-#define DDRSS_CTL_15_DATA 0x00027100
-#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_14_DATA 0x0A6B
+#define DDRSS_CTL_15_DATA 0x000411AB
+#define DDRSS_CTL_16_DATA 0x0028B0AB
#define DDRSS_CTL_17_DATA 0x0005
-#define DDRSS_CTL_18_DATA 0x0640
+#define DDRSS_CTL_18_DATA 0x0A6B
#define DDRSS_CTL_19_DATA 0x0101
#define DDRSS_CTL_20_DATA 0x02011001
#define DDRSS_CTL_21_DATA 0x0201
@@ -37,66 +38,66 @@
#define DDRSS_CTL_25_DATA 0x
#define DDRSS_CTL_26_DATA 0x
#define DDRSS_CTL_27_DATA 0x02020200
-#define DDRSS_CTL_28_DATA 0x2020
+#define DDRSS_CTL_28_DATA 0x3636
#define DDRSS_CTL_29_DATA 0x0010
#define DDRSS_CTL_30_DATA 0x
#define DDRSS_CTL_31_DATA 0x
#define DDRSS_CTL_32_DATA 0x
#define DDRSS_CTL_33_DATA 0x
#define DDRSS_CTL_34_DATA 0x040C
-#define DDRSS_CTL_35_DATA 0x081C081C
+#define DDRSS_CTL_35_DATA 0x0C300C30
#define DDRSS_CTL_36_DATA 0x00050804
#define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x08000204
-#define DDRSS_CTL_39_DATA 0x0B240034
-#define DDRSS_CTL_40_DATA 0x08001910
-#define DDRSS_CTL_41_DATA 0x0B240034
-#define DDRSS_CTL_42_DATA 0x20001910
+#define DDRSS_CTL_38_DATA 0x0D000204
+#define DDRSS_CTL_39_DATA 0x113C0057
+#define DDRSS_CTL_40_DATA 0x0D00291B
+#define DDRSS_CTL_41_DATA 0x113C0057
+#define DDRSS_CTL_42_DATA 0x2000291B
#define DDRSS_CTL_43_DATA 0x000A0A09
#define DDRSS_CTL_44_DATA 0x040006DB
-#define DDRSS_CTL_45_DATA 0x0C0A0904
-#define DDRSS_CTL_46_DATA 0x06006DB0
-#define DDRSS_CTL_47_DATA 0x0C0A0906
-#define DDRSS_CTL_48_DATA 0x06006DB0
-#define DDRSS_CTL_49_DATA 0x02030406
-#define DDRSS_CTL_50_DATA 0x11040500
-#define DDRSS_CTL_51_DATA 0x08121112
+#define DDRSS_CTL_45_DATA 0x130E0B04
+#define DDRSS_CTL_46_DATA 0x0A00B6D0
+#define DDRSS_CTL_47_DATA 0x130E0B0A
+#define DDRSS_CTL_48_DATA 0x0A00B6D0
+#define DDRSS_CTL_49_DATA 0x0203040A
+#define DDRSS_CTL_50_DATA 0x1C040500
+#define DDRSS_CTL_51_DATA 0x081D1C1D
#define DDRSS_CTL_52_DATA 0x14000D0A
#define DDRSS_CTL_53_DATA 0x02010A0A
#define DDRSS_CTL_54_DATA 0x01010002
-#define DDRSS_CTL_55_DATA 0x0408
-#define DDRSS_CTL_56_DATA 0x04131304
-#define DDRSS_CTL_57_DATA 0x1313
+#define DDRSS_CTL_55_DATA 0x04383808
+#define DDRSS_CTL_56_DATA 0x041F1F04
+#define DDRSS_CTL_57_DATA 0x1F1F
#define DDRSS_CTL_58_DATA 0x00010100
#define DDRSS_CTL_59_DATA 0x0301
#define DDRSS_CTL_60_DATA 0x0E08
#define DDRSS_CTL_61_DATA 0x00BB
-#define DDRSS_CTL_62_DATA 0x00E0
-#define DDRSS_CTL_63_DATA 0x0C28
-#define DDRSS_CTL_64_DATA 0x00E0
-#define DDRSS_CTL_65_DATA 0x0C28
+#define DDRSS_CTL_62_DATA 0x0176
+#define DDRSS_CTL_63_DATA 0x1448
+#define DDRSS_CTL_64_DATA 0x0176
+#define DDRSS_CTL_65_DATA 0x1448
#define DDRSS_CTL_66_DATA 0x0005
#define DDRSS_CTL_67_DATA 0x0003
-#define DDRSS_CTL_68_DATA 0x00380010
-#define DDRSS_CTL_69_DATA 0x0038017E
-#define DDRSS_CTL_70_DATA 0x0040017E
+#define DDRSS_CTL_68_DATA 0x005D0010
+#define
