Re: [PATCH] arm: socfpga: Add the terasic de10-standard board

2022-05-23 Thread Humberto Naves 
Hi Marek,

Thanks for the quick review!

> Doesn't the PLL config also come from quartus ? It should all come from
> it. See doc/README.socfpga

My mistake, I will update the patch using all the files created by the
bsp-create-settings.

> I think a lot of those board/config-specific copyright messages could
> use an update, I think they should be assigned to you. Please do a quick
> V2 with that change. Besides that:

Please advise what I should do there. For this particular board I adapted
the code from the de10-nano board, which already had these copyright
messages.


Best regards,


On Sat, May 21, 2022 at 10:06 PM Marek Vasut  wrote:
>
> On 5/21/22 19:32, Humberto Naves wrote:
> > Used the de10-nano files as templates for the de10-standard board.
> > Changed the iocsr_config.h and pinmux_config.h based on the handoff
> > files generated by quartus. Finally, the pll_config.h was copied
> > from the altera cyclone5-socdk board.
>
> Doesn't the PLL config also come from quartus ? It should all come from
> it. See doc/README.socfpga
>
> > Signed-off-by: Humberto Naves 
> > Cc: Marek Vasut 
>
> I think a lot of those board/config-specific copyright messages could
> use an update, I think they should be assigned to you. Please do a quick
> V2 with that change. Besides that:
>
> Reviewed-by: Marek Vasut

Re: [PATCH] arm: socfpga: Add the terasic de10-standard board

2022-05-22 Thread Marek Vasut 

On 5/22/22 17:53, Humberto Naves wrote:

Hi Marek,


Hi,


Thanks for the quick review!


Doesn't the PLL config also come from quartus ? It should all come from
it. See doc/README.socfpga


My mistake, I will update the patch using all the files created by the
bsp-create-settings.


Thanks


I think a lot of those board/config-specific copyright messages could
use an update, I think they should be assigned to you. Please do a quick
V2 with that change. Besides that:


Please advise what I should do there. For this particular board I adapted
the code from the de10-nano board, which already had these copyright
messages.


I'm not a lawyer. Maybe the most safe approach is to keep the original 
copyright and add your own in addition to it ?

Re: [PATCH] arm: socfpga: Add the terasic de10-standard board

2022-05-21 Thread Marek Vasut 

On 5/21/22 19:32, Humberto Naves wrote:

Used the de10-nano files as templates for the de10-standard board.
Changed the iocsr_config.h and pinmux_config.h based on the handoff
files generated by quartus. Finally, the pll_config.h was copied
from the altera cyclone5-socdk board.


Doesn't the PLL config also come from quartus ? It should all come from 
it. See doc/README.socfpga



Signed-off-by: Humberto Naves 
Cc: Marek Vasut 


I think a lot of those board/config-specific copyright messages could 
use an update, I think they should be assigned to you. Please do a quick 
V2 with that change. Besides that:


Reviewed-by: Marek Vasut

[PATCH] arm: socfpga: Add the terasic de10-standard board

2022-05-21 Thread Humberto Naves 
Used the de10-nano files as templates for the de10-standard board.
Changed the iocsr_config.h and pinmux_config.h based on the handoff
files generated by quartus. Finally, the pll_config.h was copied
from the altera cyclone5-socdk board.

Signed-off-by: Humberto Naves 
Cc: Marek Vasut 
---
 .../dts/socfpga_cyclone5_de10_standard.dts|  86 +++
 arch/arm/mach-socfpga/Kconfig |   7 +
 board/terasic/de10-standard/MAINTAINERS   |   5 +
 board/terasic/de10-standard/Makefile  |   6 +
 .../terasic/de10-standard/qts/iocsr_config.h  | 659 ++
 .../terasic/de10-standard/qts/pinmux_config.h | 218 ++
 board/terasic/de10-standard/qts/pll_config.h  |  84 +++
 .../terasic/de10-standard/qts/sdram_config.h  | 343 +
 board/terasic/de10-standard/socfpga.c |   5 +
 configs/socfpga_de10_standard_defconfig   |  66 ++
 include/configs/socfpga_de10_standard.h   |  16 +
 11 files changed, 1495 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_standard.dts
 create mode 100644 board/terasic/de10-standard/MAINTAINERS
 create mode 100644 board/terasic/de10-standard/Makefile
 create mode 100644 board/terasic/de10-standard/qts/iocsr_config.h
 create mode 100644 board/terasic/de10-standard/qts/pinmux_config.h
 create mode 100644 board/terasic/de10-standard/qts/pll_config.h
 create mode 100644 board/terasic/de10-standard/qts/sdram_config.h
 create mode 100644 board/terasic/de10-standard/socfpga.c
 create mode 100644 configs/socfpga_de10_standard_defconfig
 create mode 100644 include/configs/socfpga_de10_standard.h

diff --git a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts 
b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
new file mode 100644
index 00..ccd1413184
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * based on socfpga_cyclone5_de10_nano.dts
+ */
+
+#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
+
+/ {
+   model = "Terasic DE10-Standard";
+   compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   stdout-path = "serial0:115200n8";
+   };
+
+   aliases {
+   ethernet0 = &gmac1;
+   udc0 = &usb1;
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+};
+
+&gmac1 {
+   status = "okay";
+   phy-mode = "rgmii";
+
+   rxd0-skew-ps = <420>;
+   rxd1-skew-ps = <420>;
+   rxd2-skew-ps = <420>;
+   rxd3-skew-ps = <420>;
+   txen-skew-ps = <0>;
+   txc-skew-ps = <1860>;
+   rxdv-skew-ps = <420>;
+   rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+   status = "okay";
+};
+
+&gpio1 {
+   status = "okay";
+};
+
+&gpio2 {
+   status = "okay";
+};
+
+&porta {
+   bank-name = "porta";
+};
+
+&portb {
+   bank-name = "portb";
+};
+
+&portc {
+   bank-name = "portc";
+};
+
+&mmc0 {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+   status = "okay";
+};
+
+&uart0 {
+   clock-frequency = <1>;
+   u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+   status = "disabled";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 78a7549a41..547e47ed9d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -180,6 +180,10 @@ config TARGET_SOCFPGA_TERASIC_DE10_NANO
bool "Terasic DE10-Nano (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
+   bool "Terasic DE10-Standard (Cyclone V)"
+   select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -199,6 +203,7 @@ config SYS_BOARD
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+   default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
@@ -224,6 +229,7 @@ config SYS_VENDOR
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+   default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
@@ -239,6 +245,7 @@ config SYS_CONFIG_NAME
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_