Re: [PATCH] clk: imx8mp: Fix 32k clock name
On 6/13/22 15:41, ZHIZHIKIN Andrey wrote:
Hello Marek,
-Original Message-
From: U-Boot On Behalf Of Marek Vasut
Sent: Monday, June 13, 2022 3:22 PM
To: u-boot@lists.denx.de
Cc: Marek Vasut ; Fabio Estevam ; Peng Fan
; Stefano Babic
Subject: [PATCH] clk: imx8mp: Fix 32k clock name
The 32 kHz oscillator clock name is 'clock-osc-32k' instead of 'osc_32k'.
Fix the name to prevent the following warning:
"
clk_register: failed to get osc_32k device (parent of usb_root_clk)
"
Fixes: 7a2c3be95a5 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
I've already submitted a series to address this issue and the one for
ECSPI clocks, see [1].
You're also on Cc: to that series, so you can take a look at it and
decide whether it is suitable or not.
Even better, thanks.
RE: [PATCH] clk: imx8mp: Fix 32k clock name
Hello Marek,
> -Original Message-
> From: U-Boot On Behalf Of Marek Vasut
> Sent: Monday, June 13, 2022 3:22 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Fabio Estevam ; Peng Fan
> ; Stefano Babic
> Subject: [PATCH] clk: imx8mp: Fix 32k clock name
>
> The 32 kHz oscillator clock name is 'clock-osc-32k' instead of 'osc_32k'.
> Fix the name to prevent the following warning:
>
> "
> clk_register: failed to get osc_32k device (parent of usb_root_clk)
> "
>
> Fixes: 7a2c3be95a5 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
I've already submitted a series to address this issue and the one for
ECSPI clocks, see [1].
You're also on Cc: to that series, so you can take a look at it and
decide whether it is suitable or not.
> ---
> drivers/clk/imx/clk-imx8mp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index cbed86a6843..9c7857bbb3a 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -300,7 +300,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2",
> base + 0x44a0, 0));
> clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3",
> base + 0x44b0, 0));
> clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4",
> base + 0x44c0, 0));
> - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "osc_32k",
> base
> + 0x44d0, 0));
> + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> "clock-osc-32k",
> base + 0x44d0, 0));
> clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
> "usb_phy_ref", base + 0x44f0, 0));
> clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk",
> "usdhc1",
> base + 0x4510, 0));
> clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk",
> "usdhc2",
> base + 0x4520, 0));
> --
> 2.35.1
-- andrey
Link: [1]:
https://lore.kernel.org/u-boot/20220603151522.6643-1-andrey.zhizhi...@leica-geosystems.com/
[PATCH] clk: imx8mp: Fix 32k clock name
The 32 kHz oscillator clock name is 'clock-osc-32k' instead of 'osc_32k'.
Fix the name to prevent the following warning:
"
clk_register: failed to get osc_32k device (parent of usb_root_clk)
"
Fixes: 7a2c3be95a5 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
drivers/clk/imx/clk-imx8mp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index cbed86a6843..9c7857bbb3a 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -300,7 +300,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2",
base + 0x44a0, 0));
clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3",
base + 0x44b0, 0));
clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4",
base + 0x44c0, 0));
- clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "osc_32k",
base + 0x44d0, 0));
+ clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
"clock-osc-32k", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
"usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk",
"usdhc1", base + 0x4510, 0));
clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk",
"usdhc2", base + 0x4520, 0));
--
2.35.1
