[PATCH] i.MX6SX: crypto/fsl: fix entropy delay value
> RNG Hardware error is reported due to incorrect entropy delay > rng self test are run to determine the correct ent_dly. > test is executed with different voltage and temperature to identify the > worst case value for ent_dly. after adding a margin value(1000), > ent_dly should be at least 12000. > Signed-off-by: Gaurav Jain > Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
RE: [PATCH] i.MX6SX: crypto/fsl: fix entropy delay value
Hello Stefano
This patch is already merged in kernel
https://patchwork.kernel.org/project/linux-crypto/patch/20220420120601.1015362-1-feste...@gmail.com/
Can you help to check and merge this in Uboot as well.
Regards
Gaurav Jain
> -Original Message-
> From: Gaurav Jain
> Sent: Friday, April 15, 2022 4:41 PM
> To: Stefano Babic ; u-boot@lists.denx.de
> Cc: Fabio Estevam ; Peng Fan ;
> Priyanka Jain ; Ye Li ; Horia Geanta
> ; Silvano Di Ninno ; Varun
> Sethi ; dl-uboot-imx ; Gaurav Jain
>
> Subject: [PATCH] i.MX6SX: crypto/fsl: fix entropy delay value
>
> RNG Hardware error is reported due to incorrect entropy delay
>
> rng self test are run to determine the correct ent_dly.
> test is executed with different voltage and temperature to identify the worst
> case value for ent_dly. after adding a margin value(1000), ent_dly should be
> at
> least 12000.
>
> Signed-off-by: Gaurav Jain
> ---
> drivers/crypto/fsl/jr.c | 11 ++-
> include/fsl_sec.h | 6 +-
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index
> 1d951cf0a6..85a3dac796 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -623,7 +623,7 @@ static void kick_trng(int ent_delay, ccsr_sec_t *sec)
>
> static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) {
> - int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> + int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY;
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)>rng;
> u32 inst_handles;
> @@ -652,6 +652,15 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
>* the RNG.
>*/
> ret = instantiate_rng(sec_idx, sec, gen_sk);
> + /*
> + * entropy delay is calculated via self-test method.
> + * self-test are run across different volatge, temp.
> + * if worst case value for ent_dly is identified,
> + * loop can be skipped for that platform.
> + */
> + if (IS_ENABLED(CONFIG_MX6SX))
> + break;
> +
> } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> if (ret) {
> printf("SEC%u: Failed to instantiate RNG\n", sec_idx); diff
> --git
> a/include/fsl_sec.h b/include/fsl_sec.h index 7b6e3e2c20..d57c4ca820 100644
> --- a/include/fsl_sec.h
> +++ b/include/fsl_sec.h
> @@ -48,7 +48,11 @@ struct rng4tst {
> u32 rtmctl; /* misc. control register */
> u32 rtscmisc; /* statistical check misc. register */
> u32 rtpkrrng; /* poker range register */
> -#define RTSDCTL_ENT_DLY_MIN 3200
> +#ifdef CONFIG_MX6SX
> +#define RTSDCTL_ENT_DLY 12000
> +#else
> +#define RTSDCTL_ENT_DLY 3200
> +#endif
> #define RTSDCTL_ENT_DLY_MAX 12800
> union {
> u32 rtpkrmax; /* PRGM=1: poker max. limit register */
> --
> 2.25.1
Re: [PATCH] i.MX6SX: crypto/fsl: fix entropy delay value
On Fri, Apr 15, 2022 at 8:11 AM Gaurav Jain wrote:
>
> RNG Hardware error is reported due to incorrect entropy delay
Yes, I observe the RNG hardware error in the kernel too.
> rng self test are run to determine the correct ent_dly.
> test is executed with different voltage and temperature to identify the
> worst case value for ent_dly. after adding a margin value(1000),
> ent_dly should be at least 12000.
>
> Signed-off-by: Gaurav Jain
> ---
> drivers/crypto/fsl/jr.c | 11 ++-
> include/fsl_sec.h | 6 +-
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index 1d951cf0a6..85a3dac796 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -623,7 +623,7 @@ static void kick_trng(int ent_delay, ccsr_sec_t *sec)
>
> static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> {
> - int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> + int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY;
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)>rng;
> u32 inst_handles;
> @@ -652,6 +652,15 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> * the RNG.
> */
> ret = instantiate_rng(sec_idx, sec, gen_sk);
> + /*
> +* entropy delay is calculated via self-test method.
> +* self-test are run across different volatge, temp.
s/volatge/voltage
Reviewed-by: Fabio Estevam
[PATCH] i.MX6SX: crypto/fsl: fix entropy delay value
RNG Hardware error is reported due to incorrect entropy delay
rng self test are run to determine the correct ent_dly.
test is executed with different voltage and temperature to identify the
worst case value for ent_dly. after adding a margin value(1000),
ent_dly should be at least 12000.
Signed-off-by: Gaurav Jain
---
drivers/crypto/fsl/jr.c | 11 ++-
include/fsl_sec.h | 6 +-
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 1d951cf0a6..85a3dac796 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -623,7 +623,7 @@ static void kick_trng(int ent_delay, ccsr_sec_t *sec)
static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
{
- int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
+ int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY;
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)>rng;
u32 inst_handles;
@@ -652,6 +652,15 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
* the RNG.
*/
ret = instantiate_rng(sec_idx, sec, gen_sk);
+ /*
+* entropy delay is calculated via self-test method.
+* self-test are run across different volatge, temp.
+* if worst case value for ent_dly is identified,
+* loop can be skipped for that platform.
+*/
+ if (IS_ENABLED(CONFIG_MX6SX))
+ break;
+
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 7b6e3e2c20..d57c4ca820 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -48,7 +48,11 @@ struct rng4tst {
u32 rtmctl; /* misc. control register */
u32 rtscmisc; /* statistical check misc. register */
u32 rtpkrrng; /* poker range register */
-#define RTSDCTL_ENT_DLY_MIN3200
+#ifdef CONFIG_MX6SX
+#define RTSDCTL_ENT_DLY12000
+#else
+#define RTSDCTL_ENT_DLY3200
+#endif
#define RTSDCTL_ENT_DLY_MAX12800
union {
u32 rtpkrmax; /* PRGM=1: poker max. limit register */
--
2.25.1
