[PATCH] imx8m: fix reading of DDR4 MR registers [again]
> Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a > private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board > code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version > actually seems to work in practice. > However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) > reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c, > copied most of the rest of ddrphy_utils.c to > drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building > drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally > completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused > file)]. > I assume this must have broken the imx8mm-cl-iot-gate board, at least > those that have not had their eeprom programmed with the proper > information. It certainly did break our out-of-tree board which always > reads back the ID register and uses that for a sanity check. > So apply the fix from 290ffe5788 once again. > Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) > Signed-off-by: Rasmus Villemoes > Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
Re: [PATCH] imx8m: fix reading of DDR4 MR registers [again]
Hi Rasmus, On 06/10/2022 09:56, Rasmus Villemoes wrote: Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version actually seems to work in practice. However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c, copied most of the rest of ddrphy_utils.c to drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused file)]. I assume this must have broken the imx8mm-cl-iot-gate board, at least those that have not had their eeprom programmed with the proper information. It certainly did break our out-of-tree board which always reads back the ID register and uses that for a sanity check. So apply the fix from 290ffe5788 once again. Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) Signed-off-by: Rasmus Villemoes Thanks for the fix: Reviewed-by: Fabio Estevam
[PATCH] imx8m: fix reading of DDR4 MR registers [again]
Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a
private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board
code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version
actually seems to work in practice.
However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c,
copied most of the rest of ddrphy_utils.c to
drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building
drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally
completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused
file)].
I assume this must have broken the imx8mm-cl-iot-gate board, at least
those that have not had their eeprom programmed with the proper
information. It certainly did break our out-of-tree board which always
reads back the ID register and uses that for a sanity check.
So apply the fix from 290ffe5788 once again.
Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
Signed-off-by: Rasmus Villemoes
---
drivers/ddr/imx/imx8m/ddr_init.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index d964184ddc..52a4aa6323 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -134,8 +134,14 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned
int mr_addr)
tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
} while ((tmp & 0x8) == 0);
tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
- tmp = tmp & 0xff;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+ while (tmp) { //try to find a significant byte in the word
+ if (tmp & 0xff) {
+ tmp &= 0xff;
+ break;
+ }
+ tmp >>= 8;
+ }
return tmp;
}
--
2.37.2
[PATCH] imx8m: fix reading of DDR4 MR registers
> I was trying to employ lpddr4_mr_read() to something similar to what > the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM > type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c > differs from the private one used by that board in how it extracts the > byte value, and I was only getting zeroes. Adding a bit of debug > printf'ing gives me > tmp = 0x0000 > tmp = 0x00070700 > tmp = 0x > tmp = 0x00101000 > and indeed I was expecting a (combined) value of 0xff070010 (0xff > being Manufacturer ID for Micron). I can't find any documentation that > says how the values are supposed to be read, but clearly the iot-gate > definition is the right one, both for its use case as well as my > imx8mp-based board. > So lift the private definition of lpddr4_mr_read() from the > imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration > in the ddr.h header where e.g. get_trained_CDD() is already declared. > This has only been compile-tested for the imx8mm-cl-iot-gate > board (since I don't have the hardware), but since I've merely moved > its definition of lpddr4_mr_read(), I'd be surprised if it changed > anything for that board. > Signed-off-by: Rasmus Villemoes > Tested-by: Ying-Chun Liu (PaulLiu) > Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
Re: [PATCH] imx8m: fix reading of DDR4 MR registers
Hi Paul, On 27/04/2022 03:48, Paul Liu wrote: Hi Fabio, I tested. It works. Tested-by: Ying-Chun Liu (PaulLiu) Thanks for testing. Reviewed-by: Fabio Estevam
Re: [PATCH] imx8m: fix reading of DDR4 MR registers
Hi Fabio, I tested. It works. Tested-by: Ying-Chun Liu (PaulLiu) On Tue, 26 Apr 2022 at 20:59, Fabio Estevam wrote: > Hi Paul, > > On Mon, Apr 25, 2022 at 11:23 AM Rasmus Villemoes > wrote: > > > > I was trying to employ lpddr4_mr_read() to something similar to what > > the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM > > type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c > > differs from the private one used by that board in how it extracts the > > byte value, and I was only getting zeroes. Adding a bit of debug > > printf'ing gives me > > > > tmp = 0x0000 > > tmp = 0x00070700 > > tmp = 0x > > tmp = 0x00101000 > > > > and indeed I was expecting a (combined) value of 0xff070010 (0xff > > being Manufacturer ID for Micron). I can't find any documentation that > > says how the values are supposed to be read, but clearly the iot-gate > > definition is the right one, both for its use case as well as my > > imx8mp-based board. > > > > So lift the private definition of lpddr4_mr_read() from the > > imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration > > in the ddr.h header where e.g. get_trained_CDD() is already declared. > > > > This has only been compile-tested for the imx8mm-cl-iot-gate > > board (since I don't have the hardware), but since I've merely moved > > its definition of lpddr4_mr_read(), I'd be surprised if it changed > > anything for that board. > > > > Signed-off-by: Rasmus Villemoes > > Could you please test this patch? > > I only have remote access to this board. >
Re: [PATCH] imx8m: fix reading of DDR4 MR registers
Hi Paul, On Mon, Apr 25, 2022 at 11:23 AM Rasmus Villemoes wrote: > > I was trying to employ lpddr4_mr_read() to something similar to what > the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM > type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c > differs from the private one used by that board in how it extracts the > byte value, and I was only getting zeroes. Adding a bit of debug > printf'ing gives me > > tmp = 0x0000 > tmp = 0x00070700 > tmp = 0x > tmp = 0x00101000 > > and indeed I was expecting a (combined) value of 0xff070010 (0xff > being Manufacturer ID for Micron). I can't find any documentation that > says how the values are supposed to be read, but clearly the iot-gate > definition is the right one, both for its use case as well as my > imx8mp-based board. > > So lift the private definition of lpddr4_mr_read() from the > imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration > in the ddr.h header where e.g. get_trained_CDD() is already declared. > > This has only been compile-tested for the imx8mm-cl-iot-gate > board (since I don't have the hardware), but since I've merely moved > its definition of lpddr4_mr_read(), I'd be surprised if it changed > anything for that board. > > Signed-off-by: Rasmus Villemoes Could you please test this patch? I only have remote access to this board.
[PATCH] imx8m: fix reading of DDR4 MR registers
I was trying to employ lpddr4_mr_read() to something similar to what
the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM
type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c
differs from the private one used by that board in how it extracts the
byte value, and I was only getting zeroes. Adding a bit of debug
printf'ing gives me
tmp = 0x0000
tmp = 0x00070700
tmp = 0x
tmp = 0x00101000
and indeed I was expecting a (combined) value of 0xff070010 (0xff
being Manufacturer ID for Micron). I can't find any documentation that
says how the values are supposed to be read, but clearly the iot-gate
definition is the right one, both for its use case as well as my
imx8mp-based board.
So lift the private definition of lpddr4_mr_read() from the
imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration
in the ddr.h header where e.g. get_trained_CDD() is already declared.
This has only been compile-tested for the imx8mm-cl-iot-gate
board (since I don't have the hardware), but since I've merely moved
its definition of lpddr4_mr_read(), I'd be surprised if it changed
anything for that board.
Signed-off-by: Rasmus Villemoes
---
arch/arm/include/asm/arch-imx8m/ddr.h | 1 +
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 27 -
drivers/ddr/imx/imx8m/ddrphy_utils.c| 9 +--
3 files changed, 8 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h
b/arch/arm/include/asm/arch-imx8m/ddr.h
index 0f1e832c03..2ce8a8f2d4 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -723,6 +723,7 @@ void ddrphy_init_read_msg_block(enum fw_type type);
void update_umctl2_rank_space_setting(unsigned int pstat_num);
void get_trained_CDD(unsigned int fsp);
+unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);
static inline void reg32_write(unsigned long addr, u32 val)
{
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
index 5b93491923..b230478b61 100644
--- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@@ -24,33 +24,6 @@
#include
-static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
-{
- unsigned int tmp;
-
- reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
- do {
- tmp = reg32_read(DDRC_MRSTAT(0));
- } while (tmp & 0x1);
-
- reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
- reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
- reg32setbit(DDRC_MRCTRL0(0), 31);
- do {
- tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
- } while ((tmp & 0x8) == 0);
- tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
- reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
- while (tmp) { //try to find a significant byte in the word
- if (tmp & 0xff) {
- tmp &= 0xff;
- break;
- }
- tmp >>= 8;
- }
- return tmp;
-}
-
struct lpddr4_desc {
char name[16];
unsigned int id;
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c
b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index a54449e5f1..975d553674 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -198,9 +198,14 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned
int mr_addr)
tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
} while ((tmp & 0x8) == 0);
tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
- tmp = tmp & 0xff;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
-
+ while (tmp) { //try to find a significant byte in the word
+ if (tmp & 0xff) {
+ tmp &= 0xff;
+ break;
+ }
+ tmp >>= 8;
+ }
return tmp;
}
--
2.31.1
