subject:"\[PATCH 1\/6\] clk\: sunxi\: Add NAND clocks and resets"

Re: [PATCH 1/6] clk: sunxi: Add NAND clocks and resets

2022-07-18 Thread Samuel Holland

On 7/18/22 11:10 AM, Andre Przywara wrote:
> On Wed, 13 Jul 2022 22:15:21 -0500
> Samuel Holland  wrote:
> 
> Hi,
> 
>> Currently NAND clock setup is done in board code, both in SPL and in
>> U-Boot proper. Add the NAND clocks/resets here so they can be used by
>> the "full" NAND driver once it is converted to the driver model.
>>
>> The bit locations are copied from the Linux CCU drivers.
>>
>> Signed-off-by: Samuel Holland 
>> ---
>>
>>  drivers/clk/sunxi/clk_a10.c  | 2 ++
>>  drivers/clk/sunxi/clk_a10s.c | 2 ++
>>  drivers/clk/sunxi/clk_a23.c  | 3 +++
>>  drivers/clk/sunxi/clk_a31.c  | 6 ++
>>  drivers/clk/sunxi/clk_a64.c  | 3 +++
>>  drivers/clk/sunxi/clk_a80.c  | 8 
>>  drivers/clk/sunxi/clk_a83t.c | 3 +++
>>  drivers/clk/sunxi/clk_h3.c   | 3 +++
>>  drivers/clk/sunxi/clk_h6.c   | 6 ++
>>  drivers/clk/sunxi/clk_h616.c | 6 ++
>>  drivers/clk/sunxi/clk_r40.c  | 3 +++
>>  11 files changed, 45 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
>> index db92848aafde..69c46da841e9 100644
>> --- a/drivers/clk/sunxi/clk_a10.c
>> +++ b/drivers/clk/sunxi/clk_a10.c
>> @@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] = {
>>  [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
>>  [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
>>  [CLK_AHB_MMC3]  = GATE(0x060, BIT(11)),
>> +[CLK_AHB_NAND]  = GATE(0x060, BIT(13)),
>>  [CLK_AHB_EMAC]  = GATE(0x060, BIT(17)),
>>  [CLK_AHB_SPI0]  = GATE(0x060, BIT(20)),
>>  [CLK_AHB_SPI1]  = GATE(0x060, BIT(21)),
>> @@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] = {
>>  [CLK_APB1_UART6]= GATE(0x06c, BIT(22)),
>>  [CLK_APB1_UART7]= GATE(0x06c, BIT(23)),
>>  
>> +[CLK_NAND]  = GATE(0x080, BIT(31)),
>>  [CLK_SPI0]  = GATE(0x0a0, BIT(31)),
>>  [CLK_SPI1]  = GATE(0x0a4, BIT(31)),
>>  [CLK_SPI2]  = GATE(0x0a8, BIT(31)),
>> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
>> index 0c6564ef3b62..6abccea3aa9e 100644
>> --- a/drivers/clk/sunxi/clk_a10s.c
>> +++ b/drivers/clk/sunxi/clk_a10s.c
>> @@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[] = {
>>  [CLK_AHB_MMC0]  = GATE(0x060, BIT(8)),
>>  [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
>>  [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
>> +[CLK_AHB_NAND]  = GATE(0x060, BIT(13)),
>>  [CLK_AHB_EMAC]  = GATE(0x060, BIT(17)),
>>  [CLK_AHB_SPI0]  = GATE(0x060, BIT(20)),
>>  [CLK_AHB_SPI1]  = GATE(0x060, BIT(21)),
>> @@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[] = {
>>  [CLK_APB1_UART2]= GATE(0x06c, BIT(18)),
>>  [CLK_APB1_UART3]= GATE(0x06c, BIT(19)),
>>  
>> +[CLK_NAND]  = GATE(0x080, BIT(31)),
>>  [CLK_SPI0]  = GATE(0x0a0, BIT(31)),
>>  [CLK_SPI1]  = GATE(0x0a4, BIT(31)),
>>  [CLK_SPI2]  = GATE(0x0a8, BIT(31)),
>> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
>> index 0280fb51e2db..342af83b158d 100644
>> --- a/drivers/clk/sunxi/clk_a23.c
>> +++ b/drivers/clk/sunxi/clk_a23.c
>> @@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] = {
>>  [CLK_BUS_MMC0]  = GATE(0x060, BIT(8)),
>>  [CLK_BUS_MMC1]  = GATE(0x060, BIT(9)),
>>  [CLK_BUS_MMC2]  = GATE(0x060, BIT(10)),
>> +[CLK_BUS_NAND]  = GATE(0x060, BIT(13)),
>>  [CLK_BUS_SPI0]  = GATE(0x060, BIT(20)),
>>  [CLK_BUS_SPI1]  = GATE(0x060, BIT(21)),
>>  [CLK_BUS_OTG]   = GATE(0x060, BIT(24)),
>> @@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] = {
>>  [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
>>  [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
>>  
>> +[CLK_NAND]  = GATE(0x080, BIT(31)),
>>  [CLK_SPI0]  = GATE(0x0a0, BIT(31)),
>>  [CLK_SPI1]  = GATE(0x0a4, BIT(31)),
>>  
>> @@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
>>  [RST_BUS_MMC0]  = RESET(0x2c0, BIT(8)),
>>  [RST_BUS_MMC1]  = RESET(0x2c0, BIT(9)),
>>  [RST_BUS_MMC2]  = RESET(0x2c0, BIT(10)),
>> +[RST_BUS_NAND]  = RESET(0x2c0, BIT(13)),
>>  [RST_BUS_SPI0]  = RESET(0x2c0, BIT(20)),
>>  [RST_BUS_SPI1]  = RESET(0x2c0, BIT(21)),
>>  [RST_BUS_OTG]   = RESET(0x2c0, BIT(24)),
>> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
>> index 26d25f324080..703ddc01dad0 100644
>> --- a/drivers/clk/sunxi/clk_a31.c
>> +++ b/drivers/clk/sunxi/clk_a31.c
>> @@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] = {
>>  [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
>>  [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
>>  [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
>> +[CLK_AHB1_NAND1]= GATE(0x060, BIT(12)),
>> +

Re: [PATCH 1/6] clk: sunxi: Add NAND clocks and resets

2022-07-18 Thread Andre Przywara

On Wed, 13 Jul 2022 22:15:21 -0500
Samuel Holland  wrote:

Hi,

> Currently NAND clock setup is done in board code, both in SPL and in
> U-Boot proper. Add the NAND clocks/resets here so they can be used by
> the "full" NAND driver once it is converted to the driver model.
> 
> The bit locations are copied from the Linux CCU drivers.
> 
> Signed-off-by: Samuel Holland 
> ---
> 
>  drivers/clk/sunxi/clk_a10.c  | 2 ++
>  drivers/clk/sunxi/clk_a10s.c | 2 ++
>  drivers/clk/sunxi/clk_a23.c  | 3 +++
>  drivers/clk/sunxi/clk_a31.c  | 6 ++
>  drivers/clk/sunxi/clk_a64.c  | 3 +++
>  drivers/clk/sunxi/clk_a80.c  | 8 
>  drivers/clk/sunxi/clk_a83t.c | 3 +++
>  drivers/clk/sunxi/clk_h3.c   | 3 +++
>  drivers/clk/sunxi/clk_h6.c   | 6 ++
>  drivers/clk/sunxi/clk_h616.c | 6 ++
>  drivers/clk/sunxi/clk_r40.c  | 3 +++
>  11 files changed, 45 insertions(+)
> 
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index db92848aafde..69c46da841e9 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] = {
>   [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
>   [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
>   [CLK_AHB_MMC3]  = GATE(0x060, BIT(11)),
> + [CLK_AHB_NAND]  = GATE(0x060, BIT(13)),
>   [CLK_AHB_EMAC]  = GATE(0x060, BIT(17)),
>   [CLK_AHB_SPI0]  = GATE(0x060, BIT(20)),
>   [CLK_AHB_SPI1]  = GATE(0x060, BIT(21)),
> @@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] = {
>   [CLK_APB1_UART6]= GATE(0x06c, BIT(22)),
>   [CLK_APB1_UART7]= GATE(0x06c, BIT(23)),
>  
> + [CLK_NAND]  = GATE(0x080, BIT(31)),
>   [CLK_SPI0]  = GATE(0x0a0, BIT(31)),
>   [CLK_SPI1]  = GATE(0x0a4, BIT(31)),
>   [CLK_SPI2]  = GATE(0x0a8, BIT(31)),
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index 0c6564ef3b62..6abccea3aa9e 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[] = {
>   [CLK_AHB_MMC0]  = GATE(0x060, BIT(8)),
>   [CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
>   [CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
> + [CLK_AHB_NAND]  = GATE(0x060, BIT(13)),
>   [CLK_AHB_EMAC]  = GATE(0x060, BIT(17)),
>   [CLK_AHB_SPI0]  = GATE(0x060, BIT(20)),
>   [CLK_AHB_SPI1]  = GATE(0x060, BIT(21)),
> @@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[] = {
>   [CLK_APB1_UART2]= GATE(0x06c, BIT(18)),
>   [CLK_APB1_UART3]= GATE(0x06c, BIT(19)),
>  
> + [CLK_NAND]  = GATE(0x080, BIT(31)),
>   [CLK_SPI0]  = GATE(0x0a0, BIT(31)),
>   [CLK_SPI1]  = GATE(0x0a4, BIT(31)),
>   [CLK_SPI2]  = GATE(0x0a8, BIT(31)),
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index 0280fb51e2db..342af83b158d 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] = {
>   [CLK_BUS_MMC0]  = GATE(0x060, BIT(8)),
>   [CLK_BUS_MMC1]  = GATE(0x060, BIT(9)),
>   [CLK_BUS_MMC2]  = GATE(0x060, BIT(10)),
> + [CLK_BUS_NAND]  = GATE(0x060, BIT(13)),
>   [CLK_BUS_SPI0]  = GATE(0x060, BIT(20)),
>   [CLK_BUS_SPI1]  = GATE(0x060, BIT(21)),
>   [CLK_BUS_OTG]   = GATE(0x060, BIT(24)),
> @@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] = {
>   [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
>   [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
>  
> + [CLK_NAND]  = GATE(0x080, BIT(31)),
>   [CLK_SPI0]  = GATE(0x0a0, BIT(31)),
>   [CLK_SPI1]  = GATE(0x0a4, BIT(31)),
>  
> @@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
>   [RST_BUS_MMC0]  = RESET(0x2c0, BIT(8)),
>   [RST_BUS_MMC1]  = RESET(0x2c0, BIT(9)),
>   [RST_BUS_MMC2]  = RESET(0x2c0, BIT(10)),
> + [RST_BUS_NAND]  = RESET(0x2c0, BIT(13)),
>   [RST_BUS_SPI0]  = RESET(0x2c0, BIT(20)),
>   [RST_BUS_SPI1]  = RESET(0x2c0, BIT(21)),
>   [RST_BUS_OTG]   = RESET(0x2c0, BIT(24)),
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index 26d25f324080..703ddc01dad0 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] = {
>   [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
>   [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
>   [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
> + [CLK_AHB1_NAND1]= GATE(0x060, BIT(12)),
> + [CLK_AHB1_NAND0]= GATE(0x060, BIT(13)),
>   [CLK_AHB1_EMAC] = GATE(0x060,

Re: [PATCH 1/6] clk: sunxi: Add NAND clocks and resets

2022-07-15 Thread Jagan Teki

On Thu, Jul 14, 2022 at 8:45 AM Samuel Holland  wrote:
>
> Currently NAND clock setup is done in board code, both in SPL and in
> U-Boot proper. Add the NAND clocks/resets here so they can be used by
> the "full" NAND driver once it is converted to the driver model.
>
> The bit locations are copied from the Linux CCU drivers.
>
> Signed-off-by: Samuel Holland 
> ---

Reviewed-by: Jagan Teki

[PATCH 1/6] clk: sunxi: Add NAND clocks and resets

2022-07-13 Thread Samuel Holland

Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.

The bit locations are copied from the Linux CCU drivers.

Signed-off-by: Samuel Holland 
---

 drivers/clk/sunxi/clk_a10.c  | 2 ++
 drivers/clk/sunxi/clk_a10s.c | 2 ++
 drivers/clk/sunxi/clk_a23.c  | 3 +++
 drivers/clk/sunxi/clk_a31.c  | 6 ++
 drivers/clk/sunxi/clk_a64.c  | 3 +++
 drivers/clk/sunxi/clk_a80.c  | 8 
 drivers/clk/sunxi/clk_a83t.c | 3 +++
 drivers/clk/sunxi/clk_h3.c   | 3 +++
 drivers/clk/sunxi/clk_h6.c   | 6 ++
 drivers/clk/sunxi/clk_h616.c | 6 ++
 drivers/clk/sunxi/clk_r40.c  | 3 +++
 11 files changed, 45 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index db92848aafde..69c46da841e9 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
[CLK_AHB_MMC3]  = GATE(0x060, BIT(11)),
+   [CLK_AHB_NAND]  = GATE(0x060, BIT(13)),
[CLK_AHB_EMAC]  = GATE(0x060, BIT(17)),
[CLK_AHB_SPI0]  = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1]  = GATE(0x060, BIT(21)),
@@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_APB1_UART6]= GATE(0x06c, BIT(22)),
[CLK_APB1_UART7]= GATE(0x06c, BIT(23)),
 
+   [CLK_NAND]  = GATE(0x080, BIT(31)),
[CLK_SPI0]  = GATE(0x0a0, BIT(31)),
[CLK_SPI1]  = GATE(0x0a4, BIT(31)),
[CLK_SPI2]  = GATE(0x0a8, BIT(31)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 0c6564ef3b62..6abccea3aa9e 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_MMC0]  = GATE(0x060, BIT(8)),
[CLK_AHB_MMC1]  = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2]  = GATE(0x060, BIT(10)),
+   [CLK_AHB_NAND]  = GATE(0x060, BIT(13)),
[CLK_AHB_EMAC]  = GATE(0x060, BIT(17)),
[CLK_AHB_SPI0]  = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1]  = GATE(0x060, BIT(21)),
@@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_APB1_UART2]= GATE(0x06c, BIT(18)),
[CLK_APB1_UART3]= GATE(0x06c, BIT(19)),
 
+   [CLK_NAND]  = GATE(0x080, BIT(31)),
[CLK_SPI0]  = GATE(0x0a0, BIT(31)),
[CLK_SPI1]  = GATE(0x0a4, BIT(31)),
[CLK_SPI2]  = GATE(0x0a8, BIT(31)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 0280fb51e2db..342af83b158d 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_MMC0]  = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1]  = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2]  = GATE(0x060, BIT(10)),
+   [CLK_BUS_NAND]  = GATE(0x060, BIT(13)),
[CLK_BUS_SPI0]  = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1]  = GATE(0x060, BIT(21)),
[CLK_BUS_OTG]   = GATE(0x060, BIT(24)),
@@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
 
+   [CLK_NAND]  = GATE(0x080, BIT(31)),
[CLK_SPI0]  = GATE(0x0a0, BIT(31)),
[CLK_SPI1]  = GATE(0x0a4, BIT(31)),
 
@@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
[RST_BUS_MMC0]  = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1]  = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2]  = RESET(0x2c0, BIT(10)),
+   [RST_BUS_NAND]  = RESET(0x2c0, BIT(13)),
[RST_BUS_SPI0]  = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1]  = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG]   = RESET(0x2c0, BIT(24)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 26d25f324080..703ddc01dad0 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
+   [CLK_AHB1_NAND1]= GATE(0x060, BIT(12)),
+   [CLK_AHB1_NAND0]= GATE(0x060, BIT(13)),
[CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
[CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
@@ -43,6 +45,8 @@ static struct ccu_clk_gate

Re: [PATCH 1/6] clk: sunxi: Add NAND clocks and resets

Re: [PATCH 1/6] clk: sunxi: Add NAND clocks and resets

Re: [PATCH 1/6] clk: sunxi: Add NAND clocks and resets

[PATCH 1/6] clk: sunxi: Add NAND clocks and resets

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