Re: [PATCH 19/19] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board

2024-04-26 Thread Patrice CHOTARD 



On 4/22/24 01:17, Marek Vasut wrote:
> This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
> STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
> carrier board.
> 
> The SoM contains the following peripherals:
> - STPMIC (power delivery)
> - 512MB DDR3L memory
> - eMMC and SDIO WiFi module
> 
> The DHSBC carrier board contains the following peripherals:
> - Two RGMII Ethernet ports
> - USB-A Host port, USB-C peripheral port, USB-C power supply plug
> - Expansion connector
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Patrice Chotard 
> Cc: Patrick Delaunay 
> Cc: u-b...@dh-electronics.com
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
>  arch/arm/dts/Makefile |   1 +
>  .../dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi   |  25 ++
>  arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts  | 383 ++
>  arch/arm/dts/stm32mp13xx-dhcor-som.dtsi   | 308 ++
>  arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi|  55 +++
>  configs/stm32mp13_dhcor_defconfig | 148 +++
>  6 files changed, 920 insertions(+)
>  create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
>  create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
>  create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
>  create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
>  create mode 100644 configs/stm32mp13_dhcor_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index b1c9c6222e5..ca1e3bf3fc8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1290,6 +1290,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
>  dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
>  
>  dtb-$(CONFIG_STM32MP13X) += \
> + stm32mp135f-dhcor-dhsbc.dtb \
>   stm32mp135f-dk.dtb
>  
>  dtb-$(CONFIG_STM32MP15X) += \
> diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi 
> b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> new file mode 100644
> index 000..d718aae16ca
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2024 Marek Vasut 
> + */
> +
> +#include "stm32mp13xx-dhcor-u-boot.dtsi"
> +
> + {
> + bootph-all;
> +};
> +
> +_pins_b {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> + {
> + bootph-all;
> +};
> diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts 
> b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> new file mode 100644
> index 000..fc1c48ad56d
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
> @@ -0,0 +1,383 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2024 Marek Vasut 
> + *
> + * DHCOR STM32MP13 variant:
> + * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
> + * DHCOR PCB number: 718-100 or newer
> + * DHSBC PCB number: 719-100 or newer
> + */
> +
> +/dts-v1/;
> +
> +#include 
> +#include "stm32mp135.dtsi"
> +#include "stm32mp13xf.dtsi"
> +#include "stm32mp13xx-dhcor-som.dtsi"
> +
> +/ {
> + model = "DH electronics STM32MP135F DHCOR DHSBC";
> + compatible = "dh,stm32mp135f-dhcor-dhsbc",
> +  "dh,stm32mp135f-dhcor-som",
> +  "st,stm32mp135";
> +
> + aliases {
> + ethernet0 = 
> + ethernet1 = 
> + serial2 = 
> + serial3 = 
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +_1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_a _usb_cc_pins_b>;
> + vdda-supply = <_adc>;
> + vref-supply = <_adc>;
> + status = "okay";
> +
> + adc1: adc@0 {
> + status = "okay";
> +
> + /*
> +  * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
> +  * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
> +  * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
> +  * Use arbitrary margin here (e.g. 5us).
> +  *
> +  * The pinmux pins must be set as ANALOG, use datasheet
> +  * DS13483 Table 7. STM32MP135C/F ball definitions to
> +  * find out which 'pin name' maps to which 'additional
> +  * functions', which lists the mapping between pin and
> +  * ADC channel. In this case, PA5 maps to ADC1_INP2 and
> +  * PF13 maps to ADC1_INP11 .
> +  */
> + channel@2 {
> + reg = <2>;
> + st,min-sample-time-ns = <5000>;
> + };
> +
> + channel@11 {
> + reg = <11>;
> + st,min-sample-time-ns = <5000>;
> + };
> +
> + /* Expansion connector: INP12:pin29 */
> + channel@12 {
> + reg = <12>;
> + st,min-sample-time-ns = <5000>;
>

[PATCH 19/19] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board

2024-04-21 Thread Marek Vasut 
This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
carrier board.

The SoM contains the following peripherals:
- STPMIC (power delivery)
- 512MB DDR3L memory
- eMMC and SDIO WiFi module

The DHSBC carrier board contains the following peripherals:
- Two RGMII Ethernet ports
- USB-A Host port, USB-C peripheral port, USB-C power supply plug
- Expansion connector

Signed-off-by: Marek Vasut 
---
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
 arch/arm/dts/Makefile |   1 +
 .../dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi   |  25 ++
 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts  | 383 ++
 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi   | 308 ++
 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi|  55 +++
 configs/stm32mp13_dhcor_defconfig | 148 +++
 6 files changed, 920 insertions(+)
 create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
 create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
 create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
 create mode 100644 configs/stm32mp13_dhcor_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ca1e3bf3fc8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1290,6 +1290,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 
 dtb-$(CONFIG_STM32MP13X) += \
+   stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb
 
 dtb-$(CONFIG_STM32MP15X) += \
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi 
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
new file mode 100644
index 000..d718aae16ca
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut 
+ */
+
+#include "stm32mp13xx-dhcor-u-boot.dtsi"
+
+ {
+   bootph-all;
+};
+
+_pins_b {
+   bootph-all;
+
+   pins1 {
+   bootph-all;
+   };
+   pins2 {
+   bootph-all;
+   };
+};
+
+ {
+   bootph-all;
+};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts 
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
new file mode 100644
index 000..fc1c48ad56d
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut 
+ *
+ * DHCOR STM32MP13 variant:
+ * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
+ * DHCOR PCB number: 718-100 or newer
+ * DHSBC PCB number: 719-100 or newer
+ */
+
+/dts-v1/;
+
+#include 
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13xx-dhcor-som.dtsi"
+
+/ {
+   model = "DH electronics STM32MP135F DHCOR DHSBC";
+   compatible = "dh,stm32mp135f-dhcor-dhsbc",
+"dh,stm32mp135f-dhcor-som",
+"st,stm32mp135";
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   serial2 = 
+   serial3 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+_1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a _usb_cc_pins_b>;
+   vdda-supply = <_adc>;
+   vref-supply = <_adc>;
+   status = "okay";
+
+   adc1: adc@0 {
+   status = "okay";
+
+   /*
+* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
+* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+* Use arbitrary margin here (e.g. 5us).
+*
+* The pinmux pins must be set as ANALOG, use datasheet
+* DS13483 Table 7. STM32MP135C/F ball definitions to
+* find out which 'pin name' maps to which 'additional
+* functions', which lists the mapping between pin and
+* ADC channel. In this case, PA5 maps to ADC1_INP2 and
+* PF13 maps to ADC1_INP11 .
+*/
+   channel@2 {
+   reg = <2>;
+   st,min-sample-time-ns = <5000>;
+   };
+
+   channel@11 {
+   reg = <11>;
+   st,min-sample-time-ns = <5000>;
+   };
+
+   /* Expansion connector: INP12:pin29 */
+   channel@12 {
+   reg = <12>;
+   st,min-sample-time-ns = <5000>;
+   };
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-0 = <_rgmii_pins_a>;
+   pinctrl-1 = <_rgmii_sleep_pins_a>;
+   pinctrl-names = "default", "sleep";
+   phy-mode = "rgmii-id";
+   phy-handle =