e OK in practice too.
Acked-by: Stephen Warren
> Thanks,
> JC
>
> On 3/18/20 1:44 AM, Tom Warren wrote:
>> -Original Message-
>> From: Stephen Warren
>> Sent: Tuesday, March 17, 2020 10:30 AM
>> To: Tom Warren
>> Cc: u-boot@lists.denx.de; Jui
10:30 AM
> To: Tom Warren
> Cc: u-boot@lists.denx.de; Jui Chang Kuo
> Subject: Re: [PATCH 2/5] t210: do not enable PLLE and UPHY PLL HW PWRSEQ
>
> External email: Use caution opening links or attachments
>
>
> On 3/16/20 1:40 PM, twar...@nvidia.com wrote:
-Original Message-
From: Stephen Warren
Sent: Tuesday, March 17, 2020 10:30 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Jui Chang Kuo
Subject: Re: [PATCH 2/5] t210: do not enable PLLE and UPHY PLL HW PWRSEQ
External email: Use caution opening links or attachments
On 3/16/20 1:40 PM
On 3/16/20 1:40 PM, twar...@nvidia.com wrote:
> From: JC Kuo
>
> This commit removes the programming sequence that enables PLLE and UPHY
> PLL hardware power sequencers. Per TRM, boot software should enable PLLE
> and UPHY PLLs in software controlled power-on state and should power
> down PLL
From: JC Kuo
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
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