From: Peng Fan <peng....@nxp.com>
Add i.MX8ULP iomuxc support
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/include/asm/arch-imx8ulp/iomux.h | 82 +++++++++++++++++++++++
arch/arm/mach-imx/imx8ulp/iomux.c | 63 ++++++++++++++++-
2 files changed, 144 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/iomux.h
diff --git a/arch/arm/include/asm/arch-imx8ulp/iomux.h
b/arch/arm/include/asm/arch-imx8ulp/iomux.h
new file mode 100644
index 0000000000..3c8f2e067e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/iomux.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __MACH_IMX8ULP_IOMUX_H__
+#define __MACH_IMX8ULP_IOMUX_H__
+
+typedef u64 iomux_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT 0
+#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT 16
+#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT 32
+#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_SEL_INPUT_SHIFT 38
+#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+#define MUX_PAD_CTRL_SHIFT 42
+#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
+
+#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,
sel_input, pad_ctrl) \
+ (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
+ ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
+ ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
+ ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
+ ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) |
MUX_PAD_CTRL(pad))
+
+#define IOMUX_CONFIG_MPORTS 0x20
+#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
MUX_MODE_SHIFT)
+
+/* Bit definition below needs to be fixed acccording to ulp rm */
+
+#define NO_PAD_CTRL BIT(18)
+#define PAD_CTL_OBE_ENABLE BIT(17)
+#define PAD_CTL_IBE_ENABLE BIT(16)
+#define PAD_CTL_DSE BIT(6)
+#define PAD_CTL_ODE BIT(5)
+#define PAD_CTL_SRE_FAST (0 << 2)
+#define PAD_CTL_SRE_SLOW BIT(2)
+#define PAD_CTL_PUE BIT(1)
+#define PAD_CTL_PUS_UP (BIT(0) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
+
+#define IOMUXC_PCR_MUX_ALT0 (0 << 8)
+#define IOMUXC_PCR_MUX_ALT1 (1 << 8)
+#define IOMUXC_PCR_MUX_ALT2 (2 << 8)
+#define IOMUXC_PCR_MUX_ALT3 (3 << 8)
+#define IOMUXC_PCR_MUX_ALT4 (4 << 8)
+#define IOMUXC_PCR_MUX_ALT5 (5 << 8)
+#define IOMUXC_PCR_MUX_ALT6 (6 << 8)
+#define IOMUXC_PCR_MUX_ALT7 (7 << 8)
+#define IOMUXC_PCR_MUX_ALT8 (8 << 8)
+#define IOMUXC_PCR_MUX_ALT9 (9 << 8)
+#define IOMUXC_PCR_MUX_ALT10 (10 << 8)
+#define IOMUXC_PCR_MUX_ALT11 (11 << 8)
+#define IOMUXC_PCR_MUX_ALT12 (12 << 8)
+#define IOMUXC_PCR_MUX_ALT13 (13 << 8)
+#define IOMUXC_PCR_MUX_ALT14 (14 << 8)
+#define IOMUXC_PCR_MUX_ALT15 (15 << 8)
+
+#define IOMUXC_PSMI_IMUX_ALT0 (0x0)
+#define IOMUXC_PSMI_IMUX_ALT1 (0x1)
+#define IOMUXC_PSMI_IMUX_ALT2 (0x2)
+#define IOMUXC_PSMI_IMUX_ALT3 (0x3)
+#define IOMUXC_PSMI_IMUX_ALT4 (0x4)
+#define IOMUXC_PSMI_IMUX_ALT5 (0x5)
+#define IOMUXC_PSMI_IMUX_ALT6 (0x6)
+#define IOMUXC_PSMI_IMUX_ALT7 (0x7)
+
+#define IOMUXC_PCR_MUX_ALT_SHIFT (8)
+#define IOMUXC_PCR_MUX_ALT_MASK (0xF00)
+#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
+
+void imx8ulp_iomux_setup_pad(iomux_cfg_t pad);
+void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, unsigned
count);
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c
b/arch/arm/mach-imx/imx8ulp/iomux.c
index c52ccdeaea..71a8c59d64 100644
--- a/arch/arm/mach-imx/imx8ulp/iomux.c
+++ b/arch/arm/mach-imx/imx8ulp/iomux.c
@@ -1,4 +1,65 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+
+/*
+ * iomuxc0 base address. In imx7ulp-pins.h,
+ * the offsets of pins in iomuxc0 are from 0xD000,
+ * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
+ */
+static void *base_mports = (void *)(0x280A1000);
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void imx8ulp_iomux_setup_pad(iomux_cfg_t pad)
+{
+ u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs =
+ (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32 sel_input =
+ (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ u32 pad_ctrl_ofs = mux_ctrl_ofs;
+ u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+
+ if (mux_mode & IOMUX_CONFIG_MPORTS) {
+ mux_mode &= ~IOMUX_CONFIG_MPORTS;
+ base = base_mports;
+ } else {
+ base = (void *)IOMUXC_BASE_ADDR;
+ }
+
+ __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
+ IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
+
+ if (sel_input_ofs)
+ __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), base +
sel_input_ofs);
+
+ if (!(pad_ctrl & NO_PAD_CTRL))
+ __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
+ IOMUXC_PCR_MUX_ALT_MASK) |
+ (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
+ base + pad_ctrl_ofs);
+}
+
+/* configures a list of pads within declared with IOMUX_PADS macro */
+void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count)
+{
+ iomux_cfg_t const *p = pad_list;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ imx8ulp_iomux_setup_pad(*p);
+ p++;
+ }
+}
--
2.30.0
