Lukasz Majewski ; Pragnesh
> Patel ; Jagan Teki
> ; Simon Glass ;
> twoer...@gmail.com; Patrick Wildt ; Fabio Estevam
> ; Weijie Gao ; Eugeniy
> Paltsev
> Subject: Re: [PATCH 4/5] sifive: reset: add DM based reset driver for SiFive
> SoC's
>
> [External Email] Do not click
On Mon, Jun 22, 2020 at 8:28 PM Sagar Shrikant Kadam
wrote:
>
> PRCI module within SiFive SoC's has register with which we can
> reset the sub-systems within the SoC. The resets to DDR and ethernet
> sub systems within FU540-C000 SoC are active low, and are hold low
> by default on power-up.
On 6/24/20 1:15 AM, Bin Meng wrote:
> Hi Sean,
>
> On Wed, Jun 24, 2020 at 1:04 PM Sean Anderson wrote:
>>
>> On 6/24/20 1:01 AM, Bin Meng wrote:
>>> Hi Sean,
>>>
>>> On Wed, Jun 24, 2020 at 12:17 PM Sean Anderson wrote:
On 6/22/20 8:27 AM, Sagar Shrikant Kadam wrote:
> The resets
Hi Sean,
On Wed, Jun 24, 2020 at 1:04 PM Sean Anderson wrote:
>
> On 6/24/20 1:01 AM, Bin Meng wrote:
> > Hi Sean,
> >
> > On Wed, Jun 24, 2020 at 12:17 PM Sean Anderson wrote:
> >>
> >> On 6/22/20 8:27 AM, Sagar Shrikant Kadam wrote:
> >>> The resets to DDR and ethernet sub-system are
On 6/24/20 1:01 AM, Bin Meng wrote:
> Hi Sean,
>
> On Wed, Jun 24, 2020 at 12:17 PM Sean Anderson wrote:
>>
>> On 6/22/20 8:27 AM, Sagar Shrikant Kadam wrote:
>>> The resets to DDR and ethernet sub-system are connected to
>>> PRCI device reset control register, these reset signals
>>> are active
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register
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