Re: [PATCH V2] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

On Wed, Sep 08, 2021 at 03:28:59PM -0500, Nishanth Menon wrote: > From: Roger Quadros > > NB0 is bridge to SRAM and NB1 is bridge to DDR. > > To ensure that SRAM transfers are not stalled due to delays during DDR > refreshes, SRAM traffic should be higher priority (threadmap=2) than > DDR

[PATCH V2] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge

From: Roger Quadros NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This fixup is critical to provide deterministic access