The following series of patches add support for PCIe + QSGMII multilink configuration on J721e EVM. The PHY lanes are configured in U-Boot and, PCIe driver in Kernel and QSGMII driver in the ethernet firmware use them.
Notes: - Patches 1 -8 and 13 - 22 are ported from upstream kernel v5.17-rc1 - Patch 24, syncs with linux kernel dt, with the following patch https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=608996 Changes since v1: - Fixed the logic for skipping multilink configuration in patch 23 - Fixed the offset calcualation for SIERRA_PHY_PCS_LANE_CDB_OFFSET and SIERRA_PHY_PMA_LANE_CDB_OFFSET in patches 18 and 21. Aswath Govindraju (8): phy: cadence: Sierra: Add a UCLASS_PHY device for links phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE board: ti: j721e: evm.c: Add support for probing SerDes0 arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 phy: cadence: Sierra: Add support for skipping configuration arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII include: configs: j721e_evm: Add support to boot ethfw core in j721e Kishon Vijay Abraham I (6): phy: cadence: Sierra: Fix PHY power_on sequence phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes phy: cadence: Sierra: Move all clk_get_*() to a separate function phy: cadence: Sierra: Move all reset_control_get*() to a separate function phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Sanket Parmar (1): phy: cadence: sierra: Fix for USB3 U1/U2 state Swapnil Jakhade (10): phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree. phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration .../k3-j721e-common-proc-board-u-boot.dtsi | 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 14 +- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 32 + board/ti/j721e/evm.c | 37 + configs/j721e_evm_a72_defconfig | 2 +- drivers/phy/cadence/phy-cadence-sierra.c | 1537 +++++++++++++++-- drivers/phy/ti/phy-j721e-wiz.c | 2 +- include/configs/j721e_evm.h | 19 +- include/dt-bindings/phy/phy-cadence.h | 4 + 9 files changed, 1494 insertions(+), 168 deletions(-) -- 2.17.1