Re: [PATCH v2 01/11] arm: dts: Add Mercury+ AA1 devicetrees

2022-05-27 Thread Simon Glass
On Thu, 26 May 2022 at 07:37, Paweł Anikiel  wrote:
>
> Devicetree headers for Mercury+ AA1 module
>
> Signed-off-by: Paweł Anikiel 
> ---
>  .../socfpga_arria10_mercury_aa1-u-boot.dtsi   | 54 ++
>  arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++
>  2 files changed, 126 insertions(+)
>  create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi

Reviewed-by: Simon Glass 


[PATCH v2 01/11] arm: dts: Add Mercury+ AA1 devicetrees

2022-05-26 Thread Paweł Anikiel
Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel 
---
 .../socfpga_arria10_mercury_aa1-u-boot.dtsi   | 54 ++
 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++
 2 files changed, 126 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
new file mode 100644
index 00..365e05100a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+   chosen {
+   firmware-loader = <&fs_loader0>;
+   };
+
+   fs_loader0: fs-loader {
+   u-boot,dm-pre-reloc;
+   compatible = "u-boot,fs-loader";
+   phandlepart = <&mmc 1>;
+   };
+};
+
+&atsha204a {
+   u-boot,dm-pre-reloc;
+};
+
+&fpga_mgr {
+   u-boot,dm-pre-reloc;
+   altr,bitstream = "fpga.itb";
+};
+
+&i2c1 {
+   u-boot,dm-pre-reloc;
+};
+
+&main_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&mmc {
+   u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi 
b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
new file mode 100644
index 00..fee1fc39bb
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+
+/ {
+   aliases {
+   ethernet0 = &gmac0;
+   serial1 = &uart1;
+   };
+
+   chosen {
+   stdout-path = "serial1:115200n8";
+   };
+
+   memory@0 {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+};
+
+&gmac0 {
+   phy-mode = "rgmii";
+   phy-handle = <&phy3>;
+
+   max-frame-size = <3800>;
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy3: ethernet-phy@3 {
+   reg = <3>;
+   txd0-skew-ps = <0>; /* -420ps */
+   txd1-skew-ps = <0>; /* -420ps */
+   txd2-skew-ps = <0>; /* -420ps */
+   txd3-skew-ps = <0>; /* -420ps */
+   rxd0-skew-ps = <420>; /* 0ps */
+   rxd1-skew-ps = <420>; /* 0ps */
+   rxd2-skew-ps = <420>; /* 0ps */
+   rxd3-skew-ps = <420>; /* 0ps */
+   txen-skew-ps = <0>; /* -420ps */
+   txc-skew-ps = <1860>; /* 960ps */
+   rxdv-skew-ps = <420>; /* 0ps */
+   rxc-skew-ps = <1680>; /* 780ps */
+   };
+   };
+};
+
+&i2c1 {
+   atsha204a: atsha204a@64 {
+   compatible = "atmel,atsha204a";
+   reg = <0x64>;
+   };
+
+   isl12022: isl12022@6f {
+   compatible = "isil,isl12022";
+   reg = <0x6f>;
+   };
+};
+
+&mmc {
+   cap-sd-highspeed;
+   broken-cd;
+   bus-width = <4>;
+};
+
+&osc1 {
+   clock-frequency = <>;
+};
-- 
2.36.1.124.g0e6072fb45-goog