Re: [PATCH v2 1/2] mtd: spi-nor-core: Consider reserved bits in CFR5 register

2023-01-22 Thread Dhruva Gole
On 20/01/23 08:58, tkuw584...@gmail.com wrote: From: Takahiro Kuwano CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition, stop using magic numbers and describe the missing bit fields in CFR5

Re: [PATCH v2 1/2] mtd: spi-nor-core: Consider reserved bits in CFR5 register

2023-01-20 Thread Tudor Ambarus
On 1/20/23 03:28, tkuw584...@gmail.com wrote: From: Takahiro Kuwano CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition, stop using magic numbers and describe the missing bit fields in CFR5

[PATCH v2 1/2] mtd: spi-nor-core: Consider reserved bits in CFR5 register

2023-01-19 Thread tkuw584924
From: Takahiro Kuwano CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition, stop using magic numbers and describe the missing bit fields in CFR5 register. This is useful for both readability and future