From: Peng Fan <peng....@nxp.com>
Convert i.MX8MQ EVK to OF_UPSTREAM
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/imx8mq-evk.dts | 712 ----------------------------------------
arch/arm/mach-imx/imx8m/Kconfig | 1 +
configs/imx8mq_evk_defconfig | 2 +-
4 files changed, 2 insertions(+), 714 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d85a33055c9..b76ee4d609b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1090,7 +1090,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
imx8mn-var-som-symphony.dtb \
- imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
imx8mq-mnt-reform2.dtb \
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
deleted file mode 100644
index 82387b9cb80..00000000000
--- a/arch/arm/dts/imx8mq-evk.dts
+++ /dev/null
@@ -1,712 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2017 NXP
- * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <ker...@pengutronix.de>
- */
-
-/dts-v1/;
-
-#include "imx8mq.dtsi"
-
-/ {
- model = "NXP i.MX8MQ EVK";
- compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
-
- chosen {
- stdout-path = &uart1;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x00000000 0x40000000 0 0xc0000000>;
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- reg_pcie1: regulator-pcie {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie1_reg>;
- regulator-name = "MPCIE_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc2_vmmc: regulator-vsd-3v3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2>;
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- buck2_reg: regulator-buck2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_buck2>;
- compatible = "regulator-gpio";
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1000000>;
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- states = <1000000 0x0
- 900000 0x1>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ir>;
- linux,autosuspend-period = <125>;
- };
-
- audio_codec_bt_sco: audio-codec-bt-sco {
- compatible = "linux,bt-sco";
- #sound-dai-cells = <1>;
- };
-
- wm8524: audio-codec {
- #sound-dai-cells = <0>;
- compatible = "wlf,wm8524";
- wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- sound-bt-sco {
- compatible = "simple-audio-card";
- simple-audio-card,name = "bt-sco-audio";
- simple-audio-card,format = "dsp_a";
- simple-audio-card,bitclock-inversion;
- simple-audio-card,frame-master = <&btcpu>;
- simple-audio-card,bitclock-master = <&btcpu>;
-
- btcpu: simple-audio-card,cpu {
- sound-dai = <&sai3>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <16>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&audio_codec_bt_sco 1>;
- };
- };
-
- sound-wm8524 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "wm8524-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&cpudai>;
- simple-audio-card,bitclock-master = <&cpudai>;
- simple-audio-card,widgets =
- "Line", "Left Line Out Jack",
- "Line", "Right Line Out Jack";
- simple-audio-card,routing =
- "Left Line Out Jack", "LINEVOUTL",
- "Right Line Out Jack", "LINEVOUTR";
-
- cpudai: simple-audio-card,cpu {
- sound-dai = <&sai2>;
- };
-
- link_codec: simple-audio-card,codec {
- sound-dai = <&wm8524>;
- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
- };
- };
-
- sound-spdif {
- compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
- spdif-controller = <&spdif1>;
- spdif-out;
- spdif-in;
- };
-
- sound-hdmi-arc {
- compatible = "fsl,imx-audio-spdif";
- model = "imx-hdmi-arc";
- spdif-controller = <&spdif2>;
- spdif-in;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2_reg>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
- status = "okay";
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- /*
- * On imx8mq B0 PLL can't be bypassed so low bus is 166M
- */
- opp-166M {
- opp-hz = /bits/ 64 <166935483>;
- };
-
- opp-800M {
- opp-hz = /bits/ 64 <800000000>;
- };
- };
-};
-
-&dphy {
- status = "okay";
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- qca,disable-smarteee;
- vddio-supply = <&vddh>;
-
- vddh: vddh-regulator {
- };
- };
- };
-};
-
-&gpio5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wifi_reset>;
-
- wl-reg-on-hog {
- gpio-hog;
- gpios = <29 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic@8 {
- compatible = "fsl,pfuze100";
- reg = <0x8>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- sw3a_reg: sw3ab {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <975000>;
- regulator-always-on;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1675000>;
- regulator-max-microvolt = <1975000>;
- regulator-always-on;
- };
-
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1625000>;
- regulator-max-microvolt = <1875000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3625000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
-};
-
-&lcdif {
- status = "okay";
-};
-
-&mipi_dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- panel@0 {
- pinctrl-0 = <&pinctrl_mipi_dsi>;
- pinctrl-names = "default";
- compatible = "raydium,rm67191";
- reg = <0>;
- reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
- dsi-lanes = <4>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&mipi_dsi_out>;
- };
- };
- };
-
- ports {
- port@1 {
- reg = <1>;
- mipi_dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
- <&clk IMX8MQ_CLK_PCIE1_AUX>,
- <&clk IMX8MQ_CLK_PCIE1_PHY>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
- vph-supply = <&vgen5_reg>;
- status = "okay";
-};
-
-&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie1>;
- reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
- <&clk IMX8MQ_CLK_PCIE2_AUX>,
- <&clk IMX8MQ_CLK_PCIE2_PHY>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
- vpcie-supply = <®_pcie1>;
- vph-supply = <&vgen5_reg>;
- status = "okay";
-};
-
-&pgc_gpu {
- power-supply = <&sw1a_reg>;
-};
-
-&pgc_vpu {
- power-supply = <&sw1c_reg>;
-};
-
-&qspi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi>;
- status = "okay";
-
- n25q256a: flash@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&sai2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai2>;
- assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk
IMX8MQ_CLK_SAI2>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk
IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
- status = "okay";
-};
-
-&sai3 {
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&spdif1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spdif1>;
- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&spdif2 {
- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usdhc1 {
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- vqmmc-supply = <&sw4_reg>;
- bus-width = <8>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
-};
-
-&usdhc2 {
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_buck2: vddarmgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
0x4000007f
- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
0x4000007f
- >;
- };
-
- pinctrl_ir: irgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
- >;
- };
-
- pinctrl_mipi_dsi: mipidsigrp {
- fsl,pins = <
- MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
- MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
- >;
- };
-
- pinctrl_pcie1: pcie1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
- MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
- >;
- };
-
- pinctrl_pcie1_reg: pcie1reggrp {
- fsl,pins = <
- MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
- >;
- };
-
- pinctrl_qspi: qspigrp {
- fsl,pins = <
- MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
- MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_reg_usdhc2: regusdhc2gpiogrp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
- >;
- };
-
- pinctrl_sai2: sai2grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
- MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
- >;
- };
-
- pinctrl_spdif1: spdif1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
- MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_wdog: wdog1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-
- pinctrl_wifi_reset: wifiresetgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
- >;
- };
-};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 5db643c1958..6f68ee2c27d 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -53,6 +53,7 @@ config TARGET_IMX8MQ_EVK
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 941b845006a..3a2d88aec45 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -11,7 +11,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_EVK=y
CONFIG_DM_RESET=y
--
2.35.3
