Hi Conor,
> On Tue, 2022-10-25 at 19:50 +, Conor Dooley - M52691 wrote:
> On 22/10/2022 12:21, Conor Dooley wrote:
> >
> > On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> > > In the v2022.10 Icicle reference design, the seg registers are
> > > going to be
> >
> > Hey
On Sat, 2022-10-22 at 12:21 +0100, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
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>
> On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> > In the v2022.10 Icicle reference design, the seg registers are
> > going
On 22/10/2022 12:21, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
>> In the v2022.10 Icicle reference design, the seg registers are going to be
>
> Hey
On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> In the v2022.10 Icicle reference design, the seg registers are going to be
Hey Padmarao,
Since the release was done the other day I think that this should be
s/are going to be/have been
> changed, resulting in a required change
In the v2022.10 Icicle reference design, the seg registers are going to be
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific
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