Re: [PATCH v2 1/5] arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks

On Tue, Sep 07, 2021 at 05:16:54PM -0500, Dave Gerlach wrote: > From: Suman Anna > > The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 > divisors to generate the final FOUTPOSTDIV clock. These are in sequence > with POSTDIV2 following the POSTDIV1 clock. The current J721E

[PATCH v2 1/5] arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks

From: Suman Anna The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock,