On Fri, Jan 28, 2022 at 01:41:39PM +0530, Aswath Govindraju wrote:
> The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
> function device_probe, the corresponding clocks are probed before calling
> the device's probe. The PLL_CMNLC mux clock can only be created after the
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
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