Re: [PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b

2024-03-12 Thread Leo Liang
On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote:
> Add dcache operations invalidate_dcache_range and flush_dcache_range for
> cv1800b.
> 
> Signed-off-by: Kongyang Liu 
> ---
> 
> (no changes since v1)
> 
>  arch/riscv/cpu/cv1800b/Makefile |  1 +
>  arch/riscv/cpu/cv1800b/cache.c  | 45 +
>  2 files changed, 46 insertions(+)
>  create mode 100644 arch/riscv/cpu/cv1800b/cache.c

Reviewed-by: Leo Yu-Chi Liang 


[PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b

2024-03-09 Thread Kongyang Liu
Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.

Signed-off-by: Kongyang Liu 
---

(no changes since v1)

 arch/riscv/cpu/cv1800b/Makefile |  1 +
 arch/riscv/cpu/cv1800b/cache.c  | 45 +
 2 files changed, 46 insertions(+)
 create mode 100644 arch/riscv/cpu/cv1800b/cache.c

diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index da12e0f64e..95beb34b51 100644
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += dram.o
 obj-y += cpu.o
+obj-y += cache.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c
new file mode 100644
index 00..b8051e29e0
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cache.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu 
+ */
+
+#include 
+
+/*
+ * dcache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   00101010  rs1   000  0  0001011
+ *
+ * dcache.cpa rs1 (clean)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   00101001  rs1   000  0  0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   00101011  rs1   000  0  0001011
+ *
+ * sync.s
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   00011001 0  000  0  0001011
+ */
+#define DCACHE_IPA_A0  ".long 0x02a5000b"
+#define DCACHE_CPA_A0  ".long 0x0295000b"
+#define DCACHE_CIPA_A0 ".long 0x02b5000b"
+
+#define SYNC_S ".long 0x019b"
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+   register unsigned long i asm("a0") = start & 
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+   for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+   __asm__ __volatile__(DCACHE_IPA_A0);
+   __asm__ __volatile__(SYNC_S);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+   register unsigned long i asm("a0") = start & 
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+   for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+   __asm__ __volatile__(DCACHE_CPA_A0);
+   __asm__ __volatile__(SYNC_S);
+}
-- 
2.41.0