On Tue, Sep 07, 2021 at 05:16:55PM -0500, Dave Gerlach wrote:
> From: Suman Anna
>
> The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
> divisors to generate the final FOUTPOSTDIV clock. These are in sequence
> with POSTDIV2 following the POSTDIV1 clock. The current J7200
From: Suman Anna
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock,
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