[PATCH v2 2/8] ARM: dts: imx: Migrate iMX6QDL DRC02 DTs from Linux

2022-05-20 Thread sbabic
> Migrate DH DRC02 device trees from Linux commit 42226c989789
> (tag v5.18-rc7). No changes have been made, the DTs are exact copies.
> Furthermore add the DTB to dh_imx6_defconfig.
> Reviewed-by: Marek Vasut 
> Signed-off-by: Philip Oberfichtner 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v2 2/8] ARM: dts: imx: Migrate iMX6QDL DRC02 DTs from Linux

2022-05-20 Thread Philip Oberfichtner
Migrate DH DRC02 device trees from Linux commit 42226c989789
(tag v5.18-rc7). No changes have been made, the DTs are exact copies.
Furthermore add the DTB to dh_imx6_defconfig.

Reviewed-by: Marek Vasut 
Signed-off-by: Philip Oberfichtner 
---

(no changes since v1)

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/imx6qdl-dhcom-drc02.dtsi | 143 ++
 arch/arm/dts/imx6s-dhcom-drc02.dts|  30 ++
 configs/dh_imx6_defconfig |   2 +-
 4 files changed, 175 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx6qdl-dhcom-drc02.dtsi
 create mode 100644 arch/arm/dts/imx6s-dhcom-drc02.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f6..7bfdfb5313 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -771,6 +771,7 @@ dtb-y += \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard-revd1.dtb \
+   imx6s-dhcom-drc02.dtb
 
 endif
 
diff --git a/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi 
b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi
new file mode 100644
index 00..702cd4a1b2
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ */
+
+/ {
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+/*
+ * Special SoM hardware required which uses the pins from micro SD card. The
+ * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
+ * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
+ * card must be disabled and the uart1 rts/cts must be output on other DHCOM
+ * pins, see uart1 and usdhc3 node below.
+ */
+ {
+   status = "okay";
+};
+
+ {
+   /*
+* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+* GPIO line, however the i.MX6 UART driver assumes RX happens
+* during TX anyway and that it only controls drive enable DE
+* line. Hence, the RX is always enabled here.
+*/
+   rs485-rx-en-hog {
+   gpio-hog;
+   gpios = <18 0>; /* GPIO Q */
+   line-name = "rs485-rx-en";
+   output-low;
+   };
+};
+
+ {
+   gpio-line-names =
+   "", "", "", "", "", "", "", "",
+   "", "", "", "", "", "", "", "",
+   "", "", "", "", "", "", "", "",
+   "", "", "", "DRC02-In1", "", "", "", "";
+};
+
+ {
+   gpio-line-names =
+   "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
+   "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "",
+   "", "", "", "", "DRC02-Out1", "", "", "",
+   "", "", "", "", "", "", "", "";
+};
+
+ {
+   gpio-line-names =
+   "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "",
+   "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1",
+   "", "", "", "", "", "", "", "",
+   "", "", "", "", "", "", "", "";
+};
+
+ {
+   eeprom@50 {
+   compatible = "atmel,24c04";
+   reg = <0x50>;
+   pagesize = <16>;
+   };
+};
+
+ {
+   /*
+* Due to the use of can2 the signals for can2 Tx and Rx are routed to
+* DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs
+* for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
+*/
+   /delete-property/ uart-has-rtscts;
+   cts-gpios = < 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
+   pinctrl-0 = <_uart1 _dhcom_i _dhcom_m>;
+   pinctrl-names = "default";
+   rts-gpios = < 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+};
+
+ {
+   /*
+* On DRC02 this UART is used as RS485 interface and RS485_TX_En is
+* controlled by DHCOM GPIO P. So remove rts/cts pins and the property
+* uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
+* rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
+* node above.
+*/
+   /delete-property/ uart-has-rtscts;
+   linux,rs485-enabled-at-boot-time;
+   pinctrl-0 = <_uart5_core _dhcom_p _dhcom_q>;
+   pinctrl-names = "default";
+   rts-gpios = < 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
+};
+
+ {
+   disable-over-current;
+};
+
+ { /* SD card */
+   status = "okay";
+};
+
+ {
+   /*
+* Due to the use of can2 the micro SD card on module have to be
+* disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as
+* can2 Tx and Rx.
+*/
+   status = "disabled";
+};
+
+ {
+   pinctrl-0 = <
+   /*
+* The following DHCOM GPIOs are used on this board.
+* Therefore, they have been removed from the list 
below.
+* I: uart1 rts
+* M: uart1 cts
+* P: uart5 rs485-tx-en
+* Q: uart5 rs485-rx-en
+