Re: [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration

On Fri, Jan 28, 2022 at 01:41:47PM +0530, Aswath Govindraju wrote: > From: Swapnil Jakhade > > Add single link PCIe register configurations for no SSC and internal > SSC. Also, add missing PMA lane registers for external SSC. > > Signed-off-by: Swapnil Jakhade > Signed-off-by: Aswath

[PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration

From: Swapnil Jakhade Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade Signed-off-by: Aswath Govindraju --- drivers/phy/cadence/phy-cadence-sierra.c | 218 ++- 1