Re: [PATCH v2 5/5] clk: ti: k3: Update driver to account for divider flags

On Tue, Sep 07, 2021 at 05:16:58PM -0500, Dave Gerlach wrote: > From: Suman Anna > > The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in > turn serve as inputs to other HSDIV output clocks. These clocks use > the actual value to compute the divider clock rate, and need to be >

[PATCH v2 5/5] clk: ti: k3: Update driver to account for divider flags

From: Suman Anna The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and