Re: [PATCH v3] mips: dts: add initial support for ls1c300 SoC
> sorry for the late response but I was on vacation ;) long time no see. :) > > Am Donnerstag, dem 21.04.2022 um 20:31 -0400 schrieb Sean Anderson: > > On 4/18/22 4:45 PM, Du Huanpeng wrote: > > > Loongson 1C is a cost-effective SOC chip for industrial control and > > > the Internet of Things. The Loongson 1C includes a floating-point > > > processing unit, supports multiple types of memory, and supports > > > high-capacity MLC NAND Flash. Loongson 1C provides developers with > > > a > > > wealth of peripheral interfaces and on-chip modules, including > > > Camera > > > controller, USB OTG and USB HOST interfaces, AC97/I2S controller, > > > LCD > > > controller, SPI interface, UART interface, etc., providing > > > sufficient > > > computing power and multi-application connectivity. > > > > > > Some highlights of this SoC are: > > > - Single core LS232, MIPS32 instruction set compatible, main > > > frequency > > > 300MHZ > > > - 16KB data cache and 16KB instruction cache > > > - 64 bit float unit, hardware division > > > - 8/16 bit SDRAM controller, 45 ~ 133MHz > > > - 8/16 bit SRAM, NAND > > > - I2S/AC97, LCD, MAC, USB, OTG, SPI, I2C, PWM, CAN, SDIO, ADC > > > - 12 UARTs > > > > > > See Technical Reference Manual for details: > > > https://www.loongson.cn/ > > > > > > introduce base support for the ls1c300 SoC. > > > - debug UART2 > > > - serial console > > > - clock > > > - watchdog > > > - sysreset > > > - many uarts > > > > > > Signed-off-by: Du Huanpeng > > > --- > > > Changelog for v3: > > > - change cpu clock id from CLK_CPU to CLK_CPU_THROT > > > - migrate all APB dev's clock id to CLK_APB > > > - remove uarts' property to use default value <0> > > > - move /clocks/acc node to /soc/acc > > > - call clk_request() before use a clk > > > - make get_tbclk() return 1/2 clock of cpu > > > - disable debug_uart by default > > > - add ops for cpu_throt_factor clk > > > - declare MSEC_PER_SEC for converting between sec and msec > > > - return a error code when the wdt clock is out of range > > > - minor format and codingstyle fixes > > > - rebase to [9859465bfe838bc8264d45e1a1bed847bba74bad] > > > > > > Changelog for v2: > > > 1. dtsi: > > > add status disabled for uart0 ~ uart11 > > > remove bootargs from chosen > > > make serial0 alias for uart2 > > > oscillator remove @0 unit-address > > > change uart2 address to kuseg > > > > > > 2. cleanup Kconfig and update defconfig > > > - make these options configurable, disabled by default: > > > CMD_DM > > > DM_ETH > > > DM_GPIO > > > DM_SPI > > > DM_SPI_FLASH > > > DM_RESET > > > PINCONF > > > PINCTRL > > > PINMUX > > > RESET_LSMIPS > > > - make these options configurable, enabled by default: > > > CLK > > > DISPLAY_CPUINFO > > > SYSRESET > > > ROM_EXCEPTION_VECTORS > > > - disabled: > > > CONFIG_ENV_IS_IN_SPI_FLASH > > > > > > 3. fix codingstyle drivers/watchdog/lsmips-wdt.c > > > - priv->base + offset > > > - add comment for default clock value > > > > > > 4. remove address base definition header > > > - remove arch/mips/mach-lsmips/ls1c300/ls1c300.h > > > - clean up files uses this header > > > > > > 5. spl and debug uart > > > - add comment for spl & debug uart pinmuxing > > > - cleanup unused registers base header > > > > > > 6. dtsi > > > - add "loongson,ls1c300-uart" to all uart node > > > > > > 7. board dts > > > - add memory node to board dts, start at 0x8000, size 64MB > > > > > > 8. Kconfig > > > - make ROM_EXCEPTION_VECTORS user configureable > > > - enable ROM_EXCEPTION_VECTORS in defconfig > > > > > > 9. > > > - seperate sdram_init to sdram_init.S > > > - add macro helpers to do sdram, pll lowlevel init > > > > > > 10. dtsi > > > - move clock nodes to /clocks/xxx > > > > > > 11. > > > - define CONFIG_SKIP_LOWLEVEL_INIT to 1 > > > > > > 12. > > > - remove option PINCTRL_LS1C300 from Kconfig > > > > > > 13. > > > - dram_init, use get_ram_size() to detect ram size. > > > > > > 14. clk driver > > > - create custom clock ops for PLL > > > - remove debug code > > > > > > 15. > > > - rebase to 59bffec43a657598b194b9eb30dc01eec06078c7 > > > - remove CONFIG_SYS_MONITOR_BASE from include/configs/ > > > > > > > commit e4d741f8abc4a92426d3a826f99390c3abe02d61 > > > > Author: Tom Rini > > > > Date: Thu Mar 24 17:18:05 2022 -0400 > > > > > > > > Convert CONFIG_SYS_MONITOR_BASE to Kconfig > > > > > > MAINTAINERS | 13 ++ > > > arch/mips/Kconfig | 11 ++ > > > arch/mips/Makefile| 1 + > > > arch/mips/dts/Makefile| 1 + > > > arch/mips/dts/loongson32-ls1c300b.dtsi| 141 > > > ++ > > > arch/mips/dts/ls1c300-eval.dts| 31 +++ > > > arch/mips/mach-lsmips/Kconfig | 76 > > > arch/mips/mach-lsmips/Makefile| 6 + > > >
Re: [PATCH v3] mips: dts: add initial support for ls1c300 SoC
sorry for the late response but I was on vacation ;) Am Donnerstag, dem 21.04.2022 um 20:31 -0400 schrieb Sean Anderson: > On 4/18/22 4:45 PM, Du Huanpeng wrote: > > Loongson 1C is a cost-effective SOC chip for industrial control and > > the Internet of Things. The Loongson 1C includes a floating-point > > processing unit, supports multiple types of memory, and supports > > high-capacity MLC NAND Flash. Loongson 1C provides developers with > > a > > wealth of peripheral interfaces and on-chip modules, including > > Camera > > controller, USB OTG and USB HOST interfaces, AC97/I2S controller, > > LCD > > controller, SPI interface, UART interface, etc., providing > > sufficient > > computing power and multi-application connectivity. > > > > Some highlights of this SoC are: > > - Single core LS232, MIPS32 instruction set compatible, main > > frequency > > 300MHZ > > - 16KB data cache and 16KB instruction cache > > - 64 bit float unit, hardware division > > - 8/16 bit SDRAM controller, 45 ~ 133MHz > > - 8/16 bit SRAM, NAND > > - I2S/AC97, LCD, MAC, USB, OTG, SPI, I2C, PWM, CAN, SDIO, ADC > > - 12 UARTs > > > > See Technical Reference Manual for details: > > https://www.loongson.cn/ > > > > introduce base support for the ls1c300 SoC. > > - debug UART2 > > - serial console > > - clock > > - watchdog > > - sysreset > > - many uarts > > > > Signed-off-by: Du Huanpeng > > --- > > Changelog for v3: > > - change cpu clock id from CLK_CPU to CLK_CPU_THROT > > - migrate all APB dev's clock id to CLK_APB > > - remove uarts' property to use default value <0> > > - move /clocks/acc node to /soc/acc > > - call clk_request() before use a clk > > - make get_tbclk() return 1/2 clock of cpu > > - disable debug_uart by default > > - add ops for cpu_throt_factor clk > > - declare MSEC_PER_SEC for converting between sec and msec > > - return a error code when the wdt clock is out of range > > - minor format and codingstyle fixes > > - rebase to [9859465bfe838bc8264d45e1a1bed847bba74bad] > > > > Changelog for v2: > > 1. dtsi: > > add status disabled for uart0 ~ uart11 > > remove bootargs from chosen > > make serial0 alias for uart2 > > oscillator remove @0 unit-address > > change uart2 address to kuseg > > > > 2. cleanup Kconfig and update defconfig > > - make these options configurable, disabled by default: > > CMD_DM > > DM_ETH > > DM_GPIO > > DM_SPI > > DM_SPI_FLASH > > DM_RESET > > PINCONF > > PINCTRL > > PINMUX > > RESET_LSMIPS > > - make these options configurable, enabled by default: > > CLK > > DISPLAY_CPUINFO > > SYSRESET > > ROM_EXCEPTION_VECTORS > > - disabled: > > CONFIG_ENV_IS_IN_SPI_FLASH > > > > 3. fix codingstyle drivers/watchdog/lsmips-wdt.c > > - priv->base + offset > > - add comment for default clock value > > > > 4. remove address base definition header > > - remove arch/mips/mach-lsmips/ls1c300/ls1c300.h > > - clean up files uses this header > > > > 5. spl and debug uart > > - add comment for spl & debug uart pinmuxing > > - cleanup unused registers base header > > > > 6. dtsi > > - add "loongson,ls1c300-uart" to all uart node > > > > 7. board dts > > - add memory node to board dts, start at 0x8000, size 64MB > > > > 8. Kconfig > > - make ROM_EXCEPTION_VECTORS user configureable > > - enable ROM_EXCEPTION_VECTORS in defconfig > > > > 9. > > - seperate sdram_init to sdram_init.S > > - add macro helpers to do sdram, pll lowlevel init > > > > 10. dtsi > > - move clock nodes to /clocks/xxx > > > > 11. > > - define CONFIG_SKIP_LOWLEVEL_INIT to 1 > > > > 12. > > - remove option PINCTRL_LS1C300 from Kconfig > > > > 13. > > - dram_init, use get_ram_size() to detect ram size. > > > > 14. clk driver > > - create custom clock ops for PLL > > - remove debug code > > > > 15. > > - rebase to 59bffec43a657598b194b9eb30dc01eec06078c7 > > - remove CONFIG_SYS_MONITOR_BASE from include/configs/ > > > > > commit e4d741f8abc4a92426d3a826f99390c3abe02d61 > > > Author: Tom Rini > > > Date: Thu Mar 24 17:18:05 2022 -0400 > > > > > > Convert CONFIG_SYS_MONITOR_BASE to Kconfig > > > > MAINTAINERS | 13 ++ > > arch/mips/Kconfig | 11 ++ > > arch/mips/Makefile| 1 + > > arch/mips/dts/Makefile| 1 + > > arch/mips/dts/loongson32-ls1c300b.dtsi| 141 > > ++ > > arch/mips/dts/ls1c300-eval.dts| 31 +++ > > arch/mips/mach-lsmips/Kconfig | 76 > > arch/mips/mach-lsmips/Makefile| 6 + > > arch/mips/mach-lsmips/cpu.c | 19 ++ > > arch/mips/mach-lsmips/include/mach/serial.h | 16 ++ > > arch/mips/mach-lsmips/ls1c300/Makefile| 7 + > > arch/mips/mach-lsmips/ls1c300/gpio.c | 66 +++ > > arch/mips/mach-lsmips/ls1c300/init.c
Re: [PATCH v3] mips: dts: add initial support for ls1c300 SoC
On 4/18/22 4:45 PM, Du Huanpeng wrote: Loongson 1C is a cost-effective SOC chip for industrial control and the Internet of Things. The Loongson 1C includes a floating-point processing unit, supports multiple types of memory, and supports high-capacity MLC NAND Flash. Loongson 1C provides developers with a wealth of peripheral interfaces and on-chip modules, including Camera controller, USB OTG and USB HOST interfaces, AC97/I2S controller, LCD controller, SPI interface, UART interface, etc., providing sufficient computing power and multi-application connectivity. Some highlights of this SoC are: - Single core LS232, MIPS32 instruction set compatible, main frequency 300MHZ - 16KB data cache and 16KB instruction cache - 64 bit float unit, hardware division - 8/16 bit SDRAM controller, 45 ~ 133MHz - 8/16 bit SRAM, NAND - I2S/AC97, LCD, MAC, USB, OTG, SPI, I2C, PWM, CAN, SDIO, ADC - 12 UARTs See Technical Reference Manual for details: https://www.loongson.cn/ introduce base support for the ls1c300 SoC. - debug UART2 - serial console - clock - watchdog - sysreset - many uarts Signed-off-by: Du Huanpeng --- Changelog for v3: - change cpu clock id from CLK_CPU to CLK_CPU_THROT - migrate all APB dev's clock id to CLK_APB - remove uarts' property to use default value <0> - move /clocks/acc node to /soc/acc - call clk_request() before use a clk - make get_tbclk() return 1/2 clock of cpu - disable debug_uart by default - add ops for cpu_throt_factor clk - declare MSEC_PER_SEC for converting between sec and msec - return a error code when the wdt clock is out of range - minor format and codingstyle fixes - rebase to [9859465bfe838bc8264d45e1a1bed847bba74bad] Changelog for v2: 1. dtsi: add status disabled for uart0 ~ uart11 remove bootargs from chosen make serial0 alias for uart2 oscillator remove @0 unit-address change uart2 address to kuseg 2. cleanup Kconfig and update defconfig - make these options configurable, disabled by default: CMD_DM DM_ETH DM_GPIO DM_SPI DM_SPI_FLASH DM_RESET PINCONF PINCTRL PINMUX RESET_LSMIPS - make these options configurable, enabled by default: CLK DISPLAY_CPUINFO SYSRESET ROM_EXCEPTION_VECTORS - disabled: CONFIG_ENV_IS_IN_SPI_FLASH 3. fix codingstyle drivers/watchdog/lsmips-wdt.c - priv->base + offset - add comment for default clock value 4. remove address base definition header - remove arch/mips/mach-lsmips/ls1c300/ls1c300.h - clean up files uses this header 5. spl and debug uart - add comment for spl & debug uart pinmuxing - cleanup unused registers base header 6. dtsi - add "loongson,ls1c300-uart" to all uart node 7. board dts - add memory node to board dts, start at 0x8000, size 64MB 8. Kconfig - make ROM_EXCEPTION_VECTORS user configureable - enable ROM_EXCEPTION_VECTORS in defconfig 9. - seperate sdram_init to sdram_init.S - add macro helpers to do sdram, pll lowlevel init 10. dtsi - move clock nodes to /clocks/xxx 11. - define CONFIG_SKIP_LOWLEVEL_INIT to 1 12. - remove option PINCTRL_LS1C300 from Kconfig 13. - dram_init, use get_ram_size() to detect ram size. 14. clk driver - create custom clock ops for PLL - remove debug code 15. - rebase to 59bffec43a657598b194b9eb30dc01eec06078c7 - remove CONFIG_SYS_MONITOR_BASE from include/configs/ commit e4d741f8abc4a92426d3a826f99390c3abe02d61 Author: Tom Rini Date: Thu Mar 24 17:18:05 2022 -0400 Convert CONFIG_SYS_MONITOR_BASE to Kconfig MAINTAINERS | 13 ++ arch/mips/Kconfig | 11 ++ arch/mips/Makefile| 1 + arch/mips/dts/Makefile| 1 + arch/mips/dts/loongson32-ls1c300b.dtsi| 141 ++ arch/mips/dts/ls1c300-eval.dts| 31 +++ arch/mips/mach-lsmips/Kconfig | 76 arch/mips/mach-lsmips/Makefile| 6 + arch/mips/mach-lsmips/cpu.c | 19 ++ arch/mips/mach-lsmips/include/mach/serial.h | 16 ++ arch/mips/mach-lsmips/ls1c300/Makefile| 7 + arch/mips/mach-lsmips/ls1c300/gpio.c | 66 +++ arch/mips/mach-lsmips/ls1c300/init.c | 63 ++ arch/mips/mach-lsmips/ls1c300/lowlevel_init.S | 136 + arch/mips/mach-lsmips/ls1c300/sdram.S | 94 + arch/mips/mach-lsmips/ls1c300/serial.c| 109 +++ arch/mips/mach-lsmips/spl.c | 46 + board/loongson/ls1c300-eval/Kconfig | 12 ++ board/loongson/ls1c300-eval/MAINTAINERS | 7 + board/loongson/ls1c300-eval/Makefile | 3 + board/loongson/ls1c300-eval/board.c | 20 ++ configs/ls1c300_defconfig | 49 + drivers/clk/Makefile | 1 +
[PATCH v3] mips: dts: add initial support for ls1c300 SoC
Loongson 1C is a cost-effective SOC chip for industrial control and the Internet of Things. The Loongson 1C includes a floating-point processing unit, supports multiple types of memory, and supports high-capacity MLC NAND Flash. Loongson 1C provides developers with a wealth of peripheral interfaces and on-chip modules, including Camera controller, USB OTG and USB HOST interfaces, AC97/I2S controller, LCD controller, SPI interface, UART interface, etc., providing sufficient computing power and multi-application connectivity. Some highlights of this SoC are: - Single core LS232, MIPS32 instruction set compatible, main frequency 300MHZ - 16KB data cache and 16KB instruction cache - 64 bit float unit, hardware division - 8/16 bit SDRAM controller, 45 ~ 133MHz - 8/16 bit SRAM, NAND - I2S/AC97, LCD, MAC, USB, OTG, SPI, I2C, PWM, CAN, SDIO, ADC - 12 UARTs See Technical Reference Manual for details: https://www.loongson.cn/ introduce base support for the ls1c300 SoC. - debug UART2 - serial console - clock - watchdog - sysreset - many uarts Signed-off-by: Du Huanpeng --- Changelog for v3: - change cpu clock id from CLK_CPU to CLK_CPU_THROT - migrate all APB dev's clock id to CLK_APB - remove uarts' property to use default value <0> - move /clocks/acc node to /soc/acc - call clk_request() before use a clk - make get_tbclk() return 1/2 clock of cpu - disable debug_uart by default - add ops for cpu_throt_factor clk - declare MSEC_PER_SEC for converting between sec and msec - return a error code when the wdt clock is out of range - minor format and codingstyle fixes - rebase to [9859465bfe838bc8264d45e1a1bed847bba74bad] Changelog for v2: 1. dtsi: add status disabled for uart0 ~ uart11 remove bootargs from chosen make serial0 alias for uart2 oscillator remove @0 unit-address change uart2 address to kuseg 2. cleanup Kconfig and update defconfig - make these options configurable, disabled by default: CMD_DM DM_ETH DM_GPIO DM_SPI DM_SPI_FLASH DM_RESET PINCONF PINCTRL PINMUX RESET_LSMIPS - make these options configurable, enabled by default: CLK DISPLAY_CPUINFO SYSRESET ROM_EXCEPTION_VECTORS - disabled: CONFIG_ENV_IS_IN_SPI_FLASH 3. fix codingstyle drivers/watchdog/lsmips-wdt.c - priv->base + offset - add comment for default clock value 4. remove address base definition header - remove arch/mips/mach-lsmips/ls1c300/ls1c300.h - clean up files uses this header 5. spl and debug uart - add comment for spl & debug uart pinmuxing - cleanup unused registers base header 6. dtsi - add "loongson,ls1c300-uart" to all uart node 7. board dts - add memory node to board dts, start at 0x8000, size 64MB 8. Kconfig - make ROM_EXCEPTION_VECTORS user configureable - enable ROM_EXCEPTION_VECTORS in defconfig 9. - seperate sdram_init to sdram_init.S - add macro helpers to do sdram, pll lowlevel init 10. dtsi - move clock nodes to /clocks/xxx 11. - define CONFIG_SKIP_LOWLEVEL_INIT to 1 12. - remove option PINCTRL_LS1C300 from Kconfig 13. - dram_init, use get_ram_size() to detect ram size. 14. clk driver - create custom clock ops for PLL - remove debug code 15. - rebase to 59bffec43a657598b194b9eb30dc01eec06078c7 - remove CONFIG_SYS_MONITOR_BASE from include/configs/ > commit e4d741f8abc4a92426d3a826f99390c3abe02d61 > Author: Tom Rini > Date: Thu Mar 24 17:18:05 2022 -0400 > > Convert CONFIG_SYS_MONITOR_BASE to Kconfig MAINTAINERS | 13 ++ arch/mips/Kconfig | 11 ++ arch/mips/Makefile| 1 + arch/mips/dts/Makefile| 1 + arch/mips/dts/loongson32-ls1c300b.dtsi| 141 ++ arch/mips/dts/ls1c300-eval.dts| 31 +++ arch/mips/mach-lsmips/Kconfig | 76 arch/mips/mach-lsmips/Makefile| 6 + arch/mips/mach-lsmips/cpu.c | 19 ++ arch/mips/mach-lsmips/include/mach/serial.h | 16 ++ arch/mips/mach-lsmips/ls1c300/Makefile| 7 + arch/mips/mach-lsmips/ls1c300/gpio.c | 66 +++ arch/mips/mach-lsmips/ls1c300/init.c | 63 ++ arch/mips/mach-lsmips/ls1c300/lowlevel_init.S | 136 + arch/mips/mach-lsmips/ls1c300/sdram.S | 94 + arch/mips/mach-lsmips/ls1c300/serial.c| 109 +++ arch/mips/mach-lsmips/spl.c | 46 + board/loongson/ls1c300-eval/Kconfig | 12 ++ board/loongson/ls1c300-eval/MAINTAINERS | 7 + board/loongson/ls1c300-eval/Makefile | 3 + board/loongson/ls1c300-eval/board.c | 20 ++ configs/ls1c300_defconfig | 49 + drivers/clk/Makefile | 1 + drivers/clk/lsmips/Makefile | 3 +
