Re: [PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
Hi Quentin,
On 2024-04-24 11:11, Quentin Schulz wrote:
> Hi Jonas,
>
> On 4/24/24 00:40, Jonas Karlman wrote:
>> Hi Quentin,
>>
>> On 2024-04-15 16:16, Quentin Schulz wrote:
>>> From: Quentin Schulz
> [...]
>
>>> + if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
>>
>> This check does not seem to work because PTE_BLOCK_NON_SHARE evaluates
>> to 0. Because of this the logic to split the 0-8 GiB bank reported on
>> rk3568 is never split in two.
>>
>
> Oof, that's a bit oversight, thanks for the catch.
>
> Can you test the following please?
>
> """
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 5b1ff1e5495..0492f9b9f41 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -196,7 +196,23 @@ static int rockchip_dram_init_banksize(void)
> const phys_size_t rsrv_size = tmp_mem_map->size;
> const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
>
> - if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
> + /*
> + * DRAM memories are expected by Arm to be marked as
> + * Normal Write-back cacheable, Inner shareable[1], so
> + * let's filter on that to put holes in non-DRAM areas.
> + *
> + * [1]
> https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
> + */
> + const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE;
> + /*
> + * (AttrIndx | SH) in Lower Attributes of Block
> + * Descriptor[2].
> + * [2]
> https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
> + */
> + const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9,
> 8);
> +
> + if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
> tmp_mem_map++;
> continue;
> }
> """
>
> The DRAM mem_map entry for Rockchip devices seems to have those
> attributes and no other non-DRAM entry seems to have
> PTE_BLOCK_MEMTYPE(MT_NORMAL).
>
> We may have an issue in the future if we also want to mark SRAM, ROM or
> flash
> (https://developer.arm.com/documentation/102376/0200/Normal-memory
> because it's likely those would also match the same attributes but we
> would need to put holes for those so that they aren't thought to be
> DRAM, but I guess we can tackle this the day this happens :)
>
> Thanks again for the catch, let me know if this helps and makes sense
> and I'll send a v4 for it.
I think this makes sense and seem to work on at least two of my RK356x
8GB boards using the generic-rk3568 target.
U-Boot:
=> bdinfo
boot_params = 0x
DRAM bank = 0x
-> start= 0x0020
-> size = 0xefe0
DRAM bank = 0x0001
-> start= 0x0001
-> size = 0x0001
flashstart = 0x
flashsize = 0x
flashoffset = 0x
baudrate= 150 bps
relocaddr = 0xeff3a000
reloc off = 0xef53a000
Build = 64-bit
fdt_blob= 0xedf0b390
new_fdt = 0xedf0b390
fdt_size= 0xf980
lmb_dump_all:
memory.cnt = 0x2 / max = 0x10
memory[0] [0x20-0xefff], 0xefe0 bytes flags: 0
memory[1] [0x1-0x1], 0x1 bytes flags: 0
reserved.cnt = 0x2 / max = 0x10
reserved[0][0xecf07000-0xefff], 0x030f9000 bytes flags: 0
reserved[1][0x1-0x1], 0x1 bytes flags: 0
devicetree = separate
serial addr = 0xfe66
width = 0x0004
shift = 0x0002
offset = 0x
clock = 0x016e3600
arch_number = 0x
TLB addr= 0xefff
irq_sp = 0xedf0b0c0
sp start= 0xedf0b0c0
Early malloc usage: 2338 / 1
Linux:
[0.00] Machine model: Generic RK3566/RK3568
[0.00] efi: UEFI not found.
[0.00] NUMA: No NUMA configuration found
[0.00] NUMA: Faking a node at [mem
0x0020-0x0001]
[0.00] NUMA: NODE_DATA [mem 0x1ff0389c0-0x1ff03afff]
[0.00] Zone ranges:
[0.00] DMA [mem 0x0020-0x]
[0.00] DMA32empty
[0.00] Normal [mem 0x0001-0x0001]
[0.00] Movable zone start for each node
[0.00] Early memory node ranges
[0.00] node 0: [mem 0x0020-0xefff]
[0.00]
Re: [PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
Hi Jonas,
On 4/24/24 00:40, Jonas Karlman wrote:
Hi Quentin,
On 2024-04-15 16:16, Quentin Schulz wrote:
From: Quentin Schulz
[...]
+ if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
This check does not seem to work because PTE_BLOCK_NON_SHARE evaluates
to 0. Because of this the logic to split the 0-8 GiB bank reported on
rk3568 is never split in two.
Oof, that's a bit oversight, thanks for the catch.
Can you test the following please?
"""
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 5b1ff1e5495..0492f9b9f41 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -196,7 +196,23 @@ static int rockchip_dram_init_banksize(void)
const phys_size_t rsrv_size = tmp_mem_map->size;
const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
- if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
+ /*
+* DRAM memories are expected by Arm to be marked as
+* Normal Write-back cacheable, Inner shareable[1], so
+* let's filter on that to put holes in non-DRAM areas.
+*
+ * [1]
https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
+*/
+ const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ /*
+* (AttrIndx | SH) in Lower Attributes of Block
+* Descriptor[2].
+ * [2]
https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
+*/
+ const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9,
8);
+
+ if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
tmp_mem_map++;
continue;
}
"""
The DRAM mem_map entry for Rockchip devices seems to have those
attributes and no other non-DRAM entry seems to have
PTE_BLOCK_MEMTYPE(MT_NORMAL).
We may have an issue in the future if we also want to mark SRAM, ROM or
flash
(https://developer.arm.com/documentation/102376/0200/Normal-memory)
because it's likely those would also match the same attributes but we
would need to put holes for those so that they aren't thought to be
DRAM, but I guess we can tackle this the day this happens :)
Thanks again for the catch, let me know if this helps and makes sense
and I'll send a v4 for it.
Cheers,
Quentin
Re: [PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
Hi Quentin,
On 2024-04-15 16:16, Quentin Schulz wrote:
> From: Quentin Schulz
>
> Allow RK3568 and RK3588 based boards to get the RAM bank configuration
> from the ROCKCHIP_TPL stage instead of the current logic. This fixes
> both an issue where 256MB of RAM is blocked for devices with >= 4GB
> of RAM and where memory holes need to be defined for devices with
> more than 16GB of RAM. In the event that neither SoC is used or the
> ROCKCHIP_TPL stage is not used, fall back to existing logic.
>
> The logic handles creating memory holes from reserved memory areas
> defined in mem_map data struct in SoC C files, but only if the DRAM area
> overlaps with one reserved memory area.
>
> Since mem_map data struct is used, it should be rather straightforward
> to add support for other SoCs if needed.
>
> The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
> (e08e32143dd).
>
> Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
> well, but the DDR_MEM tag seems to be pretty much stable (though BL31
> seems to be reserving only 1MB for itself at the moment).
>
> u32 for ATAGS is used because it simplifies the pointer arithmetic and
> it's expected that ATAGS are always below the 4GB limit allowed by u32.
>
> Co-developed-by: Chris Morgan
> Signed-off-by: Chris Morgan
> Signed-off-by: Quentin Schulz
> ---
> arch/arm/mach-rockchip/sdram.c | 240
> +
> 1 file changed, 240 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 0d9a0aef6f5..5b1ff1e5495 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -35,12 +36,251 @@ struct tos_parameter_t {
> s64 reserve[8];
> };
>
> +/* Tag size and offset */
> +#define ATAGS_SIZE SZ_8K
> +#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
> +#define ATAGS_PHYS_BASE (CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
> +#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
> +
> +/* ATAGS memory structures */
> +
> +enum tag_magic {
> + ATAG_NONE,
> + ATAG_CORE = 0x54410001,
> + ATAG_SERIAL = 0x54410050,
> + ATAG_DDR_MEM = 0x54410052,
> + ATAG_MAX = 0x544100ff,
> +};
> +
> +/*
> + * An ATAG contains the following data:
> + * - header
> + *u32 size // sizeof(header + tag data) / sizeof(u32)
> + *u32 magic
> + * - tag data
> + */
> +
> +struct tag_header {
> + u32 size;
> + u32 magic;
> +} __packed;
> +
> +/*
> + * DDR_MEM tag bank is storing data this way:
> + * - address0
> + * - address1
> + * - [...]
> + * - addressX
> + * - size0
> + * - size1
> + * - [...]
> + * - sizeX
> + *
> + * with X being tag_ddr_mem.count - 1.
> + */
> +struct tag_ddr_mem {
> + u32 count;
> + u32 version;
> + u64 bank[20];
> + u32 flags;
> + u32 data[2];
> + u32 hash;
> +} __packed;
> +
> +static u32 js_hash(const void *buf, u32 len)
> +{
> + u32 i, hash = 0x47C6A7E6;
> +
> + if (!buf || !len)
> + return hash;
> +
> + for (i = 0; i < len; i++)
> + hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
> +
> + return hash;
> +}
> +
> +static int rockchip_dram_init_banksize(void)
> +{
> + const struct tag_header *tag_h = NULL;
> + u32 *addr = (void *)ATAGS_PHYS_BASE;
> + struct tag_ddr_mem *ddr_info;
> + u32 calc_hash;
> + u8 i, j;
> +
> + if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
> + !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
> + return -ENOTSUPP;
> +
> + if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
> + return -ENOTSUPP;
> +
> + /* Find DDR_MEM tag */
> + while (addr < (u32 *)ATAGS_PHYS_END) {
> + tag_h = (const struct tag_header *)addr;
> +
> + if (!tag_h->size) {
> + debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
> + return -ENODATA;
> + }
> +
> + if (tag_h->magic == ATAG_DDR_MEM)
> + break;
> +
> + switch (tag_h->magic) {
> + case ATAG_NONE:
> + case ATAG_CORE:
> + case ATAG_SERIAL ... ATAG_MAX:
> + addr += tag_h->size;
> + continue;
> + default:
> + debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
> + tag_h->magic, addr);
> + return -EINVAL;
> + }
> + }
> +
> + if (addr >= (u32 *)ATAGS_PHYS_END ||
> + (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
> + debug("End of ATAGS, no DDR_MEM found\n");
> + return -ENODATA;
> + }
> +
> + /* Data is right after the magic member of the tag_header struct */
> + ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
> + if
Re: [PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
On 2024/4/15 22:16, Quentin Schulz wrote:
From: Quentin Schulz
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
more than 16GB of RAM. In the event that neither SoC is used or the
ROCKCHIP_TPL stage is not used, fall back to existing logic.
The logic handles creating memory holes from reserved memory areas
defined in mem_map data struct in SoC C files, but only if the DRAM area
overlaps with one reserved memory area.
Since mem_map data struct is used, it should be rather straightforward
to add support for other SoCs if needed.
The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
(e08e32143dd).
Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
well, but the DDR_MEM tag seems to be pretty much stable (though BL31
seems to be reserving only 1MB for itself at the moment).
u32 for ATAGS is used because it simplifies the pointer arithmetic and
it's expected that ATAGS are always below the 4GB limit allowed by u32.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/sdram.c | 240 +
1 file changed, 240 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f5..5b1ff1e5495 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -35,12 +36,251 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
+
+/* ATAGS memory structures */
+
+enum tag_magic {
+ ATAG_NONE,
+ ATAG_CORE = 0x54410001,
+ ATAG_SERIAL = 0x54410050,
+ ATAG_DDR_MEM = 0x54410052,
+ ATAG_MAX = 0x544100ff,
+};
+
+/*
+ * An ATAG contains the following data:
+ * - header
+ *u32 size // sizeof(header + tag data) / sizeof(u32)
+ *u32 magic
+ * - tag data
+ */
+
+struct tag_header {
+ u32 size;
+ u32 magic;
+} __packed;
+
+/*
+ * DDR_MEM tag bank is storing data this way:
+ * - address0
+ * - address1
+ * - [...]
+ * - addressX
+ * - size0
+ * - size1
+ * - [...]
+ * - sizeX
+ *
+ * with X being tag_ddr_mem.count - 1.
+ */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+static u32 js_hash(const void *buf, u32 len)
+{
+ u32 i, hash = 0x47C6A7E6;
+
+ if (!buf || !len)
+ return hash;
+
+ for (i = 0; i < len; i++)
+ hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
+
+ return hash;
+}
+
+static int rockchip_dram_init_banksize(void)
+{
+ const struct tag_header *tag_h = NULL;
+ u32 *addr = (void *)ATAGS_PHYS_BASE;
+ struct tag_ddr_mem *ddr_info;
+ u32 calc_hash;
+ u8 i, j;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ return -ENOTSUPP;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return -ENOTSUPP;
+
+ /* Find DDR_MEM tag */
+ while (addr < (u32 *)ATAGS_PHYS_END) {
+ tag_h = (const struct tag_header *)addr;
+
+ if (!tag_h->size) {
+ debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ if (tag_h->magic == ATAG_DDR_MEM)
+ break;
+
+ switch (tag_h->magic) {
+ case ATAG_NONE:
+ case ATAG_CORE:
+ case ATAG_SERIAL ... ATAG_MAX:
+ addr += tag_h->size;
+ continue;
+ default:
+ debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
+ tag_h->magic, addr);
+ return -EINVAL;
+ }
+ }
+
+ if (addr >= (u32 *)ATAGS_PHYS_END ||
+ (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
+ debug("End of ATAGS, no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ /* Data is right after the magic member of the tag_header struct */
+ ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
+ if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
+ debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
+
[PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
From: Quentin Schulz
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
more than 16GB of RAM. In the event that neither SoC is used or the
ROCKCHIP_TPL stage is not used, fall back to existing logic.
The logic handles creating memory holes from reserved memory areas
defined in mem_map data struct in SoC C files, but only if the DRAM area
overlaps with one reserved memory area.
Since mem_map data struct is used, it should be rather straightforward
to add support for other SoCs if needed.
The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
(e08e32143dd).
Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
well, but the DDR_MEM tag seems to be pretty much stable (though BL31
seems to be reserving only 1MB for itself at the moment).
u32 for ATAGS is used because it simplifies the pointer arithmetic and
it's expected that ATAGS are always below the 4GB limit allowed by u32.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/sdram.c | 240 +
1 file changed, 240 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f5..5b1ff1e5495 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -35,12 +36,251 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
+
+/* ATAGS memory structures */
+
+enum tag_magic {
+ ATAG_NONE,
+ ATAG_CORE = 0x54410001,
+ ATAG_SERIAL = 0x54410050,
+ ATAG_DDR_MEM = 0x54410052,
+ ATAG_MAX = 0x544100ff,
+};
+
+/*
+ * An ATAG contains the following data:
+ * - header
+ *u32 size // sizeof(header + tag data) / sizeof(u32)
+ *u32 magic
+ * - tag data
+ */
+
+struct tag_header {
+ u32 size;
+ u32 magic;
+} __packed;
+
+/*
+ * DDR_MEM tag bank is storing data this way:
+ * - address0
+ * - address1
+ * - [...]
+ * - addressX
+ * - size0
+ * - size1
+ * - [...]
+ * - sizeX
+ *
+ * with X being tag_ddr_mem.count - 1.
+ */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+static u32 js_hash(const void *buf, u32 len)
+{
+ u32 i, hash = 0x47C6A7E6;
+
+ if (!buf || !len)
+ return hash;
+
+ for (i = 0; i < len; i++)
+ hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
+
+ return hash;
+}
+
+static int rockchip_dram_init_banksize(void)
+{
+ const struct tag_header *tag_h = NULL;
+ u32 *addr = (void *)ATAGS_PHYS_BASE;
+ struct tag_ddr_mem *ddr_info;
+ u32 calc_hash;
+ u8 i, j;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ return -ENOTSUPP;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return -ENOTSUPP;
+
+ /* Find DDR_MEM tag */
+ while (addr < (u32 *)ATAGS_PHYS_END) {
+ tag_h = (const struct tag_header *)addr;
+
+ if (!tag_h->size) {
+ debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ if (tag_h->magic == ATAG_DDR_MEM)
+ break;
+
+ switch (tag_h->magic) {
+ case ATAG_NONE:
+ case ATAG_CORE:
+ case ATAG_SERIAL ... ATAG_MAX:
+ addr += tag_h->size;
+ continue;
+ default:
+ debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
+ tag_h->magic, addr);
+ return -EINVAL;
+ }
+ }
+
+ if (addr >= (u32 *)ATAGS_PHYS_END ||
+ (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
+ debug("End of ATAGS, no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ /* Data is right after the magic member of the tag_header struct */
+ ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
+ if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
+ debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
+ ddr_info->count, CONFIG_NR_DRAM_BANKS);
+ return -ENOMEM;
+ }
+
+ if
