Re: [PATCH v3 1/2] arm: mediatek: add mt8195 SOC support

2022-11-10 Thread 云春峰 
On Thu, 2022-11-10 at 15:34 +0800, Macpaul Lin wrote:
> From: Fabien Parent 
> 
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
> and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
> hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> and LPDDR4 options.
> 
> Signed-off-by: Fabien Parent 
> Signed-off-by: Macpaul Lin 
> 
> ---
>  MAINTAINERS|   2 +
>  arch/arm/dts/mt8195.dtsi   | 370
> +
>  arch/arm/mach-mediatek/Kconfig |  13 +-
>  arch/arm/mach-mediatek/Makefile|   1 +
>  arch/arm/mach-mediatek/mt8195/Makefile |   3 +
>  arch/arm/mach-mediatek/mt8195/init.c   |  81 ++
>  6 files changed, 469 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/mt8195.dtsi
>  create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
>  create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
> 
> Changes for v2:
>  - Correct node name to t-phy for u3phy0.
>  - Add platform compatible string "mediatek,mt8195-tphy" to all usb
> phy nodes.
>  - remove clock nodes that software cannot controlled in phy nodes.
>  - Test and add back "mac" for HOST only xhci nodes.
> 
> Changes for v3:
>  - Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1cf99c1393..5528dd28c3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -362,8 +362,10 @@ ARM MEDIATEK
>  M:   Ryder Lee 
>  M:   Weijie Gao 
>  M:   Chunfeng Yun 
> +M:   Macpaul Lin 
>  R:   GSS_MTK_Uboot_upstream 
>  S:   Maintained
> +F:   arch/arm/dts/mt8195.dtsi
>  F:   arch/arm/mach-mediatek/
>  F:   arch/arm/include/asm/arch-mediatek/
>  F:   board/mediatek/
> diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
> new file mode 100644
> index 00..33282d21d1
> --- /dev/null
> +++ b/arch/arm/dts/mt8195.dtsi
> @@ -0,0 +1,370 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Ben Ho 
> + * Erin Lo 
> + * Fabien Parent 
> + * Macpaul Lin 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/ {
> + compatible = "mediatek,mt8195";
> + interrupt-parent = <>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <>;
> + };
> + core1 {
> + cpu = <>;
> + };
> + core2 {
> + cpu = <>;
> + };
> + core3 {
> + cpu = <>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <>;
> + };
> + core1 {
> + cpu = <>;
> + };
> + core2 {
> + cpu = <>;
> + };
> + core3 {
> + cpu = <>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x100>;
> +

[PATCH v3 1/2] arm: mediatek: add mt8195 SOC support

2022-11-09 Thread Macpaul Lin 
From: Fabien Parent 

The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.

Signed-off-by: Fabien Parent 
Signed-off-by: Macpaul Lin 

---
 MAINTAINERS|   2 +
 arch/arm/dts/mt8195.dtsi   | 370 +
 arch/arm/mach-mediatek/Kconfig |  13 +-
 arch/arm/mach-mediatek/Makefile|   1 +
 arch/arm/mach-mediatek/mt8195/Makefile |   3 +
 arch/arm/mach-mediatek/mt8195/init.c   |  81 ++
 6 files changed, 469 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/mt8195.dtsi
 create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
 create mode 100644 arch/arm/mach-mediatek/mt8195/init.c

Changes for v2:
 - Correct node name to t-phy for u3phy0.
 - Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
 - remove clock nodes that software cannot controlled in phy nodes.
 - Test and add back "mac" for HOST only xhci nodes.

Changes for v3:
 - Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cf99c1393..5528dd28c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -362,8 +362,10 @@ ARM MEDIATEK
 M: Ryder Lee 
 M: Weijie Gao 
 M: Chunfeng Yun 
+M: Macpaul Lin 
 R: GSS_MTK_Uboot_upstream 
 S: Maintained
+F: arch/arm/dts/mt8195.dtsi
 F: arch/arm/mach-mediatek/
 F: arch/arm/include/asm/arch-mediatek/
 F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 00..33282d21d1
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho 
+ * Erin Lo 
+ * Fabien Parent 
+ * Macpaul Lin 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt8195";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   core2 {
+   cpu = <>;
+   };
+   core3 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   core2 {
+   cpu = <>;
+   };
+   core3 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x000>;
+   enable-method = "psci";
+   capacity-dmips-mhz = <741>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x001>;
+   enable-method = "psci";
+   capacity-dmips-mhz = <741>;
+   };
+
+   cpu2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x002>;
+   enable-method = "psci";
+   capacity-dmips-mhz = <741>;
+   };
+
+   cpu3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x003>;
+   enable-method = "psci";
+   capacity-dmips-mhz = <741>;
+   };
+
+   cpu4: cpu@100 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a73";
+   reg = <0x100>;
+   enable-method = "psci";
+   capacity-dmips-mhz = <1024>;
+   };
+
+   cpu5: cpu@101 {
+   device_type = "cpu";
+