Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi Heiko
Did you solve it after your patch on regulator?
Michael
On Sun, Jun 19, 2022 at 4:54 PM Heiko Thiery wrote:
>
> Hi,
>
> Am So., 19. Juni 2022 um 16:51 Uhr schrieb Michael Nazzareno Trimarchi
> :
> >
> > Hi
> >
> > Il dom 19 giu 2022, 16:47 Heiko Thiery ha scritto:
> >>
> >> Hi,
> >>
> >> Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi
> >> :
> >> >
> >> > Hi Heiko
> >> >
> >> > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery
> >> > wrote:
> >> > >
> >> > > Hi,
> >> > >
> >> > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi
> >> > > :
> >> > > >
> >> > > > Hi
> >> > > >
> >> > > > Il sab 18 giu 2022, 23:56 Heiko Thiery ha
> >> > > > scritto:
> >> > > >>
> >> > > >> Hi Michael, Hi Marek,
> >> > > >>
> >> > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno
> >> > > >> Trimarchi
> >> > > >> :
> >> > > >> >
> >> > > >> > Hi Heiko
> >> > > >> >
> >> > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery
> >> > > >> > wrote:
> >> > > >> > >
> >> > > >> > > Hi Marek,
> >> > > >> > >
> >> > > >> > > [SNIP]
> >> > > >> > >
> >> > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c
> >> > > >> > > > > b/board/freescale/imx8mn_evk/spl.c
> >> > > >> > > > > index 14cb51368f..0d9909a662 100644
> >> > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c
> >> > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c
> >> > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void)
> >> > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
> >> > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode
> >> > > >> > > > > */
> >> > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
> >> > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
> >> > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
> >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
> >> > > >> > > > > +
> >> > > >> > > > > + /* Disable the BUCK2 */
> >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
> >> > > >> > > > > +
> >> > > >> > > > > + /* Set NVCC_DRAM to 1.35v */
> >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
> >> > > >> > > > > #else
> >> > > >> > > >
> >> > > >> > > > All this part is not done by the spl pmic driver?
> >> > > >> > >
> >> > > >> > > I saw that you added the PCA9450 driver. Do you know if this
> >> > > >> > > initialization can be done by the driver when
> >> > > >> > > CONFIG_SPL_DM_REGULATOR
> >> > > >> > > is enabled? If I see this correctly, it can't be done. Is that
> >> > > >> > > correct?
> >> > > >> >
> >> > > >> > + {
> >> > > >> > + u-boot,dm-spl;
> >> > > >> > +};
> >> > > >> > +
> >> > > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
> >> > > >> > + u-boot,dm-spl;
> >> > > >> > +};
> >> > > >> > +
> >> > > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
> >> > > >> > + u-boot,dm-spl;
> >> > > >> > +};
> >> > > >> > +
> >> > > >> > +_i2c1 {
> >> > > >> > + u-boot,dm-spl;
> >> > > >> > +};
> >> > > >> > +
> >> > > >> > +_pmic {
> >> > > >> > + u-boot,dm-spl;
> >> > > >> > +};
> >> > > >> > +
> >> > > >> >
> >> > > >> > Maybe something like this should work. Now question is about
> >> > > >> > should be
> >> > > >> > done in pre-reloc or not
> >> > > >>
> >> > > >> It took me a little while to understand what was meant by this. In
> >> > > >> the
> >> > > >> meantime I could
> >> > > >> change the PMIC/Regulator initialization to DT/DM and can make the
> >> > > >> setting so.
> >> > > >> What is not clear to me yet is at which point this should be done
> >> > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl
> >> > > >> specific board_init_f().
> >> > > >>
> >> > > >> Do any of you have any advice here?
> >> > > >
> >> > > >
> >> > > > After having a discussion with you, i found that maybe i have some
> >> > > > problem and some of the setting should be done before ddr
> >> > > > inizialization. I will take a look on it on afternoon. I know marek
> >> > > > was working on some way to probe driver during binding and we need
> >> > > > even to be sure that this can happen before memory training.
> >> > > >
> >> > >
> >> > > Currently I added it in board_init_f() right before spl_dram_init()
> >> > > [1] and it works. I also tried to put it in power_init_board() [2] but
> >> > > this does not work.
> >> > >
> >> > > [1]
> >> > > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162
> >> > > [2]
> >> > > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62
> >> >
> >> > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl?
> >>
> >> I added on all nodes the u-boot,dm-pre-reloc but this does not help
> >> when trying to do the init in power_init_board().
> >
> >
> > From code I navigate spl_early_init should bind the driver in pre-reloc
>
> What
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi,
Am So., 19. Juni 2022 um 16:51 Uhr schrieb Michael Nazzareno Trimarchi
:
>
> Hi
>
> Il dom 19 giu 2022, 16:47 Heiko Thiery ha scritto:
>>
>> Hi,
>>
>> Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi
>> :
>> >
>> > Hi Heiko
>> >
>> > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery
>> > wrote:
>> > >
>> > > Hi,
>> > >
>> > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi
>> > > :
>> > > >
>> > > > Hi
>> > > >
>> > > > Il sab 18 giu 2022, 23:56 Heiko Thiery ha
>> > > > scritto:
>> > > >>
>> > > >> Hi Michael, Hi Marek,
>> > > >>
>> > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi
>> > > >> :
>> > > >> >
>> > > >> > Hi Heiko
>> > > >> >
>> > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery
>> > > >> > wrote:
>> > > >> > >
>> > > >> > > Hi Marek,
>> > > >> > >
>> > > >> > > [SNIP]
>> > > >> > >
>> > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c
>> > > >> > > > > b/board/freescale/imx8mn_evk/spl.c
>> > > >> > > > > index 14cb51368f..0d9909a662 100644
>> > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c
>> > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c
>> > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void)
>> > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
>> > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
>> > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
>> > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
>> > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
>> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
>> > > >> > > > > +
>> > > >> > > > > + /* Disable the BUCK2 */
>> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
>> > > >> > > > > +
>> > > >> > > > > + /* Set NVCC_DRAM to 1.35v */
>> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
>> > > >> > > > > #else
>> > > >> > > >
>> > > >> > > > All this part is not done by the spl pmic driver?
>> > > >> > >
>> > > >> > > I saw that you added the PCA9450 driver. Do you know if this
>> > > >> > > initialization can be done by the driver when
>> > > >> > > CONFIG_SPL_DM_REGULATOR
>> > > >> > > is enabled? If I see this correctly, it can't be done. Is that
>> > > >> > > correct?
>> > > >> >
>> > > >> > + {
>> > > >> > + u-boot,dm-spl;
>> > > >> > +};
>> > > >> > +
>> > > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
>> > > >> > + u-boot,dm-spl;
>> > > >> > +};
>> > > >> > +
>> > > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
>> > > >> > + u-boot,dm-spl;
>> > > >> > +};
>> > > >> > +
>> > > >> > +_i2c1 {
>> > > >> > + u-boot,dm-spl;
>> > > >> > +};
>> > > >> > +
>> > > >> > +_pmic {
>> > > >> > + u-boot,dm-spl;
>> > > >> > +};
>> > > >> > +
>> > > >> >
>> > > >> > Maybe something like this should work. Now question is about should
>> > > >> > be
>> > > >> > done in pre-reloc or not
>> > > >>
>> > > >> It took me a little while to understand what was meant by this. In the
>> > > >> meantime I could
>> > > >> change the PMIC/Regulator initialization to DT/DM and can make the
>> > > >> setting so.
>> > > >> What is not clear to me yet is at which point this should be done
>> > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl
>> > > >> specific board_init_f().
>> > > >>
>> > > >> Do any of you have any advice here?
>> > > >
>> > > >
>> > > > After having a discussion with you, i found that maybe i have some
>> > > > problem and some of the setting should be done before ddr
>> > > > inizialization. I will take a look on it on afternoon. I know marek
>> > > > was working on some way to probe driver during binding and we need
>> > > > even to be sure that this can happen before memory training.
>> > > >
>> > >
>> > > Currently I added it in board_init_f() right before spl_dram_init()
>> > > [1] and it works. I also tried to put it in power_init_board() [2] but
>> > > this does not work.
>> > >
>> > > [1]
>> > > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162
>> > > [2]
>> > > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62
>> >
>> > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl?
>>
>> I added on all nodes the u-boot,dm-pre-reloc but this does not help
>> when trying to do the init in power_init_board().
>
>
> From code I navigate spl_early_init should bind the driver in pre-reloc
What function should be called to probe the driver? Currently I use
regulators_enable_boot_on().
> Michael
>>
>>
>> >
>> > Michael
>> >
>> > >
>> > > --
>> > > Heiko
>> > >
>> > > > Michael
>> > > >>
>> > > >>
>> > > >> Thanks
>> > > >> --
>> > > >> Heiko
>> > > >>
>> > > >> > Michael
>> > > >> > >
>> > > >> > > --
>> > > >> > > Heiko
>> > > >> >
>> > > >> >
>> > > >> >
>> > > >> > --
>> > > >> > Michael Nazzareno Trimarchi
>> > >
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi
Il dom 19 giu 2022, 16:47 Heiko Thiery ha scritto:
> Hi,
>
> Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi
> :
> >
> > Hi Heiko
> >
> > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery
> wrote:
> > >
> > > Hi,
> > >
> > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi
> > > :
> > > >
> > > > Hi
> > > >
> > > > Il sab 18 giu 2022, 23:56 Heiko Thiery ha
> scritto:
> > > >>
> > > >> Hi Michael, Hi Marek,
> > > >>
> > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno
> Trimarchi
> > > >> :
> > > >> >
> > > >> > Hi Heiko
> > > >> >
> > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <
> heiko.thi...@gmail.com> wrote:
> > > >> > >
> > > >> > > Hi Marek,
> > > >> > >
> > > >> > > [SNIP]
> > > >> > >
> > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c
> b/board/freescale/imx8mn_evk/spl.c
> > > >> > > > > index 14cb51368f..0d9909a662 100644
> > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c
> > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c
> > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void)
> > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
> > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode
> */
> > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
> > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
> > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
> > > >> > > > > +
> > > >> > > > > + /* Disable the BUCK2 */
> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
> > > >> > > > > +
> > > >> > > > > + /* Set NVCC_DRAM to 1.35v */
> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
> > > >> > > > > #else
> > > >> > > >
> > > >> > > > All this part is not done by the spl pmic driver?
> > > >> > >
> > > >> > > I saw that you added the PCA9450 driver. Do you know if this
> > > >> > > initialization can be done by the driver when
> CONFIG_SPL_DM_REGULATOR
> > > >> > > is enabled? If I see this correctly, it can't be done. Is that
> > > >> > > correct?
> > > >> >
> > > >> > + {
> > > >> > + u-boot,dm-spl;
> > > >> > +};
> > > >> > +
> > > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
> > > >> > + u-boot,dm-spl;
> > > >> > +};
> > > >> > +
> > > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
> > > >> > + u-boot,dm-spl;
> > > >> > +};
> > > >> > +
> > > >> > +_i2c1 {
> > > >> > + u-boot,dm-spl;
> > > >> > +};
> > > >> > +
> > > >> > +_pmic {
> > > >> > + u-boot,dm-spl;
> > > >> > +};
> > > >> > +
> > > >> >
> > > >> > Maybe something like this should work. Now question is about
> should be
> > > >> > done in pre-reloc or not
> > > >>
> > > >> It took me a little while to understand what was meant by this. In
> the
> > > >> meantime I could
> > > >> change the PMIC/Regulator initialization to DT/DM and can make the
> setting so.
> > > >> What is not clear to me yet is at which point this should be done
> > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl
> > > >> specific board_init_f().
> > > >>
> > > >> Do any of you have any advice here?
> > > >
> > > >
> > > > After having a discussion with you, i found that maybe i have some
> problem and some of the setting should be done before ddr inizialization. I
> will take a look on it on afternoon. I know marek was working on some way
> to probe driver during binding and we need even to be sure that this can
> happen before memory training.
> > > >
> > >
> > > Currently I added it in board_init_f() right before spl_dram_init()
> > > [1] and it works. I also tried to put it in power_init_board() [2] but
> > > this does not work.
> > >
> > > [1]
> https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162
> > > [2]
> https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62
> >
> > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl?
>
> I added on all nodes the u-boot,dm-pre-reloc but this does not help
> when trying to do the init in power_init_board().
>
>From code I navigate spl_early_init should bind the driver in pre-reloc
Michael
>
> >
> > Michael
> >
> > >
> > > --
> > > Heiko
> > >
> > > > Michael
> > > >>
> > > >>
> > > >> Thanks
> > > >> --
> > > >> Heiko
> > > >>
> > > >> > Michael
> > > >> > >
> > > >> > > --
> > > >> > > Heiko
> > > >> >
> > > >> >
> > > >> >
> > > >> > --
> > > >> > Michael Nazzareno Trimarchi
> > > >> > Co-Founder & Chief Executive Officer
> > > >> > M. +39 347 913 2170
> > > >> > mich...@amarulasolutions.com
> > > >> > __
> > > >> >
> > > >> > Amarula Solutions BV
> > > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> > > >> > T. +31 (0)85 111 9172
> > > >> > i...@amarulasolutions.com
> > > >> > www.amarulasolutions.com
> >
> >
> >
> > --
> > Michael Nazzareno
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi
[snip]
> > > >> > Maybe something like this should work. Now question is about should
> > > >> > be
> > > >> > done in pre-reloc or not
> > > >>
> > > >> It took me a little while to understand what was meant by this. In the
> > > >> meantime I could
> > > >> change the PMIC/Regulator initialization to DT/DM and can make the
> > > >> setting so.
> > > >> What is not clear to me yet is at which point this should be done
> > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl
> > > >> specific board_init_f().
> > > >>
> > > >> Do any of you have any advice here?
> > > >
> > > >
> > > > After having a discussion with you, i found that maybe i have some
> > > > problem and some of the setting should be done before ddr
> > > > inizialization. I will take a look on it on afternoon. I know marek was
> > > > working on some way to probe driver during binding and we need even to
> > > > be sure that this can happen before memory training.
> > > >
> > >
> > > Currently I added it in board_init_f() right before spl_dram_init()
> > > [1] and it works. I also tried to put it in power_init_board() [2] but
> > > this does not work.
> > >
> > > [1]
> > > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162
> > > [2]
> > > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62
> >
> > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl?
>
> I added on all nodes the u-boot,dm-pre-reloc but this does not help
> when trying to do the init in power_init_board().
This is how the dtsi looks like:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "imx8mn-u-boot.dtsi"
#include "imx8mn-ddr4-evk-u-boot.dtsi"
{
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&{/soc@0/bus@3080} {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
BUCK1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
BUCK4 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
BUCK5 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
BUCK6 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
LDO1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
LDO2 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
LDO3 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
LDO4 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
LDO5 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
};
_i2c1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
_pmic {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
{
u-boot,dm-spl;
};
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi,
Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi
:
>
> Hi Heiko
>
> On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery wrote:
> >
> > Hi,
> >
> > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi
> > :
> > >
> > > Hi
> > >
> > > Il sab 18 giu 2022, 23:56 Heiko Thiery ha
> > > scritto:
> > >>
> > >> Hi Michael, Hi Marek,
> > >>
> > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi
> > >> :
> > >> >
> > >> > Hi Heiko
> > >> >
> > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery
> > >> > wrote:
> > >> > >
> > >> > > Hi Marek,
> > >> > >
> > >> > > [SNIP]
> > >> > >
> > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c
> > >> > > > > b/board/freescale/imx8mn_evk/spl.c
> > >> > > > > index 14cb51368f..0d9909a662 100644
> > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c
> > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c
> > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void)
> > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
> > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
> > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
> > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
> > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
> > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
> > >> > > > > +
> > >> > > > > + /* Disable the BUCK2 */
> > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
> > >> > > > > +
> > >> > > > > + /* Set NVCC_DRAM to 1.35v */
> > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
> > >> > > > > #else
> > >> > > >
> > >> > > > All this part is not done by the spl pmic driver?
> > >> > >
> > >> > > I saw that you added the PCA9450 driver. Do you know if this
> > >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR
> > >> > > is enabled? If I see this correctly, it can't be done. Is that
> > >> > > correct?
> > >> >
> > >> > + {
> > >> > + u-boot,dm-spl;
> > >> > +};
> > >> > +
> > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
> > >> > + u-boot,dm-spl;
> > >> > +};
> > >> > +
> > >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
> > >> > + u-boot,dm-spl;
> > >> > +};
> > >> > +
> > >> > +_i2c1 {
> > >> > + u-boot,dm-spl;
> > >> > +};
> > >> > +
> > >> > +_pmic {
> > >> > + u-boot,dm-spl;
> > >> > +};
> > >> > +
> > >> >
> > >> > Maybe something like this should work. Now question is about should be
> > >> > done in pre-reloc or not
> > >>
> > >> It took me a little while to understand what was meant by this. In the
> > >> meantime I could
> > >> change the PMIC/Regulator initialization to DT/DM and can make the
> > >> setting so.
> > >> What is not clear to me yet is at which point this should be done
> > >> (regulators_enable_boot_on()). Currently I do it in the board/spl
> > >> specific board_init_f().
> > >>
> > >> Do any of you have any advice here?
> > >
> > >
> > > After having a discussion with you, i found that maybe i have some
> > > problem and some of the setting should be done before ddr inizialization.
> > > I will take a look on it on afternoon. I know marek was working on some
> > > way to probe driver during binding and we need even to be sure that this
> > > can happen before memory training.
> > >
> >
> > Currently I added it in board_init_f() right before spl_dram_init()
> > [1] and it works. I also tried to put it in power_init_board() [2] but
> > this does not work.
> >
> > [1]
> > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162
> > [2]
> > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62
>
> Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl?
I added on all nodes the u-boot,dm-pre-reloc but this does not help
when trying to do the init in power_init_board().
>
> Michael
>
> >
> > --
> > Heiko
> >
> > > Michael
> > >>
> > >>
> > >> Thanks
> > >> --
> > >> Heiko
> > >>
> > >> > Michael
> > >> > >
> > >> > > --
> > >> > > Heiko
> > >> >
> > >> >
> > >> >
> > >> > --
> > >> > Michael Nazzareno Trimarchi
> > >> > Co-Founder & Chief Executive Officer
> > >> > M. +39 347 913 2170
> > >> > mich...@amarulasolutions.com
> > >> > __
> > >> >
> > >> > Amarula Solutions BV
> > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> > >> > T. +31 (0)85 111 9172
> > >> > i...@amarulasolutions.com
> > >> > www.amarulasolutions.com
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> www.amarulasolutions.com
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi Heiko
On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery wrote:
>
> Hi,
>
> Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi
> :
> >
> > Hi
> >
> > Il sab 18 giu 2022, 23:56 Heiko Thiery ha scritto:
> >>
> >> Hi Michael, Hi Marek,
> >>
> >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi
> >> :
> >> >
> >> > Hi Heiko
> >> >
> >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery
> >> > wrote:
> >> > >
> >> > > Hi Marek,
> >> > >
> >> > > [SNIP]
> >> > >
> >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c
> >> > > > > b/board/freescale/imx8mn_evk/spl.c
> >> > > > > index 14cb51368f..0d9909a662 100644
> >> > > > > --- a/board/freescale/imx8mn_evk/spl.c
> >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c
> >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void)
> >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
> >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
> >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
> >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
> >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
> >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
> >> > > > > +
> >> > > > > + /* Disable the BUCK2 */
> >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
> >> > > > > +
> >> > > > > + /* Set NVCC_DRAM to 1.35v */
> >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
> >> > > > > #else
> >> > > >
> >> > > > All this part is not done by the spl pmic driver?
> >> > >
> >> > > I saw that you added the PCA9450 driver. Do you know if this
> >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR
> >> > > is enabled? If I see this correctly, it can't be done. Is that
> >> > > correct?
> >> >
> >> > + {
> >> > + u-boot,dm-spl;
> >> > +};
> >> > +
> >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
> >> > + u-boot,dm-spl;
> >> > +};
> >> > +
> >> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
> >> > + u-boot,dm-spl;
> >> > +};
> >> > +
> >> > +_i2c1 {
> >> > + u-boot,dm-spl;
> >> > +};
> >> > +
> >> > +_pmic {
> >> > + u-boot,dm-spl;
> >> > +};
> >> > +
> >> >
> >> > Maybe something like this should work. Now question is about should be
> >> > done in pre-reloc or not
> >>
> >> It took me a little while to understand what was meant by this. In the
> >> meantime I could
> >> change the PMIC/Regulator initialization to DT/DM and can make the setting
> >> so.
> >> What is not clear to me yet is at which point this should be done
> >> (regulators_enable_boot_on()). Currently I do it in the board/spl
> >> specific board_init_f().
> >>
> >> Do any of you have any advice here?
> >
> >
> > After having a discussion with you, i found that maybe i have some problem
> > and some of the setting should be done before ddr inizialization. I will
> > take a look on it on afternoon. I know marek was working on some way to
> > probe driver during binding and we need even to be sure that this can
> > happen before memory training.
> >
>
> Currently I added it in board_init_f() right before spl_dram_init()
> [1] and it works. I also tried to put it in power_init_board() [2] but
> this does not work.
>
> [1]
> https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162
> [2]
> https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62
Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl?
Michael
>
> --
> Heiko
>
> > Michael
> >>
> >>
> >> Thanks
> >> --
> >> Heiko
> >>
> >> > Michael
> >> > >
> >> > > --
> >> > > Heiko
> >> >
> >> >
> >> >
> >> > --
> >> > Michael Nazzareno Trimarchi
> >> > Co-Founder & Chief Executive Officer
> >> > M. +39 347 913 2170
> >> > mich...@amarulasolutions.com
> >> > __
> >> >
> >> > Amarula Solutions BV
> >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> >> > T. +31 (0)85 111 9172
> >> > i...@amarulasolutions.com
> >> > www.amarulasolutions.com
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi,
Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi
:
>
> Hi
>
> Il sab 18 giu 2022, 23:56 Heiko Thiery ha scritto:
>>
>> Hi Michael, Hi Marek,
>>
>> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi
>> :
>> >
>> > Hi Heiko
>> >
>> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery
>> > wrote:
>> > >
>> > > Hi Marek,
>> > >
>> > > [SNIP]
>> > >
>> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c
>> > > > > b/board/freescale/imx8mn_evk/spl.c
>> > > > > index 14cb51368f..0d9909a662 100644
>> > > > > --- a/board/freescale/imx8mn_evk/spl.c
>> > > > > +++ b/board/freescale/imx8mn_evk/spl.c
>> > > > > @@ -83,6 +83,15 @@ int power_init_board(void)
>> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
>> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
>> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
>> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
>> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
>> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
>> > > > > +
>> > > > > + /* Disable the BUCK2 */
>> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
>> > > > > +
>> > > > > + /* Set NVCC_DRAM to 1.35v */
>> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
>> > > > > #else
>> > > >
>> > > > All this part is not done by the spl pmic driver?
>> > >
>> > > I saw that you added the PCA9450 driver. Do you know if this
>> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR
>> > > is enabled? If I see this correctly, it can't be done. Is that
>> > > correct?
>> >
>> > + {
>> > + u-boot,dm-spl;
>> > +};
>> > +
>> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
>> > + u-boot,dm-spl;
>> > +};
>> > +
>> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
>> > + u-boot,dm-spl;
>> > +};
>> > +
>> > +_i2c1 {
>> > + u-boot,dm-spl;
>> > +};
>> > +
>> > +_pmic {
>> > + u-boot,dm-spl;
>> > +};
>> > +
>> >
>> > Maybe something like this should work. Now question is about should be
>> > done in pre-reloc or not
>>
>> It took me a little while to understand what was meant by this. In the
>> meantime I could
>> change the PMIC/Regulator initialization to DT/DM and can make the setting
>> so.
>> What is not clear to me yet is at which point this should be done
>> (regulators_enable_boot_on()). Currently I do it in the board/spl
>> specific board_init_f().
>>
>> Do any of you have any advice here?
>
>
> After having a discussion with you, i found that maybe i have some problem
> and some of the setting should be done before ddr inizialization. I will take
> a look on it on afternoon. I know marek was working on some way to probe
> driver during binding and we need even to be sure that this can happen before
> memory training.
>
Currently I added it in board_init_f() right before spl_dram_init()
[1] and it works. I also tried to put it in power_init_board() [2] but
this does not work.
[1]
https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162
[2]
https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62
--
Heiko
> Michael
>>
>>
>> Thanks
>> --
>> Heiko
>>
>> > Michael
>> > >
>> > > --
>> > > Heiko
>> >
>> >
>> >
>> > --
>> > Michael Nazzareno Trimarchi
>> > Co-Founder & Chief Executive Officer
>> > M. +39 347 913 2170
>> > mich...@amarulasolutions.com
>> > __
>> >
>> > Amarula Solutions BV
>> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
>> > T. +31 (0)85 111 9172
>> > i...@amarulasolutions.com
>> > www.amarulasolutions.com
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi
Il sab 18 giu 2022, 23:56 Heiko Thiery ha scritto:
> Hi Michael, Hi Marek,
>
> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi
> :
> >
> > Hi Heiko
> >
> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery
> wrote:
> > >
> > > Hi Marek,
> > >
> > > [SNIP]
> > >
> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c
> b/board/freescale/imx8mn_evk/spl.c
> > > > > index 14cb51368f..0d9909a662 100644
> > > > > --- a/board/freescale/imx8mn_evk/spl.c
> > > > > +++ b/board/freescale/imx8mn_evk/spl.c
> > > > > @@ -83,6 +83,15 @@ int power_init_board(void)
> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
> > > > > +
> > > > > + /* Disable the BUCK2 */
> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
> > > > > +
> > > > > + /* Set NVCC_DRAM to 1.35v */
> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
> > > > > #else
> > > >
> > > > All this part is not done by the spl pmic driver?
> > >
> > > I saw that you added the PCA9450 driver. Do you know if this
> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR
> > > is enabled? If I see this correctly, it can't be done. Is that
> > > correct?
> >
> > + {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
> > + u-boot,dm-spl;
> > +};
> > +
> > +_i2c1 {
> > + u-boot,dm-spl;
> > +};
> > +
> > +_pmic {
> > + u-boot,dm-spl;
> > +};
> > +
> >
> > Maybe something like this should work. Now question is about should be
> > done in pre-reloc or not
>
> It took me a little while to understand what was meant by this. In the
> meantime I could
> change the PMIC/Regulator initialization to DT/DM and can make the setting
> so.
> What is not clear to me yet is at which point this should be done
> (regulators_enable_boot_on()). Currently I do it in the board/spl
> specific board_init_f().
>
> Do any of you have any advice here?
>
After having a discussion with you, i found that maybe i have some problem
and some of the setting should be done before ddr inizialization. I will
take a look on it on afternoon. I know marek was working on some way to
probe driver during binding and we need even to be sure that this can
happen before memory training.
Michael
>
> Thanks
> --
> Heiko
>
> > Michael
> > >
> > > --
> > > Heiko
> >
> >
> >
> > --
> > Michael Nazzareno Trimarchi
> > Co-Founder & Chief Executive Officer
> > M. +39 347 913 2170
> > mich...@amarulasolutions.com
> > __
> >
> > Amarula Solutions BV
> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> > T. +31 (0)85 111 9172
> > i...@amarulasolutions.com
> > www.amarulasolutions.com
>
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi Michael, Hi Marek,
Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi
:
>
> Hi Heiko
>
> On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery wrote:
> >
> > Hi Marek,
> >
> > [SNIP]
> >
> > > > diff --git a/board/freescale/imx8mn_evk/spl.c
> > > > b/board/freescale/imx8mn_evk/spl.c
> > > > index 14cb51368f..0d9909a662 100644
> > > > --- a/board/freescale/imx8mn_evk/spl.c
> > > > +++ b/board/freescale/imx8mn_evk/spl.c
> > > > @@ -83,6 +83,15 @@ int power_init_board(void)
> > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
> > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
> > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
> > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
> > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
> > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
> > > > +
> > > > + /* Disable the BUCK2 */
> > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
> > > > +
> > > > + /* Set NVCC_DRAM to 1.35v */
> > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
> > > > #else
> > >
> > > All this part is not done by the spl pmic driver?
> >
> > I saw that you added the PCA9450 driver. Do you know if this
> > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR
> > is enabled? If I see this correctly, it can't be done. Is that
> > correct?
>
> + {
> + u-boot,dm-spl;
> +};
> +
> +&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
> + u-boot,dm-spl;
> +};
> +
> +&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
> + u-boot,dm-spl;
> +};
> +
> +_i2c1 {
> + u-boot,dm-spl;
> +};
> +
> +_pmic {
> + u-boot,dm-spl;
> +};
> +
>
> Maybe something like this should work. Now question is about should be
> done in pre-reloc or not
It took me a little while to understand what was meant by this. In the
meantime I could
change the PMIC/Regulator initialization to DT/DM and can make the setting so.
What is not clear to me yet is at which point this should be done
(regulators_enable_boot_on()). Currently I do it in the board/spl
specific board_init_f().
Do any of you have any advice here?
Thanks
--
Heiko
> Michael
> >
> > --
> > Heiko
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> www.amarulasolutions.com
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi Heiko
On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery wrote:
>
> Hi Marek,
>
> [SNIP]
>
> > > diff --git a/board/freescale/imx8mn_evk/spl.c
> > > b/board/freescale/imx8mn_evk/spl.c
> > > index 14cb51368f..0d9909a662 100644
> > > --- a/board/freescale/imx8mn_evk/spl.c
> > > +++ b/board/freescale/imx8mn_evk/spl.c
> > > @@ -83,6 +83,15 @@ int power_init_board(void)
> > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
> > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
> > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
> > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK)
> > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
> > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
> > > +
> > > + /* Disable the BUCK2 */
> > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
> > > +
> > > + /* Set NVCC_DRAM to 1.35v */
> > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
> > > #else
> >
> > All this part is not done by the spl pmic driver?
>
> I saw that you added the PCA9450 driver. Do you know if this
> initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR
> is enabled? If I see this correctly, it can't be done. Is that
> correct?
+ {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
Maybe something like this should work. Now question is about should be
done in pre-reloc or not
Michael
>
> --
> Heiko
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi Marek, [SNIP] > > diff --git a/board/freescale/imx8mn_evk/spl.c > > b/board/freescale/imx8mn_evk/spl.c > > index 14cb51368f..0d9909a662 100644 > > --- a/board/freescale/imx8mn_evk/spl.c > > +++ b/board/freescale/imx8mn_evk/spl.c > > @@ -83,6 +83,15 @@ int power_init_board(void) > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > + > > + /* Disable the BUCK2 */ > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > + > > + /* Set NVCC_DRAM to 1.35v */ > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > #else > > All this part is not done by the spl pmic driver? I saw that you added the PCA9450 driver. Do you know if this initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR is enabled? If I see this correctly, it can't be done. Is that correct? -- Heiko
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi Michael,
Am Di., 14. Juni 2022 um 08:56 Uhr schrieb Michael Nazzareno Trimarchi
:
>
> Hi
>
> On Mon, Jun 13, 2022 at 11:10 PM Heiko Thiery wrote:
> >
> > Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano
> > UltraLite Quad SoC and uses 1GB DDR3L memory.
> >
> > U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
> > Normal Boot
> > WDT: Started watchdog@3028 with servicing (60s timeout)
> > Trying to boot from BOOTROM
> > image offset 0x8000, pagesize 0x200, ivt offset 0x0
> > NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832
> > NOTICE: BL31: Built : 14:03:53, May 10 2022
> >
> > U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
> >
> > CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz
> > Reset cause: WDOG
> > Model: NXP i.MX8MNano DDR3L EVK board
> > DRAM: 1 GiB
> > Core: 142 devices, 19 uclasses, devicetree: separate
> > WDT: Started watchdog@3028 with servicing (60s timeout)
> > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > Loading Environment from MMC... OK
> > In:serial@3089
> > Out: serial@3089
> > Err: serial@3089
> > Net: eth0: ethernet@30be
> > Hit any key to stop autoboot: 0
> >
> > Signed-off-by: Heiko Thiery
> > Reviewed-by: Fabio Estevam
> > ---
> > v4:
> > - rebase on current master to fix merge conflicts
> > - remove config options from defconfig
> > - enable SPL_DM_SERIAL
> > - include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi
> > v3:
> > - fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK)
> > v2:
> > - change license formatting (thanks Marcel)
> >
> > arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 +
> > arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++
> > arch/arm/dts/imx8mn-u-boot.dtsi | 12 +
> > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > board/freescale/imx8mn_evk/Kconfig| 2 +-
> > board/freescale/imx8mn_evk/Makefile | 1 +
> > board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++
> > board/freescale/imx8mn_evk/spl.c | 9 +
> > configs/imx8mn_ddr3l_evk_defconfig| 95 +++
> > include/configs/imx8mn_evk.h | 4 +
> > 10 files changed, 1220 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts
> > create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c
> > create mode 100644 configs/imx8mn_ddr3l_evk_defconfig
> >
> > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > new file mode 100644
> > index 00..b9192515e5
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > @@ -0,0 +1,34 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +
> > +#include "imx8mn-u-boot.dtsi"
> > +#include "imx8mn-ddr4-evk-u-boot.dtsi"
> > +
> > +
> > +&{/soc@0} {
> > + u-boot,dm-pre-reloc;
> > + u-boot,dm-spl;
> > +};
> > +
> > + {
> > + u-boot,dm-spl;
> > + u-boot,dm-pre-reloc;
> > + /delete-property/ assigned-clocks;
> > + /delete-property/ assigned-clock-parents;
> > + /delete-property/ assigned-clock-rates;
> > +};
> > +
> > + {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
> > + u-boot,dm-spl;
> > +};
> > +
> > + {
> > + u-boot,dm-spl;
> > +};
> > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts
> > b/arch/arm/dts/imx8mn-ddr3l-evk.dts
> > new file mode 100644
> > index 00..4cdc03c8f2
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
> > @@ -0,0 +1,114 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +
> > +/dts-v1/;
> > +
> > +#include "imx8mn.dtsi"
> > +#include "imx8mn-evk.dtsi"
> > +#include
> > +
> > +/ {
> > + model = "NXP i.MX8MNano DDR3L EVK board";
> > + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
> > +};
> > +
> > +_0 {
> > + cpu-supply = <>;
> > +};
> > +
> > +_1 {
> > + cpu-supply = <>;
> > +};
> > +
> > +_2 {
> > + cpu-supply = <>;
> > +};
> > +
> > +_3 {
> > + cpu-supply = <>;
> > +};
> > +
> > + {
> > + pmic: pmic@25 {
> > + compatible = "nxp,pca9450b";
> > + reg = <0x25>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_pmic>;
> > + interrupt-parent = <>;
> > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > +
> > + regulators {
> > + buck1: BUCK1 {
> > + regulator-name = "VDD_SOC_0V9";
> > + regulator-min-microvolt = <85>;
> > + regulator-max-microvolt = <95>;
> > + regulator-boot-on;
> > +
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
Hi
On Mon, Jun 13, 2022 at 11:10 PM Heiko Thiery wrote:
>
> Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano
> UltraLite Quad SoC and uses 1GB DDR3L memory.
>
> U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
> Normal Boot
> WDT: Started watchdog@3028 with servicing (60s timeout)
> Trying to boot from BOOTROM
> image offset 0x8000, pagesize 0x200, ivt offset 0x0
> NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832
> NOTICE: BL31: Built : 14:03:53, May 10 2022
>
> U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
>
> CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz
> Reset cause: WDOG
> Model: NXP i.MX8MNano DDR3L EVK board
> DRAM: 1 GiB
> Core: 142 devices, 19 uclasses, devicetree: separate
> WDT: Started watchdog@3028 with servicing (60s timeout)
> MMC: FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... OK
> In:serial@3089
> Out: serial@3089
> Err: serial@3089
> Net: eth0: ethernet@30be
> Hit any key to stop autoboot: 0
>
> Signed-off-by: Heiko Thiery
> Reviewed-by: Fabio Estevam
> ---
> v4:
> - rebase on current master to fix merge conflicts
> - remove config options from defconfig
> - enable SPL_DM_SERIAL
> - include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi
> v3:
> - fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK)
> v2:
> - change license formatting (thanks Marcel)
>
> arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 +
> arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++
> arch/arm/dts/imx8mn-u-boot.dtsi | 12 +
> arch/arm/mach-imx/imx8m/Kconfig | 7 +
> board/freescale/imx8mn_evk/Kconfig| 2 +-
> board/freescale/imx8mn_evk/Makefile | 1 +
> board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++
> board/freescale/imx8mn_evk/spl.c | 9 +
> configs/imx8mn_ddr3l_evk_defconfig| 95 +++
> include/configs/imx8mn_evk.h | 4 +
> 10 files changed, 1220 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts
> create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c
> create mode 100644 configs/imx8mn_ddr3l_evk_defconfig
>
> diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> new file mode 100644
> index 00..b9192515e5
> --- /dev/null
> +++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +
> +#include "imx8mn-u-boot.dtsi"
> +#include "imx8mn-ddr4-evk-u-boot.dtsi"
> +
> +
> +&{/soc@0} {
> + u-boot,dm-pre-reloc;
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> + /delete-property/ assigned-clocks;
> + /delete-property/ assigned-clock-parents;
> + /delete-property/ assigned-clock-rates;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> +&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
> + u-boot,dm-spl;
> +};
> +
> +&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts
> b/arch/arm/dts/imx8mn-ddr3l-evk.dts
> new file mode 100644
> index 00..4cdc03c8f2
> --- /dev/null
> +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +
> +/dts-v1/;
> +
> +#include "imx8mn.dtsi"
> +#include "imx8mn-evk.dtsi"
> +#include
> +
> +/ {
> + model = "NXP i.MX8MNano DDR3L EVK board";
> + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
> +};
> +
> +_0 {
> + cpu-supply = <>;
> +};
> +
> +_1 {
> + cpu-supply = <>;
> +};
> +
> +_2 {
> + cpu-supply = <>;
> +};
> +
> +_3 {
> + cpu-supply = <>;
> +};
> +
> + {
> + pmic: pmic@25 {
> + compatible = "nxp,pca9450b";
> + reg = <0x25>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_pmic>;
> + interrupt-parent = <>;
> + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> +
> + regulators {
> + buck1: BUCK1 {
> + regulator-name = "VDD_SOC_0V9";
> + regulator-min-microvolt = <85>;
> + regulator-max-microvolt = <95>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <3125>;
> + };
> +
> + buck4: BUCK4 {
> + regulator-name = "VDD_3V3";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> +
Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support
在 2022/6/14 5:10, Heiko Thiery 写道:
Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano
UltraLite Quad SoC and uses 1GB DDR3L memory.
U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
Normal Boot
WDT: Started watchdog@3028 with servicing (60s timeout)
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832
NOTICE: BL31: Built : 14:03:53, May 10 2022
U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz
Reset cause: WDOG
Model: NXP i.MX8MNano DDR3L EVK board
DRAM: 1 GiB
Core: 142 devices, 19 uclasses, devicetree: separate
WDT: Started watchdog@3028 with servicing (60s timeout)
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:serial@3089
Out: serial@3089
Err: serial@3089
Net: eth0: ethernet@30be
Hit any key to stop autoboot: 0
Signed-off-by: Heiko Thiery
Reviewed-by: Fabio Estevam
Reviewed-by: Peng Fan
---
v4:
- rebase on current master to fix merge conflicts
- remove config options from defconfig
- enable SPL_DM_SERIAL
- include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi
v3:
- fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK)
v2:
- change license formatting (thanks Marcel)
arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 +
arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++
arch/arm/dts/imx8mn-u-boot.dtsi | 12 +
arch/arm/mach-imx/imx8m/Kconfig | 7 +
board/freescale/imx8mn_evk/Kconfig| 2 +-
board/freescale/imx8mn_evk/Makefile | 1 +
board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++
board/freescale/imx8mn_evk/spl.c | 9 +
configs/imx8mn_ddr3l_evk_defconfig| 95 +++
include/configs/imx8mn_evk.h | 4 +
10 files changed, 1220 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts
create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c
create mode 100644 configs/imx8mn_ddr3l_evk_defconfig
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
new file mode 100644
index 00..b9192515e5
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "imx8mn-u-boot.dtsi"
+#include "imx8mn-ddr4-evk-u-boot.dtsi"
+
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts
b/arch/arm/dts/imx8mn-ddr3l-evk.dts
new file mode 100644
index 00..4cdc03c8f2
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+#include "imx8mn-evk.dtsi"
+#include
+
+/ {
+ model = "NXP i.MX8MNano DDR3L EVK board";
+ compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
+};
+
+_0 {
+ cpu-supply = <>;
+};
+
+_1 {
+ cpu-supply = <>;
+};
+
+_2 {
+ cpu-supply = <>;
+};
+
+_3 {
+ cpu-supply = <>;
+};
+
+ {
+ pmic: pmic@25 {
+ compatible = "nxp,pca9450b";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmic>;
+ interrupt-parent = <>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "VDD_SOC_0V9";
+ regulator-min-microvolt = <85>;
+ regulator-max-microvolt = <95>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <180>;
+
[PATCH v4] imx: add i.MX8MN DDR3L evk board support
Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano
UltraLite Quad SoC and uses 1GB DDR3L memory.
U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
Normal Boot
WDT: Started watchdog@3028 with servicing (60s timeout)
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832
NOTICE: BL31: Built : 14:03:53, May 10 2022
U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200)
CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz
Reset cause: WDOG
Model: NXP i.MX8MNano DDR3L EVK board
DRAM: 1 GiB
Core: 142 devices, 19 uclasses, devicetree: separate
WDT: Started watchdog@3028 with servicing (60s timeout)
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:serial@3089
Out: serial@3089
Err: serial@3089
Net: eth0: ethernet@30be
Hit any key to stop autoboot: 0
Signed-off-by: Heiko Thiery
Reviewed-by: Fabio Estevam
---
v4:
- rebase on current master to fix merge conflicts
- remove config options from defconfig
- enable SPL_DM_SERIAL
- include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi
v3:
- fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK)
v2:
- change license formatting (thanks Marcel)
arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 +
arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++
arch/arm/dts/imx8mn-u-boot.dtsi | 12 +
arch/arm/mach-imx/imx8m/Kconfig | 7 +
board/freescale/imx8mn_evk/Kconfig| 2 +-
board/freescale/imx8mn_evk/Makefile | 1 +
board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++
board/freescale/imx8mn_evk/spl.c | 9 +
configs/imx8mn_ddr3l_evk_defconfig| 95 +++
include/configs/imx8mn_evk.h | 4 +
10 files changed, 1220 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts
create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c
create mode 100644 configs/imx8mn_ddr3l_evk_defconfig
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
new file mode 100644
index 00..b9192515e5
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "imx8mn-u-boot.dtsi"
+#include "imx8mn-ddr4-evk-u-boot.dtsi"
+
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts
b/arch/arm/dts/imx8mn-ddr3l-evk.dts
new file mode 100644
index 00..4cdc03c8f2
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+#include "imx8mn-evk.dtsi"
+#include
+
+/ {
+ model = "NXP i.MX8MNano DDR3L EVK board";
+ compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
+};
+
+_0 {
+ cpu-supply = <>;
+};
+
+_1 {
+ cpu-supply = <>;
+};
+
+_2 {
+ cpu-supply = <>;
+};
+
+_3 {
+ cpu-supply = <>;
+};
+
+ {
+ pmic: pmic@25 {
+ compatible = "nxp,pca9450b";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmic>;
+ interrupt-parent = <>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "VDD_SOC_0V9";
+ regulator-min-microvolt = <85>;
+ regulator-max-microvolt = <95>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+
