subject:"\[PATCH v4 1\/1\] arch\: arm\: Agilex5 enablement"

RE: [PATCH v4 1/1] arch: arm: Agilex5 enablement

2024-03-12 Thread Chee, Tien Fong

Hi,

> -Original Message-
> From: Lim, Jit Loon 
> Sent: Tuesday, March 12, 2024 10:01 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun ; Bin
> Meng 
> Subject: [PATCH v4 1/1] arch: arm: Agilex5 enablement
> 
> This patch is to enable Agilex5 platform for Intel
> product. Changes, modification and new files are
> created for board, dts, configs and makefile to
> create the base for Agilex5.
> 
> Signed-off-by: Jit Loon Lim 
> 
> ---
> Changes v3 -> v4:
> - Update defined to is_enabled
> Changes v2 -> v3:
> - Added FPGA 240G DDR region
> Changes v1 -> v2:
> - fixed git auto merge issue
> ---
>  arch/arm/Kconfig  |   4 +-
>  arch/arm/dts/Makefile |   1 +
>  arch/arm/dts/socfpga_agilex5-u-boot.dtsi  |  71 ++
>  arch/arm/dts/socfpga_agilex5.dtsi | 575 ++
>  .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 133 
>  arch/arm/dts/socfpga_agilex5_socdk.dts| 163 
>  arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi|  38 +-
>  arch/arm/mach-socfpga/Kconfig |  19 +-
>  arch/arm/mach-socfpga/Makefile|  14 +-
>  arch/arm/mach-socfpga/board.c |  56 +-
>  arch/arm/mach-socfpga/clock_manager_agilex5.c |  89 +++
>  .../include/mach/base_addr_soc64.h|  38 +-
>  .../mach-socfpga/include/mach/clock_manager.h |   4 +-
>  .../include/mach/clock_manager_agilex5.h  |  12 +
>  .../mach-socfpga/include/mach/handoff_soc64.h |  31 +-
>  .../mach-socfpga/include/mach/mailbox_s10.h   |   1 +
>  arch/arm/mach-socfpga/mmu-arm64_s10.c |  59 +-
>  board/intel/agilex5-socdk/MAINTAINERS |   8 +
>  configs/socfpga_agilex5_defconfig | 116 +++
>  drivers/clk/altera/Makefile   |   1 +
>  drivers/clk/altera/clk-agilex5.c  | 743 ++
>  drivers/clk/altera/clk-agilex5.h  | 284 +++
>  include/configs/socfpga_agilex5_socdk.h   |  12 +
>  include/configs/socfpga_soc64_common.h| 143 +++-
>  include/dt-bindings/clock/agilex5-clock.h |  71 ++
>  include/dt-bindings/reset/altr,rst-mgr-agx5.h |  80 ++
>  26 files changed, 2730 insertions(+), 36 deletions(-)
>  create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi
>  create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c
>  create mode 100644 arch/arm/mach-
> socfpga/include/mach/clock_manager_agilex5.h
>  create mode 100644 board/intel/agilex5-socdk/MAINTAINERS
>  create mode 100644 configs/socfpga_agilex5_defconfig
>  create mode 100644 drivers/clk/altera/clk-agilex5.c
>  create mode 100644 drivers/clk/altera/clk-agilex5.h
>  create mode 100644 include/configs/socfpga_agilex5_socdk.h
>  create mode 100644 include/dt-bindings/clock/agilex5-clock.h
>  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index fde85dc0d5..6df805f44c 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -28,6 +28,7 @@ config COUNTER_FREQUENCY
>   ROCKCHIP_RK3288 || ROCKCHIP_RK322X ||
> ROCKCHIP_RK3036
>   default 2500 if ARCH_LX2160A || ARCH_LX2162A ||
> ARCH_LS1088A
>   default 1 if ARCH_ZYNQMP
> + default 2 if ARCH_SOCFPGA && ARM64 &&
> TARGET_SOCFPGA_AGILEX5
>   default 0
>   help
> For platforms with ARMv8-A and ARMv7-A which features a system
> @@ -1124,7 +1125,8 @@ config ARCH_SOCFPGA
>   select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 ||
> TARGET_SOCFPGA_ARRIA10
>   select SYSRESET
>   select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 ||
> TARGET_SOCFPGA_ARRIA10
> - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
> + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5
> && \
> +   TARGET_SOCFPGA_SOC64
>   imply CMD_DM
>   imply CMD_MTDPARTS
>   imply CRC32_VERIFY
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index d9725030d5..2b4f896ad2 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -548,6 +548,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) +=
> thunderx-88xx.dtb
> 
>  dtb-$(CONFIG_ARCH_SOCFPGA) +=\
>   socfpga_agilex_socdk.dtb

[PATCH v4 1/1] arch: arm: Agilex5 enablement

2024-03-12 Thread Jit Loon Lim

This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.

Signed-off-by: Jit Loon Lim 

---
Changes v3 -> v4:
- Update defined to is_enabled
Changes v2 -> v3:
- Added FPGA 240G DDR region
Changes v1 -> v2:
- fixed git auto merge issue
---
 arch/arm/Kconfig  |   4 +-
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi  |  71 ++
 arch/arm/dts/socfpga_agilex5.dtsi | 575 ++
 .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 133 
 arch/arm/dts/socfpga_agilex5_socdk.dts| 163 
 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi|  38 +-
 arch/arm/mach-socfpga/Kconfig |  19 +-
 arch/arm/mach-socfpga/Makefile|  14 +-
 arch/arm/mach-socfpga/board.c |  56 +-
 arch/arm/mach-socfpga/clock_manager_agilex5.c |  89 +++
 .../include/mach/base_addr_soc64.h|  38 +-
 .../mach-socfpga/include/mach/clock_manager.h |   4 +-
 .../include/mach/clock_manager_agilex5.h  |  12 +
 .../mach-socfpga/include/mach/handoff_soc64.h |  31 +-
 .../mach-socfpga/include/mach/mailbox_s10.h   |   1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c |  59 +-
 board/intel/agilex5-socdk/MAINTAINERS |   8 +
 configs/socfpga_agilex5_defconfig | 116 +++
 drivers/clk/altera/Makefile   |   1 +
 drivers/clk/altera/clk-agilex5.c  | 743 ++
 drivers/clk/altera/clk-agilex5.h  | 284 +++
 include/configs/socfpga_agilex5_socdk.h   |  12 +
 include/configs/socfpga_soc64_common.h| 143 +++-
 include/dt-bindings/clock/agilex5-clock.h |  71 ++
 include/dt-bindings/reset/altr,rst-mgr-agx5.h |  80 ++
 26 files changed, 2730 insertions(+), 36 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
 create mode 100644 board/intel/agilex5-socdk/MAINTAINERS
 create mode 100644 configs/socfpga_agilex5_defconfig
 create mode 100644 drivers/clk/altera/clk-agilex5.c
 create mode 100644 drivers/clk/altera/clk-agilex5.h
 create mode 100644 include/configs/socfpga_agilex5_socdk.h
 create mode 100644 include/dt-bindings/clock/agilex5-clock.h
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fde85dc0d5..6df805f44c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -28,6 +28,7 @@ config COUNTER_FREQUENCY
ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
default 2500 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
default 1 if ARCH_ZYNQMP
+   default 2 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
default 0
help
  For platforms with ARMv8-A and ARMv7-A which features a system
@@ -1124,7 +1125,8 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
-   select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
+   select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
+ TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d9725030d5..2b4f896ad2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -548,6 +548,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
socfpga_agilex_socdk.dtb\
+   socfpga_agilex5_socdk.dtb   \
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
socfpga_arria10_chameleonv3_270_2.dtb   \
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi 
b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
new file mode 100644
index 00..a8167e5c14
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2024 Intel Corporation 
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+   memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   bootph-all;
+   };
+};
+
+ {
+   bootph-all;
+};
+
+ {
+   reset-names = "i2c";
+};
+
+ {
+   reset-names = "i2c";
+};
+
+ {
+   reset-names = "i2c";
+};
+
+ {
+   reset-names = "i2c";
+};
+

RE: [PATCH v4 1/1] arch: arm: Agilex5 enablement

[PATCH v4 1/1] arch: arm: Agilex5 enablement

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