This patch add clock driver for MediaTek MT7622 SoC.
Signed-off-by: Ryder Lee
Signed-off-by: Sam Shih
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7622.c | 678 +
include/dt-bindings/clock/mt7622-clk.h | 271 ++
3 files changed, 950 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7622.c
create mode 100644 include/dt-bindings/clock/mt7622-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e92bcd4efe..755e24c651 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
+obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers/clk/mediatek/clk-mt7622.c
new file mode 100644
index 00..a5b61a190b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -0,0 +1,678 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7622 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7622_CLKSQ_STB_CON0 0x20
+#define MT7622_PLL_ISO_CON00x2c
+#define MT7622_PLL_FMAX(2500UL * MHZ)
+#define MT7622_CON0_RST_BARBIT(24)
+
+#define MCU_AXI_DIV0x640
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX0x7c0
+#define MCU_BUS_MSKGENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7622_CON0_RST_BAR,\
+ .fmax = MT7622_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
+ 31, 0x324, 1, 0x328, 0),
+ PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
+ 31, 0x334, 1, 0x338, 0),
+ PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
+ 21, 0x344, 1, 0x348, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 3125),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 3125),
+ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 12500),
+ FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 12500),
+ FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 25000),
+ FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 25000),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, ),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 5000),
+ FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 5000),
+ FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 5000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR0(CLK_TOP_TO_USB3_SYS,
