[U-Boot] [PATCH][Boards Need to Switch DM] spi: davinci: Full dm conversion

[Jagan Teki]

davinci_spi now support dt along with platform data,
respective boards need to switch into dm for the same.

Signed-off-by: Jagan Teki 
---
 drivers/spi/Kconfig|  12 +-
 drivers/spi/davinci_spi.c  | 275 +
 include/dm/platform_data/spi_davinci.h |  15 ++
 3 files changed, 90 insertions(+), 212 deletions(-)
 create mode 100644 include/dm/platform_data/spi_davinci.h

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2f231fc12b..589484fba0 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -70,6 +70,12 @@ config CADENCE_QSPI
  used to access the SPI NOR flash on platforms embedding this
  Cadence IP core.
 
+config DAVINCI_SPI
+   bool "Davinci & Keystone SPI driver"
+   depends on ARCH_DAVINCI || ARCH_KEYSTONE
+   help
+ Enable the Davinci SPI driver
+
 config DESIGNWARE_SPI
bool "Designware SPI driver"
help
@@ -246,12 +252,6 @@ config FSL_QSPI
  used to access the SPI NOR flash on platforms embedding this
  Freescale IP core.
 
-config DAVINCI_SPI
-   bool "Davinci & Keystone SPI driver"
-   depends on ARCH_DAVINCI || ARCH_KEYSTONE
-   help
- Enable the Davinci SPI driver
-
 config SH_SPI
bool "SuperH SPI driver"
help
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index eda252d0b3..8fa5a22c78 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* SPIGCR0 */
 #define SPIGCR0_SPIENA_MASK0x1
@@ -119,9 +120,6 @@ struct davinci_spi_regs {
 
 /* davinci spi slave */
 struct davinci_spi_slave {
-#ifndef CONFIG_DM_SPI
-   struct spi_slave slave;
-#endif
struct davinci_spi_regs *regs;
unsigned int freq; /* current SPI bus frequency */
unsigned int mode; /* current SPI mode used */
@@ -241,11 +239,43 @@ static int davinci_spi_read_write(struct 
davinci_spi_slave *ds, unsigned
return 0;
 }
 
+static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
+{
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
+
+   debug("%s speed %u\n", __func__, max_hz);
+   if (max_hz > CONFIG_SYS_SPI_CLK / 2)
+   return -EINVAL;
 
-static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
+   ds->freq = max_hz;
+
+   return 0;
+}
+
+static int davinci_spi_set_mode(struct udevice *bus, uint mode)
 {
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
+
+   debug("%s mode %u\n", __func__, mode);
+   ds->mode = mode;
+
+   return 0;
+}
+
+static int davinci_spi_claim_bus(struct udevice *dev)
+{
+   struct dm_spi_slave_platdata *slave_plat =
+   dev_get_parent_platdata(dev);
+   struct udevice *bus = dev->parent;
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
unsigned int mode = 0, scalar;
 
+   if (slave_plat->cs >= ds->num_cs) {
+   printf("Invalid SPI chipselect\n");
+   return -EINVAL;
+   }
+   ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
+
/* Enable the SPI hardware */
writel(SPIGCR0_SPIRST_MASK, >regs->gcr0);
udelay(1000);
@@ -255,7 +285,7 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave 
*ds, int cs)
writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, >regs->gcr1);
 
/* CS, CLK, SIMO and SOMI are functional pins */
-   writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
+   writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK |
SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), >regs->pc0);
 
/* setup format */
@@ -293,20 +323,32 @@ static int __davinci_spi_claim_bus(struct 
davinci_spi_slave *ds, int cs)
return 0;
 }
 
-static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
+static int davinci_spi_release_bus(struct udevice *dev)
 {
+   struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
+
/* Disable the SPI hardware */
writel(SPIGCR0_SPIRST_MASK, >regs->gcr0);
 
return 0;
 }
 
-static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
-   unsigned int bitlen,  const void *dout, void *din,
-   unsigned long flags)
+static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
+   const void *dout, void *din,
+   unsigned long flags)
 {
+   struct dm_spi_slave_platdata *slave =
+   dev_get_parent_platdata(dev);
+   struct udevice *bus = dev->parent;
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
unsigned int len;
 
+   if (slave->cs >= ds->num_cs) {
+   printf("Invalid SPI chipselect\n");
+   return -EINVAL;
+   }
+   ds->cur_cs = slave->cs;
+
if (bitlen == 0)
/* Finish any previously submitted transfers */
goto out;

[U-Boot] [PATCH][[Boards Need to Switch DM] spi: davinci: Full dm conversion

[Jagan Teki]

davinci_spi now support dt along with platform data,
respective boards need to switch into dm for the same.

Signed-off-by: Jagan Teki 
---
 drivers/spi/Kconfig|  12 +-
 drivers/spi/davinci_spi.c  | 275 +
 include/dm/platform_data/spi_davinci.h |  15 ++
 3 files changed, 90 insertions(+), 212 deletions(-)
 create mode 100644 include/dm/platform_data/spi_davinci.h

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2f231fc12b..589484fba0 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -70,6 +70,12 @@ config CADENCE_QSPI
  used to access the SPI NOR flash on platforms embedding this
  Cadence IP core.
 
+config DAVINCI_SPI
+   bool "Davinci & Keystone SPI driver"
+   depends on ARCH_DAVINCI || ARCH_KEYSTONE
+   help
+ Enable the Davinci SPI driver
+
 config DESIGNWARE_SPI
bool "Designware SPI driver"
help
@@ -246,12 +252,6 @@ config FSL_QSPI
  used to access the SPI NOR flash on platforms embedding this
  Freescale IP core.
 
-config DAVINCI_SPI
-   bool "Davinci & Keystone SPI driver"
-   depends on ARCH_DAVINCI || ARCH_KEYSTONE
-   help
- Enable the Davinci SPI driver
-
 config SH_SPI
bool "SuperH SPI driver"
help
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index eda252d0b3..8fa5a22c78 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* SPIGCR0 */
 #define SPIGCR0_SPIENA_MASK0x1
@@ -119,9 +120,6 @@ struct davinci_spi_regs {
 
 /* davinci spi slave */
 struct davinci_spi_slave {
-#ifndef CONFIG_DM_SPI
-   struct spi_slave slave;
-#endif
struct davinci_spi_regs *regs;
unsigned int freq; /* current SPI bus frequency */
unsigned int mode; /* current SPI mode used */
@@ -241,11 +239,43 @@ static int davinci_spi_read_write(struct 
davinci_spi_slave *ds, unsigned
return 0;
 }
 
+static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
+{
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
+
+   debug("%s speed %u\n", __func__, max_hz);
+   if (max_hz > CONFIG_SYS_SPI_CLK / 2)
+   return -EINVAL;
 
-static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
+   ds->freq = max_hz;
+
+   return 0;
+}
+
+static int davinci_spi_set_mode(struct udevice *bus, uint mode)
 {
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
+
+   debug("%s mode %u\n", __func__, mode);
+   ds->mode = mode;
+
+   return 0;
+}
+
+static int davinci_spi_claim_bus(struct udevice *dev)
+{
+   struct dm_spi_slave_platdata *slave_plat =
+   dev_get_parent_platdata(dev);
+   struct udevice *bus = dev->parent;
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
unsigned int mode = 0, scalar;
 
+   if (slave_plat->cs >= ds->num_cs) {
+   printf("Invalid SPI chipselect\n");
+   return -EINVAL;
+   }
+   ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
+
/* Enable the SPI hardware */
writel(SPIGCR0_SPIRST_MASK, >regs->gcr0);
udelay(1000);
@@ -255,7 +285,7 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave 
*ds, int cs)
writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, >regs->gcr1);
 
/* CS, CLK, SIMO and SOMI are functional pins */
-   writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
+   writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK |
SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), >regs->pc0);
 
/* setup format */
@@ -293,20 +323,32 @@ static int __davinci_spi_claim_bus(struct 
davinci_spi_slave *ds, int cs)
return 0;
 }
 
-static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
+static int davinci_spi_release_bus(struct udevice *dev)
 {
+   struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
+
/* Disable the SPI hardware */
writel(SPIGCR0_SPIRST_MASK, >regs->gcr0);
 
return 0;
 }
 
-static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
-   unsigned int bitlen,  const void *dout, void *din,
-   unsigned long flags)
+static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
+   const void *dout, void *din,
+   unsigned long flags)
 {
+   struct dm_spi_slave_platdata *slave =
+   dev_get_parent_platdata(dev);
+   struct udevice *bus = dev->parent;
+   struct davinci_spi_slave *ds = dev_get_priv(bus);
unsigned int len;
 
+   if (slave->cs >= ds->num_cs) {
+   printf("Invalid SPI chipselect\n");
+   return -EINVAL;
+   }
+   ds->cur_cs = slave->cs;
+
if (bitlen == 0)
/* Finish any previously submitted transfers */
goto out;