subject:"\[U\-Boot\] \[PATCH\] ARM\: non\-sec\: flush code cacheline aligned"

Re: [U-Boot] [PATCH] ARM: non-sec: flush code cacheline aligned

2016-08-03 Thread Fabio Estevam

Hi Stefan, On Wed, Aug 3, 2016 at 5:08 PM, Stefan Agner wrote: > From: Stefan Agner > > Flush operations need to be cacheline aligned to take effect, make > sure to flush always complete cachelines. This avoids messages such > as: > CACHE: Misaligned

[U-Boot] [PATCH] ARM: non-sec: flush code cacheline aligned

2016-08-03 Thread Stefan Agner

From: Stefan Agner Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [0090, 009004d9] Signed-off-by: Stefan Agner