jérémy alcim schrieb am Fr., 29. Nov. 2019, 08:32:
> Hi, i think i have find the problem, but i think i doesn't have the
> experience for modifie that.
> on the file : drivers/fpga/ socfpga_gen5.c : line 161 : function
> :
>
>1. we wait fot the return of the fonction with the
>value or
Hi, i think i have find the problem, but i think i doesn't have the
experience for modifie that.
on the file : drivers/fpga/ socfpga_gen5.c : line 161 : function
:
1. we wait fot the return of the fonction with the
value or
2. but he never comming its always the value
then we are
On 10/10/19 7:15 AM, Simon Goldschmidt wrote:
[...]
>>> Have you dropped this? It's assigned to me in patchwork (I'm going
>>> through the list of old items assigned to me...).
>>
>> I don't know, sorry. Apparently there isn't enough information to decide
>> whether this patch is correct or not.
>>
Marek Vasut schrieb am Mi., 9. Okt. 2019, 23:01:
> On 10/9/19 8:06 PM, Simon Goldschmidt wrote:
> [...]
> >>> Based on my understand through this register
> >>> fpga_mgr_fpgamgrdata
> >>> address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
> >>> of
> >>> FIFO
>
On 10/9/19 8:06 PM, Simon Goldschmidt wrote:
[...]
>>> Based on my understand through this register
>>> fpga_mgr_fpgamgrdata
>>> address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
>>> of
>>> FIFO
>>> buffer is mapping to above range addresses.
>> 0xFFCFE7FF-0
Marek,
Am 13.05.2019 um 15:12 schrieb Marek Vasut:
On 5/13/19 2:58 PM, Chee, Tien Fong wrote:
On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
On 5/13/19 2:58 PM, Chee, Tien Fong wrote:
> On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
>> On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
>>>
>>> On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
>
>
> On Tue, 2019-05-07 at
On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
> On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
> > >
> > > On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
>
On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
> On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
>> On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
>>>
>>> On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
>
>
>
>
> On 07.05.
On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
> On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:41, Marek Vasut wrote
On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
>> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
>>>
>>>
>>>
>>> On 07.05.19 21:41, Marek Vasut wrote:
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>
>
>
> On 07.05.19 21:19, Ma
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
>
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
>
On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:41, Marek Vasut wrote:
>> On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>>>
>>>
>>> On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data regist
On 07.05.19 21:41, Marek Vasut wrote:
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, F
On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:19, Marek Vasut wrote:
>> According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
>> (Chapter 5, FPGA Manager, data register) and Arria10 datasheet
>> rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
>> re
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes with
non-incrementing address.
The curren
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes with
non-incrementing address.
The curren
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