Re: [U-Boot] [PATCH] EXYNOS: SMDK5250: Add support for DDR3 memory.
On Wed, Feb 8, 2012 at 3:44 AM, Hatim Ali hatim...@samsung.com wrote: SMDK5250 development boards have different memory variants like DDR3, LPDDR2 and LPDDR3. This patch adds supports for DDR3. The DDR3 is configured for 667Mhz and is being enabled by default. One other note: the SDRAM doesn't appear to be stable with the current CL as is. Specifically, I ran this test: Load two copies of vmlinuz: Hit any key to stop autoboot: 0 SMDK5250 # mmc rescan 0 SMDK5250 # fatload mmc 0:c 0x4200 vmlinuz reading vmlinuz 3272888 bytes read SMDK5250 # fatload mmc 0:c 0x40008000 vmlinuz reading vmlinuz 3272888 bytes read Now compare them: SMDK5250 # cmp.l 0x40008000 0x4200 3272888 word at 0x400097fc (0xe3160024) != word at 0x420017fc (0xe3160020) Total of 1535 words were the same ...but if you look at that memory, it's the same! SMDK5250 # md.l 0x420017fc 1 420017fc: e3160020 ... SMDK5250 # md.l 0x400097fc 1 400097fc: e3160020 ... ...in this case, re-running the cmp.l still showed the difference (?) Running RAM at 400MHz didn't show the same problem. NOTE: that doesn't prove the the problem is related to SDRAM stability, but it sure looks suspicious. -Doug ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] EXYNOS: SMDK5250: Add support for DDR3 memory.
Dear Hatim,
On 8 February 2012 17:14, Hatim Ali hatim...@samsung.com wrote:
SMDK5250 development boards have different memory variants like
DDR3, LPDDR2 and LPDDR3. This patch adds supports for DDR3.
The DDR3 is configured for 667Mhz and is being enabled by default.
This patch is based on Chander Kashyap's v9 patchset.
(http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/124396)
Signed-off-by: Hatim Ali hatim...@samsung.com
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..50a17cb 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,11 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
+ifdef CONFIG_DDR3
+COBJS += dmc_init_ddr3.o
+else
COBJS += dmc_init.o
+endif
COBJS += tzpc_init.o
ifndef CONFIG_SPL_BUILD
diff --git a/board/samsung/smdk5250/dmc_init.c
b/board/samsung/smdk5250/dmc_init.c
index 7881074..160d86e 100644
--- a/board/samsung/smdk5250/dmc_init.c
+++ b/board/samsung/smdk5250/dmc_init.c
@@ -248,7 +248,7 @@ static void config_rdlvl(struct exynos5_dmc *dmc,
* ctrl_gateduradj, rdlvl_pass_adj
* rdlvl_rddataPadj
*/
- val = SET_RDLVL_RDDATAPADJ;
+ val = SET_RDLVL_RDDATA_ADJ;
writel(val, phy0_ctrl-phy_con1);
writel(val, phy1_ctrl-phy_con1);
@@ -361,8 +361,8 @@ void mem_ctrl_init()
config_zq(phy0_ctrl, phy1_ctrl);
/* Operation Mode : LPDDR2 */
- val = PHY_CON0_RESET_VAL;
- SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
+ val = CTRL_DDR_MODE(LPDDR2);
+ val |= BYTE_RDLVL_EN;
writel(val, phy0_ctrl-phy_con0);
writel(val, phy1_ctrl-phy_con0);
Spilt the patch in two. One related to dmc_init.c and second for ddr3 support.
diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c
b/board/samsung/smdk5250/dmc_init_ddr3.c
new file mode 100644
index 000..da42dd2
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_init_ddr3.c
@@ -0,0 +1,464 @@
+/*
+ * DDR3 Memory setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include config.h
+#include asm/io.h
+#include asm/arch/dmc.h
+#include asm/arch/clock.h
+#include asm/arch/cpu.h
+#include setup.h
+
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_677*/
+/* LPDDR support: DDR3 */
+
+static void dmc_directcmd_PALL(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, chip, mask = 0, val;
+
+ /* Sending PALL cmd on
+ * Channel0-Chip0
+ * Channel0-Chip1
+ * Channel1-Chip0
+ * Channel1-Chip1
+ */
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ SET_CMD_CHANNEL(mask, channel);
+ for (chip = 0; chip CONFIG_CHIPS_PER_CHANNEL; chip++) {
+ SET_CMD_CHIP(mask, chip);
+ val = DIRECT_CMD_PALL | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+ }
+ }
+
+}
+
+
+static void dmc_directcmd(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, mask = 0, val;
+
+ /* Selecting Channel0-Chip0 */
+ SET_CMD_CHANNEL(mask, 0);
+ SET_CMD_CHIP(mask, 0);
+
+ /* Sending NOP cmd on Channel0-Chip0 */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ dmc_directcmd_PALL(dmc);
+
+ /* Selecting Chip 0*/
+ mask = 0;
+ SET_CMD_CHIP(mask, 0);
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ /* Selecting Channel */
+ SET_CMD_CHANNEL(mask, channel);
+
+ if (channel == 1) {
+ /* Sending NOP cmd on Channel1-Chip0 */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+ }
+ /* Sending MRS/EMRS command and ZQINIT command
+ * on Channel0-Chip0
+ */
+ val =
Re: [U-Boot] [PATCH] EXYNOS: SMDK5250: Add support for DDR3 memory.
Hatim,
Overall comments:
* Random delays are evil. Please explain each sdelay() call. Be sure
to include information about why exactly 65,536 iterations through a
delay loop is necessary in each case.
* For functions that are nearly the same between dmc_init.c and
dmc_init_ddr3.c should be unified. If possible, unify everything.
* If we really need to have two files, please submit a separate patch
to rename dmc_init.c to dmc_init_lpddr2.c
* If we really need to have two files, please reorder functions so
that functions that are in both dmc_init_ddr3.c and in
dmc_init_lpddr2.c are in the same order for easy diffing.
* In general, avoid defining hex registers. Instead, define things
symbolically. See comments about DMC_MEMCONTROL_VAL below as an
example.
* I've started reviewing this before the patches from Chander. I'll
probably go back and review that next, if I have time. Expect similar
comments there.
See below for some scattered comments. Note that I didn't fully
review everything, so I'd expect another round will be needed.
On Wed, Feb 8, 2012 at 3:44 AM, Hatim Ali hatim...@samsung.com wrote:
--- a/board/samsung/smdk5250/dmc_init.c
+++ b/board/samsung/smdk5250/dmc_init.c
@@ -248,7 +248,7 @@ static void config_rdlvl(struct exynos5_dmc *dmc,
* ctrl_gateduradj, rdlvl_pass_adj
* rdlvl_rddataPadj
*/
- val = SET_RDLVL_RDDATAPADJ;
+ val = SET_RDLVL_RDDATA_ADJ;
This doesn't seem related to DDR3. Perhaps it should be split into a
separate patch?
@@ -361,8 +361,8 @@ void mem_ctrl_init()
config_zq(phy0_ctrl, phy1_ctrl);
/* Operation Mode : LPDDR2 */
- val = PHY_CON0_RESET_VAL;
- SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
+ val = CTRL_DDR_MODE(LPDDR2);
+ val |= BYTE_RDLVL_EN;
I'd prefer this (and related header change) to be in a separate patch as well.
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_677*/
+/* LPDDR support: DDR3 */
I assume that future CLs will relax some of these restrictions?
+ /* Sending PALL cmd on
+ * Channel0-Chip0
+ * Channel0-Chip1
+ * Channel1-Chip0
+ * Channel1-Chip1
+ */
nit: please use proper commenting style. AKA:
/*
* Sending PALL cmd on
* - Channel0-Chip0
* - Channel0-Chip1
* - Channel1-Chip0
* - Channel1-Chip1
*/
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ SET_CMD_CHANNEL(mask, channel);
+ for (chip = 0; chip CONFIG_CHIPS_PER_CHANNEL; chip++) {
+ SET_CMD_CHIP(mask, chip);
+ val = DIRECT_CMD_PALL | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
As with all sdelays, please explain.
+ }
+ }
+
+}
+
+
+static void dmc_directcmd(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, mask = 0, val;
+
+ /* Selecting Channel0-Chip0 */
+ SET_CMD_CHANNEL(mask, 0);
+ SET_CMD_CHIP(mask, 0);
+
+ /* Sending NOP cmd on Channel0-Chip0 */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ dmc_directcmd_PALL(dmc);
+
+ /* Selecting Chip 0*/
+ mask = 0;
+ SET_CMD_CHIP(mask, 0);
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ /* Selecting Channel */
+ SET_CMD_CHANNEL(mask, channel);
+
+ if (channel == 1) {
+ /* Sending NOP cmd on Channel1-Chip0 */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+ }
+ /* Sending MRS/EMRS command and ZQINIT command
+ * on Channel0-Chip0
+ */
+ val = DIRECT_CMD_MRS1 | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ val = DIRECT_CMD_MRS2 | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ val = DIRECT_CMD_MRS3 | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ val = DIRECT_CMD_MRS4 | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ val = DIRECT_CMD_ZQINIT | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+ }
+}
+
+static void update_reset_dll(struct exynos5_dmc *dmc)
+{
* Unify with LPDDR2 version and/or explain differences.
+static void config_memory(struct exynos5_dmc *dmc)
+{
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 8
+ * Number of chips: 1
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 0 Cycle
+ */
+ writel(DMC_MEMCONTROL_VAL,
Re: [U-Boot] [PATCH] EXYNOS: SMDK5250: Add support for DDR3 memory.
Dear Chander,
Thanks for your review.
Please find inline my replies to your comments.
On Thu, Feb 9, 2012 at 6:44 PM, Chander Kashyap
chander.kash...@linaro.orgwrote:
Dear Hatim,
On 8 February 2012 17:14, Hatim Ali hatim...@samsung.com wrote:
SMDK5250 development boards have different memory variants like
DDR3, LPDDR2 and LPDDR3. This patch adds supports for DDR3.
The DDR3 is configured for 667Mhz and is being enabled by default.
This patch is based on Chander Kashyap's v9 patchset.
(http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/124396)
Signed-off-by: Hatim Ali hatim...@samsung.com
diff --git a/board/samsung/smdk5250/Makefile
b/board/samsung/smdk5250/Makefile
index 226db1f..50a17cb 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,11 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
+ifdef CONFIG_DDR3
+COBJS += dmc_init_ddr3.o
+else
COBJS += dmc_init.o
+endif
COBJS += tzpc_init.o
ifndef CONFIG_SPL_BUILD
diff --git a/board/samsung/smdk5250/dmc_init.c
b/board/samsung/smdk5250/dmc_init.c
index 7881074..160d86e 100644
--- a/board/samsung/smdk5250/dmc_init.c
+++ b/board/samsung/smdk5250/dmc_init.c
@@ -248,7 +248,7 @@ static void config_rdlvl(struct exynos5_dmc *dmc,
* ctrl_gateduradj, rdlvl_pass_adj
* rdlvl_rddataPadj
*/
- val = SET_RDLVL_RDDATAPADJ;
+ val = SET_RDLVL_RDDATA_ADJ;
writel(val, phy0_ctrl-phy_con1);
writel(val, phy1_ctrl-phy_con1);
@@ -361,8 +361,8 @@ void mem_ctrl_init()
config_zq(phy0_ctrl, phy1_ctrl);
/* Operation Mode : LPDDR2 */
- val = PHY_CON0_RESET_VAL;
- SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
+ val = CTRL_DDR_MODE(LPDDR2);
+ val |= BYTE_RDLVL_EN;
writel(val, phy0_ctrl-phy_con0);
writel(val, phy1_ctrl-phy_con0);
Spilt the patch in two. One related to dmc_init.c and second for ddr3
support.
Sure, will do that in my next patch-set.
diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c
b/board/samsung/smdk5250/dmc_init_ddr3.c
new file mode 100644
index 000..da42dd2
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_init_ddr3.c
@@ -0,0 +1,464 @@
+/*
+ * DDR3 Memory setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include config.h
+#include asm/io.h
+#include asm/arch/dmc.h
+#include asm/arch/clock.h
+#include asm/arch/cpu.h
+#include setup.h
+
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_677*/
+/* LPDDR support: DDR3 */
+
+static void dmc_directcmd_PALL(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, chip, mask = 0, val;
+
+ /* Sending PALL cmd on
+ * Channel0-Chip0
+ * Channel0-Chip1
+ * Channel1-Chip0
+ * Channel1-Chip1
+ */
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ SET_CMD_CHANNEL(mask, channel);
+ for (chip = 0; chip CONFIG_CHIPS_PER_CHANNEL; chip++) {
+ SET_CMD_CHIP(mask, chip);
+ val = DIRECT_CMD_PALL | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+ }
+ }
+
+}
+
+
+static void dmc_directcmd(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, mask = 0, val;
+
+ /* Selecting Channel0-Chip0 */
+ SET_CMD_CHANNEL(mask, 0);
+ SET_CMD_CHIP(mask, 0);
+
+ /* Sending NOP cmd on Channel0-Chip0 */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ dmc_directcmd_PALL(dmc);
+
+ /* Selecting Chip 0*/
+ mask = 0;
+ SET_CMD_CHIP(mask, 0);
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ /* Selecting Channel */
+ SET_CMD_CHANNEL(mask, channel);
+
+ if (channel == 1) {
+ /*
[U-Boot] [PATCH] EXYNOS: SMDK5250: Add support for DDR3 memory.
SMDK5250 development boards have different memory variants like
DDR3, LPDDR2 and LPDDR3. This patch adds supports for DDR3.
The DDR3 is configured for 667Mhz and is being enabled by default.
This patch is based on Chander Kashyap's v9 patchset.
(http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/124396)
Signed-off-by: Hatim Ali hatim...@samsung.com
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..50a17cb 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,11 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
+ifdef CONFIG_DDR3
+COBJS += dmc_init_ddr3.o
+else
COBJS += dmc_init.o
+endif
COBJS += tzpc_init.o
ifndef CONFIG_SPL_BUILD
diff --git a/board/samsung/smdk5250/dmc_init.c
b/board/samsung/smdk5250/dmc_init.c
index 7881074..160d86e 100644
--- a/board/samsung/smdk5250/dmc_init.c
+++ b/board/samsung/smdk5250/dmc_init.c
@@ -248,7 +248,7 @@ static void config_rdlvl(struct exynos5_dmc *dmc,
* ctrl_gateduradj, rdlvl_pass_adj
* rdlvl_rddataPadj
*/
- val = SET_RDLVL_RDDATAPADJ;
+ val = SET_RDLVL_RDDATA_ADJ;
writel(val, phy0_ctrl-phy_con1);
writel(val, phy1_ctrl-phy_con1);
@@ -361,8 +361,8 @@ void mem_ctrl_init()
config_zq(phy0_ctrl, phy1_ctrl);
/* Operation Mode : LPDDR2 */
- val = PHY_CON0_RESET_VAL;
- SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
+ val = CTRL_DDR_MODE(LPDDR2);
+ val |= BYTE_RDLVL_EN;
writel(val, phy0_ctrl-phy_con0);
writel(val, phy1_ctrl-phy_con0);
diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c
b/board/samsung/smdk5250/dmc_init_ddr3.c
new file mode 100644
index 000..da42dd2
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_init_ddr3.c
@@ -0,0 +1,464 @@
+/*
+ * DDR3 Memory setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include config.h
+#include asm/io.h
+#include asm/arch/dmc.h
+#include asm/arch/clock.h
+#include asm/arch/cpu.h
+#include setup.h
+
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_677*/
+/* LPDDR support: DDR3 */
+
+static void dmc_directcmd_PALL(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, chip, mask = 0, val;
+
+ /* Sending PALL cmd on
+ * Channel0-Chip0
+ * Channel0-Chip1
+ * Channel1-Chip0
+ * Channel1-Chip1
+ */
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ SET_CMD_CHANNEL(mask, channel);
+ for (chip = 0; chip CONFIG_CHIPS_PER_CHANNEL; chip++) {
+ SET_CMD_CHIP(mask, chip);
+ val = DIRECT_CMD_PALL | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+ }
+ }
+
+}
+
+
+static void dmc_directcmd(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, mask = 0, val;
+
+ /* Selecting Channel0-Chip0 */
+ SET_CMD_CHANNEL(mask, 0);
+ SET_CMD_CHIP(mask, 0);
+
+ /* Sending NOP cmd on Channel0-Chip0 */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ dmc_directcmd_PALL(dmc);
+
+ /* Selecting Chip 0*/
+ mask = 0;
+ SET_CMD_CHIP(mask, 0);
+ for (channel = 0; channel CONFIG_DMC_CHANNELS; channel++) {
+ /* Selecting Channel */
+ SET_CMD_CHANNEL(mask, channel);
+
+ if (channel == 1) {
+ /* Sending NOP cmd on Channel1-Chip0 */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+ }
+ /* Sending MRS/EMRS command and ZQINIT command
+ * on Channel0-Chip0
+ */
+ val = DIRECT_CMD_MRS1 | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ val = DIRECT_CMD_MRS2 | mask;
+ writel(val, dmc-directcmd);
+ sdelay(0x1);
+
+ val = DIRECT_CMD_MRS3 | mask;
+
